3 Development Board Circuit
3.4 Clock, Reset
DBUG377-1.0E
13(21)
3.3.3
FPGA Power Pinout
Table 3-2 FPGA Power Pinout
Name
Pin No.
BANK
Description
I/O Level
VCCO0
78
0
I/O Bank Voltage
2.5V
VCCO1
12, 67
1
I/O Bank Voltage
3.3V
VCCO2
3, 64
2
I/O Bank Voltage
1.8V
VCCO3
58
3
I/O Bank Voltage
3.3V
VCCO4
44
4
I/O Bank Voltage
3.3V
VCCO5
23
5
I/O Bank Voltage
2.5V
VCCO6
12, 67
6
I/O Bank Voltage
3.3V
VCCO7
3, 64
7
I/O Bank Voltage
1.8V
VCCPLLL1
14
-
PLLL1 power
1.0V
VCCPLLR1 50
-
PLLR1 power
1.0V
VCCX
12, 67
-
Auxiliary voltage
and VCCO1, VCCO6
are internal
connected.
3.3V
VCC
1, 22, 45,
66
-
Core voltage
1.0V
VSS
2, 21, 24,
43, 46, 65,
68
-
GND
-
3.4
Clock, Reset
3.4.1
Overview
The development board provides a 27MHz crystal oscillator connected
to the PLL input pin. This can be employed as the input clock for the PLL in
FPGA. Frequency division and multiplication of PLL can provide the clock
required by the user.
For easier debugging, one reset signal active-low, is added on the
development board.
