GD32W51x User Manual
805
shows the operation for an interrupt during a 4-bit multi-block read and
Multiple block 4-Bit write interrupt cycle timing
shows the operation for an interrupt during
a 4-bit multi-block write
Figure 23-17. Multiple block 4-Bit read interrupt cycle timing
SDIO_CK
D0
Command read data
CMD
D1
D1(mode)
S
E
Response
S
E
Data
S
E
interrupt
data
data
int
Data
S
E
Data
S
E
Data
S
E
int
2 CLK
2 CLK
data
Figure 23-18. Multiple block 4-Bit write interrupt cycle timing
SDIO_CK
D0
CMD
D1
D1(mode)
interrupt
data
interrupt
2 CLK
2 CLK
CRC
S
E
Command writ e data
S
E
Response
S
E
Data
S
E
Data
S
E
Data
S
E
Data
S
E
CRC
S
E
2 CLK
data
interrupt
23.7.2.
CE-ATA specific operations
The CE-ATA device supports these specific operations:
Receive command completion signal
Send command completion disable signal
The SDIO supports these operations only when SDIO_CMDCTL[14] is set.
Command completion signal
CE-ATA defines a command completion signal that the device uses to notify the host upon
normal ATA
command completion or when ATA command termination has occurred due to
an error condition the device has encountered.
If the
‘
enable CMD completion
’
bit SDIO_CMDCTL[12] is set and the
‘
not interrupt Enable
’
bit
SDIO_CMDCTL[13] is reset, the CSM waits for the command completion signal in the
Waitcompl state.
When start bit is received on the CMD line, the CSM enters the Idle state. No new command
can be sent for 7 bit cycles. Then, for the last 5 cycles (out of the 7) the CMD line is driven
to
‘
1
’
in push-pull mode.
After the host
detects a command completion signal from the device, it should issue a
FAST_IO (CMD39) command to read the ATA Status register to determine the ending status
for the ATA command.
