GD32F20x User Manual
873
These bits indicate the number of frames dropped by RxFIFO
16
Reserved
Must be kept at reset value
15:0
MSFC[15:0]
Missed frames by the controller bits
These bits indicate the number of frames missed by the RxDMA controller because
of the unavailable receive buffer. Each time the RxDMA controller flushes one
frame, this counter will plus 1.
27.4.51.
DMA
current
transmit
descriptor
address
register
(ENET_DMA_CTDADDR)
Address offset: 0x1048
Reset value: 0x0000 0000
This register points to the start descriptor address of the current transmit descriptor read by
the TxDMA controller.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TDAP[31:16]
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TDAP[15:0]
r
Bits
Fields
Descriptions
31:0
TDAP[31:0]
Transmit descriptor address pointer bits
These bits are automatically updated by TxDMA controller during operation.
27.4.52.
DMA
current
receive
descriptor
address
register
(ENET_DMA_CRDADDR)
Address offset: 0x104C
Reset value: 0x0000 0000
This register points to the start descriptor address of the current receive descriptor read by
the RxDMA controller.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RDAP[31:16]
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RDAP[15:0]
r
Summary of Contents for GD32F20 Series
Page 191: ...GD32F20x User Manual 191 Bits Fields Descriptions 31 0 TRNDATA 31 0 32 Bit Random data ...
Page 290: ...GD32F20x User Manual 290 conversion is ongoing ...
Page 325: ...GD32F20x User Manual 325 15 0 ALRM 15 0 RTC alarm value low ...
Page 385: ...GD32F20x User Manual 385 ...
Page 523: ...GD32F20x User Manual 523 clears AERR bit by writing 0 to it ...