GigaDevice Semiconductor GD32F20 Series, User Manual

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GD32F20x User Manual
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Figure 25-25. SQPI-PSRAM access
Data
(EXMC_D[0])
Data
(EXMC_D[1])
Clock
(EXMC_CLK)
Chip Enable
(EXMC_NEx)
Data
(EXMC_D[2])
Data
(EXMC_D[3])
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Command, width
depends on CMDBIT
Address, 24-bits Data 1 Data 2 Wait
Command
6. QPI-PSRAM access timing
The only difference between SQPI and QPI mode is that the command is sent parallel on the
4 data IO lines as shown in the diagram below.
The following QPI-PSRAM waveforms are configured with:
ADRBIT[4:0] = 24,
CMDBIT[1:0] = 1,
Figure 25-26. QPI-PSRAM access
Data
(EXMC_D[0])
Data
(EXMC_D[1])
Clock
(EXMC_CLK)
Chip Enable
(EXMC_NEx)
Data
(EXMC_D[2])
Data
(EXMC_D[3])
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Command Address Data 1 Data 2 Wait
0
1
2
3
4
5
6
7
25.3.5. NAND flash or PC card controller
EXMC has partitioned Bank1 and Bank2 as NAND Flash access field, bank3 as PC Card
access field. Each bank has its own set of control register for access timing configuration. 8-
and 16-bit NAND Flash and 16-bit PC Card are supported. An ECC hardware is provided for
the NAND Flash controller to ensure the robustness of data transfer and storage.