User Manual
GD32450I-EVAL
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4.12
Ethernet
TX_CLK
1
TX_EN
2
TXD_0
3
TXD_1
4
TXD_2
5
TXD_3/SNI_MODE
6
PWR_DOWN/INT
7
NC
8
NC
9
NC
10
NC
11
NC
12
RD-
13
RD+
14
AGND
15
TD-
16
TD+
17
PFBIN1
18
AGND
19
NC
20
NC
21
AVDD33
22
PFBOUT
23
RBIAS
24
25MHz_OUT
25
LED_ACT/COL/AN_EN
26
LED_SPEED/AN1
27
LED_LINK/AN0
28
RESET_N
29
MDIO
30
MDC
31
IOVDD33
32
X2
33
X1
34
IOGND
35
DGND
36
PFBIN2
37
RX_CLK
38
RX_DV/MII_MODE
39
CRS/CRS_DV/LED_CFG
40
RX_ER/MDIX_EN
41
COL/PHYAD0
42
RXD_0/PHYAD1
43
RXD_1/PHYAD2
44
RXD_2/PHYAD3
45
RXD_3/PHYAD4
46
IOGND
47
IOVDD33
48
U8
DP83848CVV
+3V3
R32
2.2K
Ω
RMII MODE
R33
1.5K
Ω
+3V3
NRST
R40 2.2K
Ω
+3V3
R41
4.87K
Ω
GND
E3
16V/10uF,AVX
C37
50
V
/0
.1
uF
C38
50
V
/0
.1
uF
C39
50
V
/0
.1
uF
GND
GND
+3V3
R38
2.2K
Ω
R39
2.2K
Ω
+3V3
R34
2.2K
Ω
R35
2.2K
Ω
R36
2.2K
Ω
+3V3
TD+
1
4
TD-
2
RD+
3
5
RD-
6
L+
9
L-
10
R+
12
R-
11
GND1
13
GND2
14
JP16
HR911105A
GND
+3V3
R26
49.9
Ω
R27
49.9
Ω
R28
49.9
Ω
R29
49.9
Ω
C36
50V/0.1uF
C35
50V/0.1uF
GND
GND
R30
240
Ω
R31
240
Ω
C40
50V/0.1uF
C41
50V/0.1uF
C42
50V/0.1uF
+3V3
GND
PC4
PC5
PA1
MCO
RMII_TX_EN
RMII_TXD0
RMII_TXD1
RMII_RXD0
RMII_RXD1
RMII_CRS_DV
RMII_MDC
RMII_MDIO
RMII_REF_CLK
RMII_TX_EN
RMII_TXD0
RMII_TXD1
RMII_RXD0
RMII_RXD1
RMII_MDC
RMII_MDIO
RMII_REF_CLK
RMII_CRS_DV
RP2
33
Ω
RP3
33
Ω
PA8
PA8 is an AFIO, refer to DCI schematic for right config
Ethernet
PA7
PA2
PG11
PG13
PG14
PG11
、
PG13
、
PG14 are AFIOs, please refer to SPI schematic for right config
1
2
3
JP17
HEADER 3
EXMC_SDCKE0
Short JP17(1,2) for Ethnet function
Short JP17(2,3) for SDRAM function
PC1
1
2
3
JP18
HEADER 3
Short JP18(1,2) for Ethnet function
Short JP18(2,3) for I2S function
I2S1_SD
4.13
SDIO
R37
10K
Ω
R42
10K
Ω
R45
10K
Ω
R46
10K
Ω
+3V3
+3V3
E5
16V/10uF,AVX
GND
PD2
PC12
SDIO_DAT3
SDIO_CMD
SDIO_CLK
SDIO_DAT0
SDIO_DAT1
SDIO_DAT3
SDIO_CMD
SDIO_CLK
SDIO_DAT0
SDIO_DAT1
SDIO_DAT2
D2
1
D3
2
CMD
3
VCC
4
CLK
5
GND
6
D0
7
D1
8
CD
9
JP32
TF_CARD_SOCKET
+3V3
SDIO
GND
SDIO_DAT2
PC10
PC8
PC9
PC11
PC8
SDIO_DAT0
DCI_D2
PC9
SDIO_DAT1
DCI_D3
PC11
SDIO_DAT2
DCI_D4