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BIOS Setup
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Parameter
Description
NBIO RAS Common Options
Press [Enter] for more options.
NBIO RAS Global Control
– Options available: Manual/Auto. Default option is
Auto
.
NBIO RAS Control
– 0 = Disabled, 1 = MCA, 2 = Legacy.
– Options available: Disabled/MCA/Legacy. Default option is
MCA
.
Egress Poison Severity High
– Enter a value. Each bit set to 1 enables high severity on the
associated IOHC egress port. A bit of 0 indicates low severity.
Egress Poison Severity Low
– Enter a value. Each bit set to 1 enables high severity on the
associated IOHC egress port. A bit of 0 indicates low severity.
NBIO SyncFlood Generation
– This value may be used to mask SyncFlood caused by NBIO RAS
options. When set to TRUE SyncFlood from NBIO is masked.
When set to FALSE NBIO is capable of generating SyncFlood.
– Options available: Enabled/Disabled/Auto. Default option is
Auto
.
NBIO SyncFlood Reporting
– This value may be used to enable SyncFlood reporting to APML.
When set to TRUE SyncFlood will be reported to APML. When set
to FALSE that reporting will be disabled.
– Options available: Enabled/Disabled. Default option is
Disabled
.
Egress Poison Mask High
– Enter a value. These set the enable mask for masking of errors
logged in EGRESS_POISON_STATUS. For each bit set to 1,
errors are masked. For each bit set to 0, errors trigger response
actions.
Egress Poison Mask Low
– Enter a value. These set the enable mask for masking of errors
logged in EGRESS_POISON_STATUS. For each bit set to 1,
errors are masked. For each bit set to 0, errors trigger response
actions.
Uncorrected Converted to Poison Enable Mask High
– Enter a value. These set the enable mask for masking of
uncorrectable parity errors on internal arrays. For each bit set to
1, a system fatal error event is triggered for UCP errors on arrays
associated with that egress port. For each bit set to 0, errors are
masked.
Uncorrected Converted to Poison Enable Mask Low
– Enter a value. These set the enable mask for masking of
uncorrectable parity errors on internal arrays. For each bit set to
1, a system fatal error event is triggered for UCP errors on arrays
associated with that egress port. For each bit set to 0, errors are
masked.
Summary of Contents for G482-Z50
Page 1: ...G482 Z50 G482 Z51 AMD EPYCTM 7002 Series Processor Server User Manual Rev 1 0 ...
Page 16: ...Hardware Installation 16 1 3 System Block Diagram 1 3 1 G482 Z50 1 3 2 G482 Z51 ...
Page 30: ...System Hardware Installation 30 3 4 5 ...
Page 31: ... 31 System Hardware Installation 6 6 6 ...
Page 33: ... 33 System Hardware Installation 3 5 4 ...
Page 35: ... 35 System Hardware Installation 2 3 ...
Page 48: ...System Hardware Installation 48 4 ...
Page 54: ...System Hardware Installation 54 G482 Z51 1 2 3 2 1 3 Motherboard to 2 5 HDD Backplane Board ...
Page 80: ...BIOS Setup 80 5 2 13 SATA Configuration ...
Page 85: ... 85 BIOS Setup 5 2 18 Intel R I350 Gigabit Network Connection ...
Page 87: ... 87 BIOS Setup 5 2 19 VLAN Configuration ...
Page 91: ... 91 BIOS Setup 5 2 22 Intel R Ethernet Controller X550 ...