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CHAPTER 4: PCI INTERFACE
4.0
PCI Interface Registers
The PMC/PCI interface is handled by a PCI9056 I/O Accelerator from PLX Technology. The PCI interface is
compliant with the 5V, 66MHz 32-bit PCI Specification 2.2. The PCI9056 provides dual DMA controllers for fast
data transfers to and from the on-board FIFOs. Fast DMA burst accesses provide for a maximum burst throughput of
264MB/s to the PCI interface. To reduce CPU overhead during DMA transfers, the controller also implements
Chained (Scatter/Gather) DMA, as well as Demand Mode DMA.
Since many features of the PCI9056 are not utilized in this design, it is beyond the scope of this document to
duplicate the PCI9056 User’s Manual. Only those features, which will clarify areas specific to the PCIe-SIO4BX2
are detailed here. Please refer to the PCI9056 User’s Manual (See Related Publications) for more detailed
information. Note that the BIOS configuration and software driver will handle most of the PCI9056 interface.
Unless the user is writing a device driver, the details of this PCI Interface Chapter may be skipped.
4.1
PCI Registers
The PLX 9056 contains many registers, many of which have no effect on the SIO4BX2 performance. The following
section attempts to filter the information from the PCI9056 manual to provide the necessary information for a
SIO4BX2 specific driver.
The SIO4BX2 uses an on-board serial EEPROM to initialize many of the PCI9056 registers after a PCI Reset. This
allows board specific information to be preconfigured correctly.
4.1.1 PCI Configuration Registers
The PCI Configuration Registers allow the PCI controller to identify and control the cards in a system.
PCI device identification is provided by the Vendor ID/Device ID (Addr 0x0000) and Sub-Vendor ID/Sub-Device
ID Registers (0x002C). The following definitions are unique to the General Standards SIO4BX2 boards. All drivers
should verify the ID/Sub-ID information before attaching to this card. These values are fixed via the Serial
EEPROM load following a PCI Reset, and cannot be changed by software.
Vendor ID
0x10B5
PLX Technology
Device ID
0x9056
PCI9056
Sub-Vendor ID
0x10B5
PLX Technology
Sub-Device ID
0x3198
GSC SIO4B
The configuration registers also setup the PCI IO and Memory mapping for the SIO4BX2. The PCI9056 is setup to
use PCIBAR0 and PCIBAR1 to map the internal PLX registers into PCI Memory and IO space respectively.
PCIBAR2 will map the Local Space Registers into PCI memory space, and PCIBAR3 is unused. Typically, the OS
will configure the PCI configuration space.
For further information of the PCI configuration registers, please consult the PLX Technology PCI9056 Manual.
