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Gemlight GMB-486UN, User Manual

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  GMB-486UN
  80486 Mainboard
  User's Guide

  Version  3.00

Summary of Contents for GMB-486UN

Page 1: ...GMB 486UN 80486 Mainboard User s Guide Version 3 00...

Page 2: ...des provides references for all POST communicate errors TRADEMARKS USED IN THIS MANUAL MS DOS XENIX Microsoft WINDOWS are trademarks of Microsoft Corp NOVELL Netware are trademarks of Novell Inc Words...

Page 3: ...1 Touch an unpainted area of the system chassis before handling the mainboard or any component Doing so discharges the static charge user s body may have built 2 Remove the mainboard from its anti st...

Page 4: ...PER SETTING 6 2 3 5 INSTALLING CACHE CHIPS 7 2 4 JP12 DISPLAY ADAPTER SETUP 8 2 5 JP2 DISCHARGE CMOS SETUP 9 2 6 JP10 SOURCE OF GA20 9 2 7 MEMORY INSTALLATION 10 2 7 1 INSTALLING SIMM 11 CHAPTER 3 MAI...

Page 5: ...UP 19 4 2 ADVANCED CMOS SETUP 21 4 3 ADVANCED CHIPSET SETUP 22 4 4 AUTO CONFIGURATION WITH BIOS DEFAULTS 26 4 5 AUTO CONFIGURATION WITH POWER ON DEFAULTS 26 4 6 CHANGE PASSWORD 27 4 7 HARD DISK UTILIT...

Page 6: ...Hz or 80486DX2 25MHz 33MHz microprocessor with 32 bit access to data High performance single chip core logic with Internal Cache Controller Built in direct mapped secondary cache controller with optio...

Page 7: ...and system Configuration User Defined Password to inhibit illegal access 1 2 MAINBOARD COMPONENTS This section gives a brief description of key components on the mainboard Refer to Fig 1 for component...

Page 8: ...and how to install memory modules Before beginning the configuration user should take the following precautions Turn off the power supply and unplug the power cord before begin Unplug all cables that...

Page 9: ...illator is used instead 2 3 CACHE CONFIGURATION The special feature of the GMB 486UN mainboard is a built in direct mapped cache controller with optional write back or write through operation which su...

Page 10: ...uires 25ns tag and 25ns data SRAM chips 25MHz CPU requires 35ns tag and 35ns data SRAM chips 2 3 2 CACHE SIZE AND MEMORY LOCATIONS The table below describes the chip capacity and socket location requi...

Page 11: ...HIP SOCKETS AND JUMPER LOCATIONS 2 3 4 JP22 JP23 JP25 30 CACHE JUMPER SETTING Cache memory is configured using jumpers JP22 JP23 and JP25 JP30 JP22 JP23 and JP25 JP30 Cache Size Setup Fig 3 Cache Jump...

Page 12: ...Hardware Configuration...

Page 13: ...w the section on static electricity precautions at the beginning of this manual and make sure that power to the mainboard is off 2 Align the chip so that the notched corner of the chip matches the not...

Page 14: ...er JP12 to configure the mainboard for either a color display card or a monochrome display card Short the jumper for a color display adapter Open the jumper for a monochrome display adapter Refer to F...

Page 15: ...Chapter 2 Table 4...

Page 16: ...2 for the location of JP2 JP2 Discharge CMOS Setup 2 6 JP10 SOURCE OF GA20 The source of GA20 can be selected by JP10 when emulation fast gate A20 is selected the system performance may optimize unde...

Page 17: ...Chapter 2 Table 6...

Page 18: ...ser can install either a 256K 1M or 4M SIMM in each socket Note that all SIMM modules in a bank must be the same capacity SIMM speed required for best performance depends on the CPU speed which requir...

Page 19: ...the SIMM module so that the pin 1 marking on the module corresponds to the socket pin 1 marking 3 Hold the module at a 70 degree angle to the socket and insert the module s connectors into the socket...

Page 20: ...onfiguration 5 To fill a bank repeat steps 1 through 4 until the sockets in each bank contain SIMMs 6 After installing memory run BIOS Setup to indicate to the system for how much memory the user has...

Page 21: ...board 3 1 COMPONENTS The following components are recommended Case with standard chassis and hardware The GMB 486UN fits most AT compatible cases Standard AT power supply 8 ohm speaker Floppy disk dri...

Page 22: ...inboard Make sure to access the keyboard connector J1 once the board is installed 5 From the bottom of the mainboard insert stand offs into the proper holes on the board and attach the mounting screws...

Page 23: ...connector has two six pin male header connectors Plug the dual connectors from the power directly onto the board connector J2 J3 Pin Description Pin Description 1 Power Good 1 Ground 2 5V DC 2 Ground...

Page 24: ...nd Table 9 3 5 3 JP15 TURBO SWITCH CONNECTOR JP15 connects to Turbo switch which is used to select the mainboard s clock speed Setting Description Open Normal Mode Short default Turbo Mode Table 10 3...

Page 25: ...t switch cable to this connector The Reset switch restarts the system Setting Description Short Reset Open Not Reset Table 13 3 5 7 JP1 EXTERNAL BATTERY The GMB 486UN mainboard has a battery on board...

Page 26: ...e chassis Connect a wide 34 wire ribbon cable to each disk drive which will attach to an adapter card Connect the 4 power supply cables to disk drives 3 Adapter Cards Insert each adapter card Disk Con...

Page 27: ...BIOS DEFAULTS AUTO CONFIGURATION WITH POWER ON DEFAULTS CHANGE PASSWORD HARD DISK UTILITY WRITE TO CMOS AND EXIT DO NOT WRITE TO CMOS AND EXIT 3 Choose an option and press Enter Modify the system para...

Page 28: ...MOS SETUP C 1990 American Megatrends Inc All Rights Reserved Date mn date year Thu Jan 31 1991 Base memory 640 KB Time hour min sec 15 23 15 Ext memory 3072 KB Daylight saving Disabled Hard disk C typ...

Page 29: ...6K Disabled Hit DEL Message Display Enabled Adaptor ROM Shadow D400 16K Disabled Hard Disk Type 47 RAM Area 0 300 Adaptor ROM Shadow D800 16K Disabled Wait For F1 If Any Error Enabled Adaptor ROM Shad...

Page 30: ...all options in the Advanced CMOS Setup Advanced Chipset Setup with the BIOS Setup default values F7 Load all options in the Advanced CMOS Setup Advanced Chipset Setup with the Power On default values...

Page 31: ...Video BIOS Cache Enabled DRAM Read Write 0 WS RAS Precharge 2Sclk SRAM Read 0 WS SRAM Burst Enabled SRAM Write 0 WS Master Cycle Swap Disabled IO Recovery Time 1ATCLK AT Wait State 0 WS AT BUS CLK SCL...

Page 32: ...AM Read 0 WS SRAM Burst Enabled SRAM Write 0 WS Master Cycle Swap Disabled IO Recovery Time 1ATCLK AT Wait State 0 WS AT BUS CLK SCLK 4 Non Cacheable Block 0 Size 0 KB Non Cacheable Block 0 Base 00000...

Page 33: ...c All Rights Reserved Tag RAM Include Dirty Enabled Cyrix Pin Enabled Barb Hidden Refresh Enabled Gate A20 Path Normal Cache Scheme W Back Video BIOS Cache Enabled DRAM Read Write 2 WS RAS Precharge 4...

Page 34: ...prompt to Y and press Enter The following message appears Default values loaded Press any key to continue 4 5 AUTO CONFIGURATION WITH POWER ON DEFAULTS This Main Menu item uses the default Power On va...

Page 35: ...d check that the Password Checking Option in the Advanced CMOS Setup is configured for Always or Setup See the section above on Advanced CMOS Setup When the password prompt appears key in the new pass...

Page 36: ...alyzes each track of the hard drive Marks unusable tracks as bad to prevent future data storage on those tracks Error messages specific to the Hard Disk Utility options may appear during initializatio...

Page 37: ...17 31MB 8 733 5 65535 733 17 30MB 9 900 15 65535 901 17 112MB 10 820 3 65535 820 17 20MB 11 855 5 65535 855 17 35MB 12 855 7 65535 855 17 50MB 13 306 8 128 319 17 20MB 14 733 7 65535 733 17 43MB 15 0...

Page 38: ...8MB 33 1024 5 1024 1024 17 43MB 34 612 2 128 612 17 10MB 35 1024 9 65535 1024 17 77MB 36 1024 8 512 1024 17 68MB 37 615 8 128 615 17 41MB 38 987 3 987 987 17 25MB 39 987 7 987 987 17 57MB 40 820 6 820...

Page 39: ...nue and error messages appear on the screen 6 1 BEEP ERROR CODES These codes are emitted as a series of audible beeps All Beep Error Codes except for number 8 are fatal errors If the system does not b...

Page 40: ...rd to monochrome or color Keyboard Is Locked Unlock It Unlock the keyboard lock to continue boot up Keyboard Error Make sure to have the AMI keyboard BIOS installed or set the Standard CMOS Setup s Ke...

Page 41: ...error messages may appear during the Hard Disk Utility routines of the BIOS Setup program The first four messages may appear during initialization the rest may appear during operations Message Action...

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