Gemalto Cinterion PLS62T-W USB, Hardware Interface Description

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Cinterion
®
Java Terminal Hardware Interface Description
Figures
7

PLS62T-W_HID_v01 2018-06-20
Confidential / Prelimenary
Page 7 of 91
Figures
Figure 1: Sample Java Terminal label PLS62T-W USB................................................. 17
Figure 2: Java Terminal 3D view.................................................................................... 22
Figure 3: Block diagram ................................................................................................. 23
Figure 4: Java Terminal circuit block diagram................................................................ 24
Figure 5: Pin assignment RS-232 (D-sub 9-pole female)............................................... 26
Figure 6: 8-pole RJ-45 Ethernet connector (female) ...................................................... 28
Figure 7: PLS62T-W USB: GPIO connectors (8-pin and 12-pin) ................................... 29
Figure 8: Characteristics of SPI modes.......................................................................... 32
Figure 9: 6-pole Western jack for power supply, ignition, reset, typical connection ....... 34
Figure 10: SIM interface ................................................................................................... 38
Figure 11: Status LED ...................................................................................................... 39
Figure 12: Antenna connectors ........................................................................................ 40
Figure 13: Java Terminal 3D overview............................................................................. 53
Figure 14: Java Terminal mechanical dimensions ........................................................... 54
Figure 15: Java Terminal exploded view.......................................................................... 55
Figure 16: Mounting the Java Terminal............................................................................ 56
Figure 17: Reference equipment for approval.................................................................. 58
Figure 18: Hardware watchdog configuration................................................................... 63
Figure 19: Write data to address register ......................................................................... 79
Figure 20: Read data from address register..................................................................... 80
Figure 21: Setting GPIO direction to OUTPUT via I
2
C interface ...................................... 82
Figure 22: Setting GPIO direction to INPUT via I
2
C interface .......................................... 82
Figure 23: Setting GPIO direction to OUTPUT via TXD0 line (at 1200bps) ..................... 83
Figure 24: Setting GPIO direction to INPUT via TXD0 line (at 1200bps) ......................... 83