Getting Started with Cinterion
®
PLS62-W
4 Appendix: Circuit Diagrams for Evaluation Module Board
16
PLS62-W_startup_guide_v01
2018-05-17
Confidential / Released
Page 16 of 17
Figure 9:
Schematic sheet 2
1 0 0 k
R203
BATT+_DSB
2 2 p
C200
V180
RING0/GPIO24
GND
GND
T S 5 A 2 3 1 6 6
D200
A1
NO1
B1
COM1
C1
I N 2
D1
GND
D2
NO2
C2
COM2
B2
I N 1
A2
VCC
V180
V180
PWM1/SDIO2/GPIO7
ADC1
AD2
E S D A 6 V 1 - 5 P 6
V200
2
1
3
4
5
6
220n
C201
VSIM
GND
CCIN
CCCLK
CCIO
GND
1 0 0 k
R209
GND
GND
X202
10
1
9
8
7
6
5
4
3
2
11
20
19
18
17
16
15
14
13
12
100k
R223
GND
10k
R221
TFSDAI/GPIO22
RXD0
RXDDAI/GPIO21
RTS1/GPIO18
RTS0
DSR0/SPI_CLK/GPIO3
CCRST
TXD0
VRTC
GND
RXD1/SPI_MOSI/GPIO16
10k
R220
CTS1/SPI_CS/GPIO19
EMERG_RST
AGND
DTR0/SDIO_CD/GPIO1
TXD1/SPI_MISO/GPIO17
DCD0/SDIO0/GPIO2
MICP1
MICN1
SCLK/GPIO23
STATUS/SDIO_CLK/GPIO5
CTS0
IGT
TXDDAI/GPIO20
100k
R226
GND
0 R
R227
5 1 R
R234
5 1 R
R235
5 1 R
R236
5 1 R
R238
5 1 R
R239
5 1 R
R240
5 1 R
R241
5 1 R
R246
5 1 R
R247
5 1 R
R248
22p
C214
5 1 R
R249
5 1 R
R250
22p
C217
22p
C218
22p
C220
22p
C221
22p
C222
22p
C223
5 1 R
R252
5 1 R
R253
5 1 R
R254
5 1 R
R255
1 2 0 R
L 2 0 2
5 1 R
R259
22p
C229
GND
0 R
R268
0 R
R224
4 7 0 R
R237
10k
R218
10k
R219
1 0 0 n
C312
1 0 0 n
C313
0 R
R213
22p
C230
22p
C215
5 1 R
R243
GPIO4/FAST_SHDN
GND
GND
CCRST
AD2
5 1 R
R242
-1 - 1 %
220k
R228
V180
GND
GND
GND
GPIO6/PWM2
GND
2 k 2
R225
GND
22p
C231
GND
TMS
EPP1
CCCLK
CCIO
GND
GND
5 1 R
R257
5 1 R
R244
22p
C232
GND
SIM_SW/GPIO26
22p
C202
5 1 R
R258
VSIM
1k
R201
22p
C224
GND
PWR_IND
22p
C203
22p
C206
22p
C228
GND
GND
GND
22p
C205
2 k 2
R211
-1 - 1 %
220k
R229
GND
PWM1/SDIO2/GPIO7
GND
22p
C204
GND
22p
C212
EPN1
GND
V180
EMERG_RST
GND
22p
C225
TDO
SIMSEL
CC2CLK
1 2 0 R
L 2 0 3
GPIO15
I2CDAT
CC2IO
COUNTER/SDIO3/GPIO8
GPIO14
22p
C227
E S D A 6 V 1 - 5 P 6
V201
2
1
3
4
5
6
VMIC
CC2RST
GND
V180
GND
GND
22p
C211
TRST
10k
R204
GPIO13
CCIN
2 2 k
R283
22p
C207
GND
GND
GND
GND
22p
C216
GND
USB_DN
GND
GND
CC2IN
GND
SIM_SW/GPIO26
GND
GND
BATT_PWR
22p
C226
AD1
I2CCLK
22p
C251
KINGSTON
T D I
AD1
RTCK
VUSB
5 1 R
R279
5 1 R
R256
TCK
GND
5 1 R
R284
GND
5 1 R
R245
GND
1 2 0 R
L 2 0 1
USB_DP
22p
C210
100k
R200
B C 8 4 7
V202
2
B1
B2
5
C1
6
3
C2
E1
1
E2
4
GND
22p
C233
GND
X201
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
2 8
2 9
3
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
4 9
5
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6
6 0
6 1
6 2
6 3
6 4
6 5
6 6
6 7
6 8
6 9
7
7 0
7 1
7 2
7 3
7 4
7 5
7 6
77
7 8
7 9
8
8 0
9
EMERG_OFF
0R
R280
0R
R281
GPIO12
VSIM2
5 1 R
R282
22p
C234
GND
FAB_TP1
1u
C281
100n
C282
VGPS
GND
GND
S i 1 0 2 3 X
V280
1
2
6
0R
R287
S i 1 0 2 3 X
V280
4
5
3
3k3
R291
GND
ANT_GPS_DC
GPIO25
0R
R292
GND
GND
10k
R290
1R
R288
GND
10k
R289
Load
GND
NC
I o u t
NC
V i n
FAN4010
N280
6
5
4
3
2
1
GND
220n
C208
GPIO25
GPIO11
TX_Act
0R
R286
22p
C252
51R
R285
GND
L P 3 9 8 5 I M 5 X - 2 . 9
U280
4
BYPASS
2
GND
3
VEN
VIN
1
5
VOUT
GND
GND
GND
10n
C283
1u
C284
0R
R293
VMMC
BATT_PWR
Note:
Circuit elements
marked
blue
are not (yet)
populated on the PLS62
evaluation module
boards, and thus re-
served for future use.
