Gemalto Cinterion ELS31-VA, Description

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Cinterion
®
ELS31-VA/ELS51-VA Hardware Interface Description
Figures
106

ELS31-VA_ELS51-VA_HID_v01.000 2017-01-04
Confidential / Preliminary
Page 7 of 106
Figures
Figure 1: ELS31-VA/ELS51-VA system overview ......................................................... 12
Figure 2: ELS31-VA/ELS51-VA baseband block diagram ............................................ 13
Figure 3: Numbering plan for connecting pads (bottom view)....................................... 14
Figure 4: USB circuit ..................................................................................................... 22
Figure 5: USB Additional ESD Protection Implementation............................................ 23
Figure 6: Serial interface ASC0..................................................................................... 25
Figure 7: ASC0 startup behavior ................................................................................... 26
Figure 8: Serial interface ASC1..................................................................................... 27
Figure 9: ASC1 startup behavior ................................................................................... 28
Figure 10: External UICC/SIM/USIM card holder circuit ................................................. 30
Figure 11: PCM timing short frame (4096KHz, 16kHz sample rate) ............................... 32
Figure 12: I
2
S timing (slave mode) .................................................................................. 33
Figure 13: GPIO startup behavior ................................................................................... 35
Figure 14: I
2
C interface connected to V180 .................................................................... 36
Figure 15: I
2
C startup behavior ....................................................................................... 37
Figure 16: Characteristics of SPI modes......................................................................... 38
Figure 17: SDIO interface timing diagrams (Input/Output) .............................................. 40
Figure 18: Status signaling with LED driver .................................................................... 42
Figure 19: Power indication circuit .................................................................................. 43
Figure 20: Wake-up via RING0 ....................................................................................... 44
Figure 21: Fast shutdown timing ..................................................................................... 45
Figure 22: Antenna pads (bottom view) .......................................................................... 47
Figure 23: RF interface signals example......................................................................... 48
Figure 24: Embedded Stripline with 65µm prepreg (1080) and 710µm core .................. 49
Figure 25: Micro-Stripline on 1.0mm standard FR4 2-layer PCB - example 1 ................ 50
Figure 26: Micro-Stripline on 1.0mm Standard FR4 PCB - example 2............................ 51
Figure 27: Micro-Stripline on 1.5mm Standard FR4 PCB - example 1............................ 52
Figure 28: Micro-Stripline on 1.5mm Standard FR4 PCB - example 2............................ 53
Figure 29: Schematic diagram of ELS31-VA/ELS51-VA sample application .................. 55
Figure 30: Sample level conversion circuit...................................................................... 56
Figure 31: Sample circuit for applying power using an external µC ................................ 58
Figure 32: ON timing ....................................................................................................... 59
Figure 33: Emergency restart timing ............................................................................... 60
Figure 34: Switch off behavior......................................................................................... 63
Figure 35: Power saving and paging in LTE networks .................................................... 66
Figure 36: Wake-up via RTS0/RTS1............................................................................... 67
Figure 37: Position of reference points BATT_BB/BATT_RF and GND.......................... 70
Figure 38: ESD protection for RF antenna interface ....................................................... 72
Figure 39: EMI circuits..................................................................................................... 73
Figure 40: ELS31-VA/ELS51-VA– top and bottom view ................................................. 77
Figure 41: Dimensions of ELS31-VA/ELS51-VA (all dimensions in mm)........................ 78
Figure 42: Dimensions of ELS31-VA/ELS51-VA (all dimensions in mm) - bottom view . 78
Figure 43: Land pattern (top view) .................................................................................. 79
Figure 44: Recommended design for 120 micron thick stencil (top view, dual design)... 80
Figure 45: Reflow Profile ................................................................................................. 82
Figure 46: Carrier tape .................................................................................................... 86
Figure 47: Reel direction ................................................................................................. 86
Figure 48: Barcode label on tape reel ............................................................................. 87
Figure 49: Moisture barrier bag (MBB) with imprint......................................................... 88