gefran RK-5 C, User Manual, Page: 7 / 35

7 85201A_RK5C_User Manual_02-2017_ENG
LSS configure bit timing parameters
By means of this service, the LSS master device configures the pending bit rate of the LSS slave device. The LSS slave
device confirms the success or the failure of the service execution.
The allowed bit rate values with the associated table index, are specified in the following table.
Table index Bit rate (kbit/s)
0 1000
1 800
2 500
3 250
4 125
5 Reserved
6 50
7 20
8 10
Table 2 - Table index for bit timing table
The LSS master sends this message to configure the bit rate (the slave sends the response message):
COB-ID Rx/Tx DLC
Data
D0 D1 D2 D3 D4 D5 D6 D7
7E5h Rx 8 13h 00h
Table
index
00h 00h 00h 00h 00h
7E4h Tx 8 13h
Error
code
00h 00h 00h 00h 00h 00h
Figure 14 - LSS configure bit timing message
where Error code: 00h (Protocol successfully completed) or 01h (Bit timing not supported).
The pending bit rate becomes active only after the master sends the LSS activate bit timing parameter service, or with
the next power-on after the execution of the LSS store configuration service.
The bit rate is not automatically saved to the non-volatile memory of the slave device. In order to save the persistent
bit rate, refer to the LSS store configuration service.
At the power on, the active bit rate equals the persistent bit rate.
LSS activate bit timing parameters
By means of this service, the LSS master activates simultaneously the bit rate at the LSS communication interface of
all CANopen devices in the network.
Therefore the reception of this command triggers at the LSS slave the copying process of the currently pending bit rate
to the active bit rate.
The LSS master sends this message to activate the bit timing parameters:
COB-ID Rx/Tx DLC
Data
D0 D1 D2 D3 D4 D5 D6 D7
7E5h Rx 8 15h Switch delay 00h 00h 00h 00h 00h
Figure 15 - LSS activate bit timing parameters message
where Switch delay is the time, in ms, multiplied by 2 when the new bit timing settings becomes active (Intel format byte
ordering)