GE Mini COM Express 10, Hardware Reference Manual

Page: 62 / 82

6.7.8 Line Status
This register provides access to status indicators on the UART line interface.
UART Line Status Register (Offset 0x5)
Bit Name Access Default
Description
7
ERR_INF
R 0
Error in FIFO. Always cleared in register mode. In
FIFO mode, this bit indicates that at least one
parity error, framing error, or break indication has
been received and is inside the receive FIFO.
Cleared on read if no more errors reside in the
FIFO.
6 TEMPT R 1
Transmitter empty. Set to 1 when both the
transmit holding register and the transmit shift
register are empty. In FIFO mode, this bit
indicates that both the transmit FIFO and the
transmit shift register are empty.
5 THRE R 1
Transmit holding register empty. Set to 1 to
indicate that the transmit holding register is ready
to accept a new character. In FIFO mode, this bit
indicates that the entire transmit FIFO is empty.
4 BI R 0
Break indicator. Set to 1 when the receive data is
held at logic 0 for at least one full character (start
bit + data + stop bit) time. In FIFO mode,
this applies to the character at the top of the FIFO.
Generates a Receiver Line Status interrupt.
Cleared when read.
3 FE R 0
Framing error. Set to 1 when the received
character does not have a valid stop bit. In FIFO
mode, this applies to the character at the top of
the FIFO. Generates a Receiver Line Status
interrupt. Cleared when read.
2 PE R 0
Parity error. Set to 1 when the received character
has incorrect parity. In FIFO mode, this applies to
the character at the top of the FIFO. Generates a
Receiver Line Status interrupt. Cleared when
read.
1 OE R 0
Overrun error. Set to 1 when a new receive
character is transferred to the transmit holding
register before the prior character was read, or
that the FIFO is full and a complete new character
is received in the shift register. Generates a
Receiver Line Status interrupt. Cleared when
read.
0 DR R 0
Data ready. Set to 1 when a complete incoming
character has been received and transferred to
the receive data buffer or receive FIFO. Cleared
on a read from the receive buffer register, or when
the FIFO is empty.
62 GFK-2896 Mini COM Express Type 10 Module mCOM10-L1500
For public disclosure