6.6
Watchdog Timer Configuration Registers
Watchdog Timer Configuration Registers
Index
Name
Description
0x30
Control
Logical device activation control
0x60
Wdog Base (High)
Watchdog registers base I/O address (upper 8
bits)
0x61
Wdog Base (Low)
Watchdog registers base I/O address (lower 8
bits)
0x70
Wdog IRQ
Watchdog interrupt request assignment
0xF0
Wdog Options
Watchdog timer options settings
6.6.1
Watchdog Timer Control
The Watchdog Timer Control register allows the logical device to be activated or
deactivated.
Watchdog Timer Control Register (LDN 0x14, Index 0x30)
Bit
Name
Access
Default
Description
7:01
—
R
0b0000000
Reserved
0
ACTIVATE
R/W
0
Logical device activation
0: Disabled
1: Enabled
6.6.2
Watchdog Timer Base Address
The Watchdog Timer Base Address register sets the I/O base addresses for the FFC
watchdog timer run-time registers. The base address must be aligned on an 8-byte
boundary.
Watchdog Timer Base Address Register (LDN 0x14, Index 0x60-0x61)
Bit
Name
Access
Default
Description
15:03
ADDR[15:3]
R/W
0x000
Base address bits 15:03
2:0
—
R
0b000
Reserved
54
GFK-2896
Mini COM Express Type 10 Module mCOM10-L1500
For public disclosure
Summary of Contents for Mini COM Express 10
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