36 IMP2B 3U cPCI Single Board Computer
Publication No. IMP2B-0HH/5
3.16.5
GPIO Interrupt Active Register – Offset 0x00000408
The bits indicate whether there is an active interrupt on the corresponding GPIO
line, as follows:
0 = Interrupt inactive
1 = Interrupt active
If a line is set to ‘Edge Triggered’, writing a ‘1’ to the corresponding bit will clear the
appropriate interrupt.
3.16.6
GPIO Interrupt Enable Register – Offset 0x0000040A
The bits indicate whether interrupts are enabled or disabled on the corresponding
GPIO line, as follows:
0 = Interrupt disabled (default)
1 = Interrupt enabled
3.16.7
GPIO Masked Interrupt Status Register – Offset 0x0000040C
This read-only register is a logical AND of the GPIO Interrupt Active and GPIO
Interrupt Enable Registers. The bits indicate whether interrupts on the
corresponding GPIO line are active and enabled, as follows:
0 = Interrupt inactive or disabled
1 = Interrupt active and enabled
3.17 CompactPCI Arbiter
The EPLD contains an 8-slot PCI arbiter to control the CompactPCI bus when
configured as System Controller (Rack Host). The priority can be set as either fixed
(slot 1 highest, slot 8 lowest) or rotational in the EPLD
. The
default is ‘Round-Robin’.
The arbiter implements broken master detection (grant removed if bus is not used
within 16 cycles of grant asserted) and bus parking on the last master.