GS66504B-EVBDB 650V
GaN E-HEMT Evaluation Board
User’s Guide
_____________________________________________________________________________________________________________________
GS66504B-EVBDB UG rev. 161120
© 2016 GaN Systems Inc.
www.gansystems.com 11
Please refer to the Evaluation Board/Kit Important Notice on page 29
CON1
Q1
CON2
Q2
VDC-
CON4
CON3
L
OUT
400V DC
+
VDC+
CON7
CON6
VSW
CON5
+5V
0V
PWM
INPUT
(J7)
V
DS
I
L
I
SW
V
GL
+6V
0V
V
DS
V
GL
I
L
t0
t1 t2 t3
T
ON1
Figure 12 Double pulse test setup
Double pulse test allows easy evaluation of device switching performance at high voltage/current
without the need of actually running at high power. It can also be used for switching loss (Eon/Eoff)
measurement and other switching characterization parameter test.
The circuit configuration and operating principle can be found in Figure 12:
1.
The output inductor is connected to the VDC+.
2.
At t0 when Q2 is switched on, the inductor current starts to ramp up until t1. The period of first
pulse Ton1 defines the switching current I
SW
= (V
DS
*T
ON1
) / L.
3.
t1-t2 is the free wheeling period when the inductor current I
L
forces Q1 to conduct in reverse.
4.
t1 (turn-off) and t2 (turn-on) are of interest for this test as they are the hard switching trasients for
the half bridge circuit when Q2 is under high switching stress.
5.
The second pulse t2-t3 is kept short to limit the peak inductor current at t3.
The double pulse signal can be generated using programmable signal generaotor or microcontroller/DSP
board. As this test involves high switching stress and high current, it is recommended to set the double
pulse test gate signal as single trigger mode or use long repetition period (for example >50-100ms) to void
excess stress to the switches. Q1 can be kept off during the test or driven synchronously (J4 set to OFF or
INT_INV) and Q2 is set to INT (or EXT position if PWM signal is from J5).
WARNING!
Limit the maximum switching test current to 15A and ensure maximum drain
voltage including ringing is below 650V for pulse testing. Exceeding this limit
may cause damage to the devices.
Buck/Standard half bridge mode
