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SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

M.2

Cache Coherency Protocols

The CPU uses the UPA MOESI cache-coherence protocol; these letters are acronyms
for cache line states as follows:

A subset of the MOESI protocol is used in the on-chip caches as well as the D-Tags in
the system controller.

TABLE M-4

shows the relationships between the protocols.

TABLE M-5

shows the encoding of the MOESI states in the L2 Cache.

M.3

Cache Control/Status Instructions

Several ASI instructions are defined to manipulate the caches. The following
conventions are common to all of the load and store alternate instructions defined in
this section:

M

Exclusive modified

O

Shared modified (owned)

E

Exclusive clean

S

Shared clean

I

Invalid

TABLE M-4

Relationships Between Cache Coherency Protocols

L2-Cache

L1D-Cache

SAT (store ownership)

L1I-Cache

Invalid (I)

Invalid (I)

Invalid (I)

Invalid (I)

Shared Clean (S)

Invalid (I) or Clean (C)

Invalid (I)

Invalid (I) or
Valid (V)

Shared Modified (O)

Exclusive Clean (E)

Exclusive Modified (M)

Invalid (I)

Exclusive Modified (M)

Valid (V)

TABLE M-5

L2 Cache MOESI States

Bit 2 (Valid)

Bit 1 (Exclusive)

Bit 0 (Modified)

State

0

—

—

Invalid (I)

1

0

0

Shared clean (S)

1

1

0

Exclusive clean (E)

1

0

1

Shared modified (O)

1

1

1

Exclusive modified (M)

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Summary of Contents for SPARC JPS1

Page 1: ...Fujitsu Limited 4 1 1 Kamikodanaka Nahahara ku Kawasaki 211 8588 Japan SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Fujitsu Limited Release 1 0 1 July 2002 Part No 806 6755 1 0 ...

Page 2: ... et dans d autres pays et licenciée exclusivement par X Open Company Ltd La notice suivante est applicable à Netscape Communicator Copyright 1995 Netscape Communications Corporation Tous droits réservés Sun Sun Microsystems the Sun logo AnswerBook2 docs sun com et Solaris sont des marques de fabrique ou des marques déposées ou marques de service de Sun Microsystems Inc aux Etats Unis et dans d aut...

Page 3: ...3 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 4: ...6 Execution Unit EU 6 Storage Unit SU 7 Secondary Cache and External Access Unit SXU 8 2 Definitions 9 3 Architectural Overview 13 4 Data Formats 15 5 Registers 17 Nonprivileged Registers 17 Floating Point State Register FSR 18 Tick TICK Register 19 Privileged Registers 19 Trap State TSTATE Register 19 Version VER Register 20 Ancillary State Registers ASRs 20 Registers Referenced Through ASIs 22 ...

Page 5: ...p Instructions 30 Implementation Dependent Instructions 30 Processor Pipeline 31 Instruction Fetch Stages 31 Issue Stages 33 Execution Stages 33 Completion Stages 34 7 Traps 35 Processor States Normal and Special Traps 35 RED_state 36 error_state 36 Trap Categories 37 Deferred Traps 37 Reset Traps 37 Uses of the Trap Categories 37 Trap Control 38 PIL Control 38 Trap Table Entry Addresses 38 Trap T...

Page 6: ... 50 Jump and Link 53 Load Quadword Atomic Physical 54 Memory Barrier 55 Partial Store VIS I 57 Prefetch Data 57 Read State Register 58 SHUTDOWN VIS I 58 Write State Register 59 Deprecated Instructions 59 Store Barrier 59 B IEEE Std 754 1985 Requirements for SPARC V9 61 Traps Inhibiting Results 61 Floating Point Nonstandard Mode 61 fp_exception_other Exception ftt unfinished_FPop 62 Operation Under...

Page 7: ...Data In Data Access and Tag Read Registers 93 I D TSB Extension Registers 97 I D Synchronous Fault Status Registers I SFSR D SFSR 97 MMU Bypass 104 TLB Replacement Policy 105 G Assembly Language Syntax 107 H Software Considerations 109 I Extending the SPARC V9 Architecture 111 J Changes from SPARC V8 to SPARC V9 113 K Programming with the Memory Models 115 L Address Space Identifiers 117 SPARC64 V...

Page 8: ...nterrupt Global Registers 136 Interrupt Related ASR Registers 136 Interrupt Vector Dispatch Register 136 Interrupt Vector Dispatch Status Register 136 Interrupt Vector Receive Register 136 O Reset RED_state and error_state 137 Reset Types 137 Power on Reset POR 137 Watchdog Reset WDR 138 Externally Initiated Reset XIR 138 Software Initiated Reset SIR 138 RED_state and error_state 139 RED_state 140...

Page 9: ...nt Error 165 URGENT ERROR STATUS ASI_UGESR 165 Action of async_data_error ADE Trap 168 Instruction End Method at ADE Trap 170 Expected Software Handling of ADE Trap 171 Instruction Access Errors 173 Data Access Errors 173 Restrainable Errors 174 ASI_ASYNC_FAULT_STATUS ASI_AFSR 174 ASI_ASYNC_FAULT_ADDR_D1 177 ASI_ASYNC_FAULT_ADDR_U2 178 Expected Software Handling of Restrainable Errors 179 Handling...

Page 10: ...rumentation 201 Performance Monitor Overview 201 Sample Pseudocodes 201 Performance Monitor Description 203 Instruction Statistics 204 Trap Related Statistics 206 MMU Event Counters 207 Cache Event Counters 208 UPA Event Counters 210 Miscellaneous Counters 211 R UPA Programmer s Model 213 Mapping of the CPU s UPA Port Slave Area 213 UPA PortID Register 214 UPA Config Register 215 S Summary of Diff...

Page 11: ...viii SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 12: ...on page 2 Component Overview on page 4 Processor Pipeline on page 31 2 Study the terminology in Chapter 2 Definitions 3 For details of architectural changes see the remaining chapters in this Implementation Supplement as your interests direct For this revision we added new appendixes Appendix R UPA Programmer s Model and Appendix S Summary of Differences between SPARC64 V and UltraSPARC III 1 2 Fo...

Page 13: ...ble Out of order execution in SPARC64 V contributes to high performance SPARC64 V implements a large branch history buffer to predict its instruction path The history buffer is large enough to sustain a good prediction rate for large scale programs such as DBMS and to support the advanced instruction fetch mechanism of SPARC64 V This instruction fetch scheme predicts the execution path beyond the ...

Page 14: ...he special error marking The identification information enables the processor to avoid repetitive error logging for the same error cause 2 Advanced RAS features for the core Strong error protection Parity protection for all data paths Parity protection for most of software visible registers and internal temporary registers Parity prediction or residue checking for the accumulator output Hardware i...

Page 15: ...d depends on the executing instruction and the detected error Some ADE traps that are deferred but retryable Simultaneous reporting of all detected ADE errors at the error barrier for correct handling of retryability 1 3 1 Component Overview The SPARC64 V processor contains these components Instruction control Unit IU Execution Unit EU Storage Unit SU Secondary cache and eXternal access Unit SXU F...

Page 16: ...Us FLA EXA EXB FLB EAGA EAGB ALU Output Input Registers Registers SX order queue Store queue SX interface D TLB tag data 2048 32 entry Level 1 D cache 128 KB 2 way S Unit and Instruction Instruction Commit stack entry Reservation stations Branch history PC nPC CCR FSR I Unit GUB FUB GPR FPR E unit control logic pipeline fetch buffer E Unit I TLB tag data 2048 32 entry Level 1 I cache 128 KB 2 way ...

Page 17: ...associative Instruction buffer Six entries 32 bytes entry Reservation station Six reservation stations to hold instructions until they can execute RSBR for branch and the other control transfer instructions RSA for load store instructions RSEA and RSEB for integer arithmetic instructions RSFA and RSFB for floating point arithmetic and VIS instructions Commit stack entries Sixty four entries basica...

Page 18: ...uction source Data level 1 cache 128 Kbyte 2 way associative 64 byte line writeback provides the low latency data source for loads and stores Instruction Translation Buffer 1024 entries 2 way associative TLB for 8 Kbyte pages 1024 entries 2 way associative TLB for 4 Mbyte pages1 32 entries fully associative TLB for unlocked 64 Kbyte 512 Kbyte 4 Mbyte1 pages and locked pages in all sizes 1 Unloced ...

Page 19: ...l 2 cache 2 Mbyte 4 way associative 64 byte line writeback provides low latency data source for both instruction level 1 cache and data level 1 cache Movein buffer Sixteen entries 64 bytes entry catches returning data from memory system in response to the cache line read request A maximum of 16 outstanding cache read operations can be issued Moveout buffer Eight entries 64 bytes entry holds writeb...

Page 20: ...the state has not yet been permanently changed and the old state can be recovered until the instruction has been committed executed Term applied to an instruction that has been processed by an execution unit such as a load unit An instruction is in execution as long as it is still being processed by an execution unit fetched Term applied to an instruction that is obtained from the I2 instruction c...

Page 21: ... mTLB for the translation If the mTLB contains the translation it sends the translation to the respective uTLB If the mTLB does not contain the translation it generates a fast access exception to a software translation trap handler which will load the translation information TTE into the mTLB and retry the access See also TLB uDTLB Micro Data TLB A small fully associative buffer that contains addr...

Page 22: ...tion are scheduled for execution Reservation stations also contain special tag matching logic that captures the appropriate operand data Reservation stations are sometimes referred to as queues for example the integer queue speculative A distribution system whereby a result is not guaranteed as known to be correct or an operand state is not known to be valid SPARC64 V employs speculative distribut...

Page 23: ...12 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 24: ...13 F CHAPTER 3 Architectural Overview Please refer to Chapter 3 in the Commonality section of SPARC Joint Programming Specification ...

Page 25: ...14 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 26: ...15 F CHAPTER 4 Data Formats Please refer to Chapter 4 Data Formats in Commonality ...

Page 27: ...16 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 28: ...ronous events such as interrupts asynchronous error conditions and RED_state entry traps For general information please see parallel subsections of Chapter 5 in Commonality For easier referencing this chapter follows the organization of Chapter 5 in Commonality For information on MMU registers please refer to Section F 10 Internal Registers and ASI operations on page 92 The chapter contains these ...

Page 29: ...RC V9 IU implementation as identified by its VER impl field there may be one or more FPU implementations or none This field identifies the particular FPU implementation present For the first SPARC64 V FSR ver 0 impl dep 19 however future versions of the architecture may set FSR ver to other values Consult the SPARC64 V Data Sheet for the setting of FSR ver for your chipset FSR_floating point_trap_...

Page 30: ...mplements TICK counter register as a 63 bit register impl dep 105 Implementation Note On SPARC64 V the counter part of the value returned when the TICK register is read is the value of TICK counter when the RDTICK instruction is executed The difference between the counter values read from the TICK register on two reads reflects the number of processor cycles executed between the executions of the ...

Page 31: ... Please refer to Section 5 2 11 of Commonality for details of the ASRs Performance Control Register PCR ASR 16 SPARC64 V implements the PCR register as described in SPARC JPS1 Commonality with additional features as described in this section In SPARC64 V the accessibility of PCR when PSTATE PRIV 0 is determined by PCR PRIV If PSTATE PRIV 0 and PCR PRIV 1 an attempt to execute either RDPCR or WRPCR...

Page 32: ...ounter pairs encoded as 0 7 for 1 8 counter pairs impl dep 207 For SPARC64 V the hardcoded value of NC is 3 indicating presence of 4 counter pairs 20 18 SC Select PIC In SPARC64 V three bit field specifying which counter pair is currently selected as PIC ASR 17 and which SU SL values are visible to software On write PCR SC selects which counter pair is updated unless PCR ULRO is set see below On r...

Page 33: ...rflow Overflow status bits are cleared by software writing 0 to the appropriate bit of PCR OVF and may be set by writing 1 to the appropriate bit Setting these bits by software does not generate a level 15 interrupt Dispatch Control Register DCR ASR 18 The DCR is not implemented in SPARC64 V Zero is returned on read and writes to the register are ignored The DCR is a privileged register attempted ...

Page 34: ...re instructions are considered presync instructions that are executed when all previous instructions are committed Because all CTI are considered as not taken instructions residing beyond 1 Kbyte of a CTI may be fetched and executed On entering aggressive instruction Prefetch disable mode supervisor software should issue membar Sync to make sure all in flight instructions in the pipeline are disca...

Page 35: ...h BPcc FBPfcc Bicc BPr instruction in an instruction cache are identical to their architectural encoding as it appears in main memory impl dep 245 5 2 13 Floating Point Deferred Trap Queue FQ SPARC64 V does not contain a Floating Point Deferred trap Queue impl dep 24 An attempt to read FQ with an RDPR instruction generates an illegal_instruction exception impl dep 25 5 2 14 IU Deferred Trap Queue ...

Page 36: ...V9 Several instructions may be issued and executed in parallel Although SPARC64 V provides serial program execution semantics some of the implementation characteristics described below are part of the architecture visible to software for correctness and efficiency The affected software includes optimizing compilers and supervisor code 6 1 1 Data Prefetch SPARC64 V employs speculative out of progra...

Page 37: ...allowing speculative accesses to certain memory pages or I O spaces This can be done by setting the E side effect bit in the PTE for all memory pages that should not allow speculation All accesses made to memory pages that have the E bit set in their PTE will be delayed until they are no longer speculative or until they are cancelled See Appendix F Memory Management Unit for details 2 Alternate sp...

Page 38: ... all instructions commit in order but store instruction commit before becoming globally visible A few syncing instructions cause the processor to discard prefetched instructions and to refetch the successive instructions TABLE 6 1 lists all pre postsync instructions and the effects of instruction execution TABLE 6 1 SPARC64 V Syncing Instructions Opcode Presyncing Postsyncing Sync Wait for store g...

Page 39: ...nly TABLE 6 2 Instruction Fields Specific to SPARC64 V Bits Field Description 13 9 rs3 This 5 bit field is the address of the third f register source operand for the floating point multiply add and multiply subtract instruction 8 7 var This 2 bit field specifies which specific operation variation to perform for the floating point multiply add and multiply subtract instructions 6 5 size This 2 bit ...

Page 40: ...al moves Register window management State register access Privileged register access Floating point operate FPop Implementation dependent 6 3 3 Control Transfer Instructions CTIs These are the basic control transfer instruction types Conditional branch Bicc BPcc BPr FBfcc FBPfcc Unconditional branch Call and link CALL Jump and link JMPL RETURN Return from trap DONE RETRY Trap Tcc Instructions othe...

Page 41: ...e complete conditions of generating an fp_exception_other exception with FSR ftt unfinished_FPop are described in Section B 6 Floating Point Nonstandard Mode on page 61 The SPARC64 V specific FMADD and FMSUB instructions described below are also floating point operations They require the floating point unit to be enabled otherwise an fp_disabled trap is generated They also affect the FSR like FPop...

Page 42: ...uffer IA through IR stages are dedicated to instruction fetch These stages work in concert with the cache access unit to supply instructions to subsequent stages The instructions fetched from memory or cache are stored in the Instruction Buffer I buffer The I buffer has six entries each of which can hold 32 byte aligned 32 byte data eight instructions SPARC64 V has a branch prediction mechanism an...

Page 43: ...Release 1 0 1 July 2002 FIGURE 6 2 SPARC64 V Pipeline IA IT IM IB IR D P B X Ts Ms Bs Rs U W E Ps BRHIS iTLB Instruction Buffer RSFA RSFB RSEB RSEA RSA RSBR L1I dTLB L1D FXB EXB FXA EXA EAGA EAGB IWR GUB GPR FUB FPR PC nPC ccr fsr IF EAG LB LR RR RR RR RR CSE ...

Page 44: ...he instruction but all resources must be assigned at these stages In normal execution assigned resources are released at the very last stage of the pipeline W stage 1 Instructions between the E stage and W stage are considered to be in flight When an exception is signalled all in flight instructions and the resources used by them are released immediately This behavior enables the decoder to restar...

Page 45: ...d by memory access instructions are released The cache access pipeline itself remains working in order to complete outgoing memory accesses When data is returned it is then stored to the cache 6 4 4 Completion Stages U Update Update of physical renamed register W Write Update of architectural registers and retire exception handling After an out of order execution execution reverts to program order...

Page 46: ...aps on page 35 RED_state on page 36 error_state on page 36 Trap Categories on page 37 Deferred Traps on page 37 Reset Traps on page 37 Uses of the Trap Categories on page 37 Trap Control on page 38 PIL Control on page 38 Trap Table Entry Addresses on page 38 Trap Type TT on page 38 Details of Supported Traps on page 39 Exception and Interrupt Descriptions on page 39 7 1 Processor States Normal and...

Page 47: ...dent behavior in RED_state impl dep 115 While in RED_state all internal ITLB based translation functions are disabled DTLB based translations are disabled upon entry but may be reenabled by software while in RED_state However ASI based access functions to the TLBs are still available While mTLBs and uTLBs are disabled all accesses are assumed to be noncacheable and strongly ordered for data access...

Page 48: ... certain error conditions impl dep 32 Please refer to the description of I_UGE error on Relation between tpc and the instruction that caused the error row in TABLE P 2 page 156 for details See also Instruction End Method at ADE Trap on page 170 7 2 4 Reset Traps Please refer to Section 7 2 4 of Commonality In SPARC64 V a watchdog reset WDR occurs when the processor has not committed an instruction...

Page 49: ...terrupt has sufficient priority SPARC64 V will stop issuing new instructions will flush all uncommitted instructions and then will vector to the trap handler The only exception to this process occurs when SPARC64 V is processing a higher priority trap SPARC64 V takes a normal disrupting trap upon receipt of an interrupt request 7 4 Trap Table Entry Addresses Please refer to Section 7 4 of Commonal...

Page 50: ... V9 Implementation Dependent Optional Traps That Are Mandatory in SPARC JPS1 Please refer to Section 7 6 4 of Commonality SPARC64 V implements all six traps that are implementation dependent in SPARC V9 but mandatory in JPSI impl dep 35 Se Section 7 6 4 of Commonality for details 7 6 5 SPARC JPS1 Implementation Dependent Traps Please refer to Section 7 6 5 of Commonality SPARC64 V implements the f...

Page 51: ... access error upon access by an ldxa or stxa instruction Multiple errors may be reported in a single generation of the async_data_error exception Depending on the situation the async_data_error trap becomes a precise trap a disrupting trap or a preemptive trap upon error detection The TPC and TNPC stacked by the exception may indicate the exact instruction the preceding instruction or the subseque...

Page 52: ...rder RMO All SPARC V9 processors must provide Total Store Order or a more strongly ordered model for example Sequential Consistency to ensure SPARC V8 compatibility Whether the PSO or RMO models are supported by SPARC V9 systems is implementation dependent SPARC64 V behaves in a manner that guarantees adherence to whichever memory model is currently in effect This chapter describes the following m...

Page 53: ...n this mode Since programs written for PSO or RMO will always work if run under Total Store Order this behavior is safe but does not take advantage of the reduced restrictions of PSO 8 4 SPARC V9 Memory Model Please refer to Section 8 4 of Commonality In addition this section describes SPARC64 V specific details about the processor memory interface model 8 4 5 Mode Control SPARC64 V implements Tot...

Page 54: ...dified data to be flushed and corresponding unmodified data to be invalidated from all data caches The flush operation is still operative in SPARC64 V however Since the FLUSH instruction synchronizes the processor the total latency varies depending on the situation in SPARC64 V Assuming all prior instructions are completed the latency of FLUSH is 18 CPU cycles ...

Page 55: ...44 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 56: ...s defined in the subsection with the values of the field s that uniquely identify the instruction s 2 An illustration of the applicable instruction format s In these illustrations a dash indicates that the field is reserved for future versions of the architecture and shall be 0 in any instance of the instruction If a conforming SPARC V9 implementation encounters nonzero values in these fields its ...

Page 57: ...ction that has been programmed into the processor s IIU_INST_TRAP ASI 6016 VA 0 These traps are also not listed under each instruction The following traps never occur in SPARC64 V instruction_access_MMU_miss data_access_MMU_miss data_access_protection unimplemented_LDD unimplemented_STD LDQF_mem_address_not_aligned STQF_mem_address_not_aligned internal_processor_error fp_exception_other ftt invali...

Page 58: ... an operand address conflict in SPARC64 V To maintain the memory ordering even for the memory address conflicts MEMBAR instructions shall be inserted into appropriate location in the program Although self consistency with respect to the block load store and the other memory reference instructions is not maintained in some cases register conflicts between the other instructions and block load store...

Page 59: ...is present in the operand cache and the status is clean exclusive the line in the operand cache is invalidated and the operand is stored in the L2 cache If the line is in the operand cache and the status is modified modified the operand is stored in the operand cache The following table summarizes each cache status before block store and the results of the block store Blank cells mean that no acti...

Page 60: ...d the value in the return address stack is used to predict the return address A 24 Implementation Dependent Instructions The IMPDEP1 and IMPDEP2 instructions are completely implementation dependent Implementation dependent aspects include their operation the interpretation of bits 29 25 and 18 0 in their encodings and which if any exceptions they may cause SPARC64 V uses IMPDEP1 to encode VIS inst...

Page 61: ...gative Multiply Add Double FNMSUBs 10 01 Negative Multiply Subtract Single FNMSUBd 10 10 Negative Multiply Subtract Double Operation Implementation Multiply Add rd rs1 rs2 rs3 Multiply Subtract rd rs1 rs2 rs3 Negative Multiply Subtract rd rs1 rs2 rs3 Negative Multiple Add rd rs1 rs2 rs3 Assembly Language Syntax fmadds fregrs1 fregrs2 fregrs3 fregrd fmaddd fregrs1 fregrs2 fregrs3 fregrd fmsubs freg...

Page 62: ...SPARC64 V That is a multiply operation is first performed with a complete rounding step as if it were a single multiply operation and then an add subtract operation is performed with a complete rounding step as if it were a single add subtract operation Consequently at most two rounding errors can be incurred 1 Special behaviors in handling traps are generated in a Floating point Multiply Add Subt...

Page 63: ...n unfinished_FPop trap by SPARC64 V In addition the conditions with do not exist TABLE A 2 Exceptions in Floating Point Multiply Add Subtract Instructions FMUL IEEE754 trap No trap No trap FADD SUB IEEE754 trap No trap cexc Exception condition of FMUL Exception condition of FADD Logical or of the nontrapping exception conditions of FMUL and FADD SUB aexc No change No change Logical OR of the cexc ...

Page 64: ...when PSTATE AM is set impl dep 125 The value written into r rd is visible to the instruction in the delay slot If either of the low order two bits of the jump address is nonzero a mem_address_not_aligned exception occurs However when the JMPL instruction causes a mem_address_not_aligned trap DSFSR and DSFAR are not updated If the JMPL instruction has r rd 15 SPARC64 V stores PC 8 in a hardware tab...

Page 65: ...I a data_access_exception exception occurs for a noncacheable access or for the use of the quadword load ASIs with any instruction other than LDDA A mem_address_not_aligned exception is generated if the access is not aligned on a 16 byte boundary ASIs 3416 and 3C16 are supported in SPARC64 V in addition to those for Load Quadword Atomic for virtually addressed data ASIs 2416 and 2C16 The memory ac...

Page 66: ...DD and ASI_PHYS_USE_EC With respect to little endian memory a Load Quadword Atomic instruction behaves as if it comprises two 64 bit loads each of which is byte swapped independently before being written into its respective destination register Exceptions privileged_action PA_watchpoint recognized on only the first 8 bytes of a transfer illegal_instruction misaligned rd mem_address_not_aligned dat...

Page 67: ...ecated STBAR instruction Has no effect on SPARC64 V since all stores are performed in program order mmask 2 LoadStore All loads appearing before the MEMBAR instruction must have been performed before the effects of any stores following the MEMBAR are visible to any other processor Has no effect on SPARC64 V since all stores are performed in program order and must occur after performance of any loa...

Page 68: ...disabled PA_watchpoint VA_watchpoint illegal_instruction misaligned rd mem_address_not_aligned see Partial Store ASIs on page 120 data_access_exception see Partial Store ASIs on page 120 LDDF_mem_address_not_aligned see Partial Store ASIs on page 120 data_access_error fast_data_access_MMU_miss fast_data_access_protection A 49 Prefetch Data Please refer to Section A 49 Prefetch Data of Commonality ...

Page 69: ... as a NOP in privileged mode impl dep 206 TABLE A 7 Prefetch Variants fcn Fetch to Status Description 0 L1D S 1 L2 S 2 L1D M 3 L2 M 4 NOP 5 15 reserved SPARC V9 illegal_instruction exception is signalled 16 19 implementation dependent NOP 20 L1D S If an access causes an mTLB miss fast_data_access_MMU_miss exception is signalled 21 L2 S If an access causes an mTLB miss fast_data_access_MMU_miss exc...

Page 70: ...privileged_action exception only when an attempt is made to change that is write 1 to PCR PRIV impl dep 250 A 71 Deprecated Instructions The deprecated instructions in A 71 of Commonality are provided only for compatibility with previous versions of the architecture They should not be used in new software A 71 10 Store Barrier In SPARC64 V STBAR behaves as NOP since the hardware memory models alwa...

Page 71: ...60 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 72: ...ion specific to the SPARC64 V implementation of SPARC V9 in these sections Traps Inhibiting Results on page 61 Floating Point Nonstandard Mode on page 61 B 1 Traps Inhibiting Results Please refer to Section B 1 of Commonality The SPARC64 V hardware in conjunction with kernel or emulation code produces the results described in this section B 6 Floating Point Nonstandard Mode In this section the har...

Page 73: ... d FSQRT s d floating point instructions In addition Floating point Multiply Add Subtract instructions generate the exception since the instruction is the combination of a multiply and an add subtract operation FMADD s d FMSUB s d FNMADD s d and FNMADD s d The following basic policies govern the detection of boundary conditions 1 When one of the operands is a denormalized number and the other oper...

Page 74: ... calculated eres is a biased result exponent after mantissa alignment and before rounding where the appropriate adjustment of the exponent is applied to the result mantissa left shifting or right shifting the mantissa to the implicit 1 at the left of the binary point subtracting or adding the shift amount to the exponent The result mantissa is assumed to be 1 xxxx in calculating eres If the result...

Page 75: ...for a NaN and an infinity 2 Both operands are denormalized numbers FDIVs FDIVd 1 The dividend operand1 rs1 is a normal nonzero floating point number except for a NaN and an infinity the divisor operand2 rs2 is a denormalized number and single precision Er 255 double precision Er 2047 2 The dividend operand1 rs1 is a denormalized number the divisor operand2 rs2 is a normal nonzero floating point nu...

Page 76: ...on condition is detected or if the operation is FSQRT s d and an invalid_operation condition is detected the inexact condition is not reported If the result before rounding is a denormalized number the result is flushed to a zero with a same sign and signals either an underflow exception or an inexact exception depending on FSR TEM As observed from the preceding when FSR NS 1 SPARC64 V generates n...

Page 77: ...ized number and the other operand is a normal or a denormalized number non zero non NaN and non infinity Result Denorm2 2 The result before rounding turns out to be a denormalized number Pessimistic Zero Pessimistic Overflow UFM OFM NXM Result 0 No Yes Yes 1 UF 0 1 NX 0 uf nx a signed zero or a signed Dmin3 3 Dmin denormalized minimum No 1 UF 0 unfinished_FPop4 4 If the FPop is either FADD s d or ...

Page 78: ...d zero FdTOs Yes 1 UF 0 1 NX 0 uf nx a signed zero FADDs FSUBs FADDd FSUBd Yes No 1 NX 0 nx op2 No Yes 1 NX 0 nx op1 Yes Yes 1 NX 0 nx a signed zero FMULs FMULd FsMULd Yes 1 NX 0 nx a signed zero Yes 1 NX 0 nx a signed zero FDIVs FDIVd Yes No 1 NX 0 nx a signed zero No Yes 1 DZ 0 dz a signed infinity Yes Yes 1 NV 0 nv dNaN1 1 A single precision dNaN is 7FFF FFFF16 and a double precision dNaN is 7F...

Page 79: ...68 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 80: ...dy of this document for SPARC64 V to make the document more readable TABLE C 1 has been modified to include descriptions of the manner in which SPARC64 V has resolved each implementation dependency Note SPARC International maintains a document Implementation Characteristics of Current SPARC V9 based Products Revision 9 x that describes the implementation dependent design features of all SPARC V9 c...

Page 81: ...gal_instruction or unimplemented_FPop exceptions 2 Number of IU registers SPARC64 V supports eight register windows NWINDOWS 8 SPARC64 V supports an additional two global register sets Interrupt globals and MMU globals for a total of 160 integer registers 3 Incorrect IEEE Std 754 1985 results See Section B 6 Floating Point Nonstandard Mode on page 61 for details 62 4 5 Reserved 6 I O registers pri...

Page 82: ...C64 V floating point traps are always precise no FQ is needed 24 24 FPU deferred trap queue FQ SPARC64 V neither has nor needs a floating point deferred trap queue 24 25 RDPR of FQ with nonexistent FQ Attempting to execute an RDPR of the FQ causes an illegal_instruction exception 24 26 28 Reserved 29 Address space identifier ASI definitions The ASIs that are supported by SPARC64 V are defined in A...

Page 83: ...06F16 async_data_error tt 04016 39 39 36 Trap priorities SPARC64 V s implementation dependent traps have the following priorities interrupt_vector_trap priority 16 PA_watchpoint priority 12 VA_watchpoint priority 1 ECC_error priority 33 fast_instruction_access_MMU_miss priority 2 fast_data_access_MMU_miss priority 12 fast_data_access_protection priority 12 async_data_error priority 2 38 37 Reset t...

Page 84: ...tation dependent characteristics The prefetches have observable effects in privileged code Prefetch variants 0 3 do not cause a fast_data_access_MMU_miss trap because the prefetch is dropped when a fast_data_access_MMU_miss condition happens On the other hand prefetch variants 20 23 cause data_access_MMU_miss traps on TLB misses All prefetches are for 64 byte cache lines which are aligned on a 64 ...

Page 85: ... the check for fp_disabled The trap handler software emulates the instruction 112 STQF_mem_address_not_aligned SPARC64 V generates an illegal_instruction exception for all STQFs The processor does not perform the check for fp_disabled The trap handler software emulates the instruction 113 Implemented memory models SPARC64 V implements Total Store Order TSO for all the memory models specified in PS...

Page 86: ... are completed the latency of FLUSH is 18 processor cycles 123 Input output I O semantics This dependency is beyond the scope of this publication It should be defined in a system that uses SPARC64 V 124 Implicit ASI when TL 0 See Section 5 1 7 of Commonality for details 125 Address masking When PSTATE AM 1 SPARC64 V does mask out the high order 32 bits of the PC when transmitting it to the destina...

Page 87: ...res software intervention is implementation dependent 210 ERROR output signal The causes and the semantics of ERROR output signal are implementation dependent 211 Error logging registers information The information that the error logging registers preserves beyond the reset induced by an ERROR signal is implementation dependent 212 Trap with fatal error Generation of a trap along with ERROR signal...

Page 88: ...B multiple hit detection On SPARC64 V TLB multiple hit detection is supported However the multiple hit is not detected at every TLB reference When the micro TLB uTLB which is the cache of sTLB and fTLB matches the virtual address the multiple hit in sTLB and fTLB is not detected The multiple hit is detected only when the micro TLB mismatches and the main TLB is referenced 86 224 MMU physical addre...

Page 89: ...so impl dep 226 23 91 233 TSB_Hash field SPARC64 V does not implement TSB_Hash 92 234 TLB replacement algorithm For fTLB SPARC64 V implements a pseudo LRU For sTLB LRU is used 93 235 TLB data access address assignment The MMU TLB data access address assignment and the purpose of the address are implementation dependent 94 236 TSB_Size field width In SPARC64 V TSB_Size is 4 bits wide occupying bits...

Page 90: ...rupt Vector Dispatch Register is written 136 247 Interrupt Vector Receive Register SID fields SPARC64 V obtains the interrupt source identifier SID_L from the UPA packet 136 248 Conditions for fp_exception_other with unfinished_FPop SPARC64 V triggers fp_exception_other with trap type unfinished_FPop under the standard conditions described in Commonality Section 5 1 7 18 249 Data watchpoint for Pa...

Page 91: ...r LDDFA with ASI E016 or E11 and a memory address aligned on a 2n byte boundary a SPARC64 V processor behaves as follows n 3 8 byte alignment no exception related to memory address alignment is generated n 2 4 byte alignment LDDF_mem_address_not_aligned exception is generated n 1 2 byte alignment mem_address_not_aligned exception is generated 120 257 LDDFA with ASI C016 C516 or C816 CD16 and misal...

Page 92: ...F APPENDIX 81 D Formal Specification of the Memory Models Please refer to Appendix D of Commonality ...

Page 93: ...82 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 94: ...TABLE E 1 lists the opcode map for the SPARC64 V IMPDEP2 instruction TABLE E 1 IMPDEP2 op 2 op3 3716 var instruction 8 7 00 01 10 11 size instruction 6 5 00 not used reserved 01 FMADDs FMSUBs FNMADDs FNMADDs 10 FMADDd FMSUBd SNMSUBd FNMSUBd 11 reserved for quad operations ...

Page 95: ...84 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 96: ...plementation dependency as given in TABLE C 1 of Commonality then describe the SPARC64 V implementation F 1 Virtual Address Translation IMPL DEP 222 TLB organization is JPS1 implementation dependent SPARC64 V has the following TLB organization Level 1 micro ITLB uITLB 32 way fully associative Level 1 micro DTLB uDTLB 32 way fully associative Level 2 IMMU TLB consists of sITLB set associative Instr...

Page 97: ... TTE IMPL DEP in Commonality TABLE F 1 TTE_Data bits 46 43 are implementation dependent On SPARC64 V TTE_Data bits 46 43 are reserved IMPL DEP 224 Physical address width support by the MMU is implementation dependent in JPS1 minimum PA width is 43 bits The SPARC64 V MMU implements 43 bit physical addresses The PA field of the TTE holds a 43 bit physical address The MMU translates virtual addresses...

Page 98: ...ages respectively by a Data Access read are the data previously written to them IMPL DEP 225 The mechanism by which entries in TLB are locked is implementation dependent in JPS1 In SPARC64 V when a TTE with its lock bit set is written into TLB through the Data In register the TTE is automatically written into the corresponding fully associative TLB and locked in the TLB Otherwise the TTE is writte...

Page 99: ...ield is 4 bits IMPL DEP 229 Whether the implementation generates the TSB Base address by exclusive ORing the TSB Base Register and a TSB Extension Register or by taking the TSB_Base field directly from the TSB Extension Register is implementation dependent in JPS1 This implementation dependency is only to maintain compatibility with the TLB miss handling software of UltraSPARC I II On SPARC64 V wh...

Page 100: ...alid ASI See Section F 10 9 for details IMPL DEP 237 Whether the fault status and or address DSFSR DSFAR are captured when mem_address_not_aligned is generated during a JMPL or RETURN instruction is implementation dependent On SPARC64 V the fault status and address DSFSR DSFAR are not captured when a mem_address_not_aligned exception is generated during a JMPL or RETURN instruction Additional info...

Page 101: ...cted in an fTLB lookup for an instruction reference Ref 10 data_access_error Signalled upon the detection of at least one of the following errors An uncorrectable error is detected upon an instruction operand access A bus error response from the UPA bus is detected upon an operand access mDTLB sDTLB and fDTLB multiple hits are detected in an mDTLB lookup for an operand access 2 instruction_access_...

Page 102: ...wer on reset sequencer is set to UPA_configuraion_regiser AM by the JTAG command during the power on reset sequence So the initial value of the UPA physical address width is system dependent IMPL DEP 232 Whether CP and CV bits exist in the DCU Control Register is implementation dependent in JPS1 On SPARC64 V CP and CV bits do not exist in the DCU Control Register When DMMU is disabled the processo...

Page 103: ...16 are implementation dependent See impl dep 235 in I D TLB Data In Data Access and Tag Read Registers on page 93 Additional information The ASI_DCUCR register also affects the MMUs ASI_DCUCR is described in Section 5 2 12 of Commonality The SPARC64 V implementation dependency in ASI_DCUCR is described in Data Cache Unit Control Register DCUCR on page 22 SPARC64 V also has an additional MMU intern...

Page 104: ...TLB through ITLB Data In Register is directed to fITLB fw_fITLB is provided for use by OBP to register the TTEs that map the address translations themselves into fDTLB Data 13 12 RMD R TLB RAM MODE Handling of 4 Mbyte page entry is indicated on this fileld 00 4 Mbyte page entry is stored in fully associative TLB 01 reserved 10 4 Mbyte page entry is stored in 1024 entry 2 way set associative TLB 11...

Page 105: ...ement Fujitsu SPARC64 V Release 1 0 1 July 2002 For fTLB SPARC64 V implements a pseudo LRU For sTLB LRU is used IMPL DEP 235 The MMU TLB data access address assignment and the purpose of the address are implementation dependent in JPS1 ...

Page 106: ...e page sTLB Index 512 1023 addresses way1 of 8K byte page sTLB MCNTL RMD 01 Reserved On all index 0 is returned on read and writes data is ignored MCNTL RMD 10 Index 0 511 addresses way0 of 8K byte page sTLB Index 512 1023 addresses way1 of 8K byte page sTLB Index 1024 1535 addresses way0 of 4M byte page sTLB Index 1536 2047 addresses way1 of 4M byte page sTLB MCNTL RMD 11 Index 0 511 addresses wa...

Page 107: ...is feature to validate faulty TLB entries On verifing the consistency the bits position and length that is interpreted as index against the data in Tag Access Register varies on the page size and MCNTL RMD In 8 Kbyte page bits 21 13 is conscidered as index and compared with the index field of TLB Data Access or Data In Register In 4 Mbyte page bits 30 22 when MCNTL RMD 10 or bits 29 22 when MCNTL ...

Page 108: ...SB F 10 7 I D TSB Extension Registers IMPL DEP in Commonality FIGURE F 13 Bits 11 3 in I D TSB Extension Register are an implementation dependent field On SPARC64 V bits 11 0 in I D TSB Extension Registers are assigned as follows Bits 11 4 Reserved Always read as 0 and writes to it are ignored Bits 3 0 TSB_Size field is expanded to be a 4 bit field in SPARC64 V F 10 9 I D Synchronous Fault Status ...

Page 109: ...rror Marking for Cacheable Data Error on page 157 for details Data 45 32 EID R W Error mark ID Valid for a marked UE See Section P 2 4 Error Marking for Cacheable Data Error on page 157 for ERROR_MARK_ID Data 31 UE R W Instruction error status uncorrectable error When UE 1 an uncorrectable error in a fetched instruction word has been detected Valid only for an instruction_access_error exception Da...

Page 110: ...d 1002 Nucleus 1102 Reserved Data 3 PR R W Privileged Indicates the CPU privilege status during the instruction reference that generates the exception This field is valid when ISFSR FV 1 Data 1 OW R W Overwritten Set when ISFSR FV 1 upon the detection of a exception This means that the fault valid bit is not yet cleared when another fault is detected Data 0 FV R W Fault valid Set when the IMMU det...

Page 111: ...0 V V 0 V Error Access error V4 4 Updated when mITLB is signified 1 0 V 0 V V Overwrite policy5 5 Types 0 logical 0 1 logical 1 K keep U Update as per fault miss Error on exception U4 1 1 U K K U U Exception on error K 1 1 U U K U K Error on miss U 1 K U K 1 U U Exception on miss K 1 K U U 1 U K Miss on exception error K 1 K K K 1 K K Miss on miss K K K U K 1 K K TABLE F 8 D SFSR Bit Description 1...

Page 112: ...n data_access_error exception caused by DSFSR UE or DSFSR UPA For other causes of the trap the value is unknown Data 24 NF R W Nonfaulting load The instruction which generated the exception was a nonfaulting load instruction Data 23 16 ASI 7 0 R W ASI The 8 bit address space identifier applied to the reference that has invoked an exception This field is valid for the exception in which the DSFSR F...

Page 113: ... store instruction Data 1 OW R W Overwritten Set when DSFSR FV 1 upon detection of a exception This means that the fault valid bit is not yet cleared when another fault is detected Data 0 FV R W Fault valid Set when the DMMU detects an exception The bit is not set on an DMMU miss When the FV bit is not set the values of the remaining fields in the DSFSR and DSFAR are undefined except for a DMMU mi...

Page 114: ... generates a data_access_exception exception which otherwise has lower priority than fast_data_access_MMU_miss Note too that a reference to an internal ASI may generate a mem_address_not_aligned exception 1016 Access other than nonfaulting load was made to a page marked NFO This bit is zero for internal ASI accesses 2016 Reserved since there is no virtual hole 4016 Reserved since there is no virtu...

Page 115: ...for the data_access_error caused by DSFSR UE or DSFSR UPA 3 Types 0 logic 0 1 logic 1 V Valid field to be updated not a valid field 4 Memory reference instruction only 5 Updated when mDTLB is signified 6 Types 0 logic 0 1 logic 1 V Valid field to be updated not a valid field 7 Fault exception on miss means the miss happened first then a fault exception was encountered before soft ware had a chance...

Page 116: ... the fully associative TLB fTLB then the following alternatives are evaluated a The first invalid entry is replaced measuring from entry 0 If there is no invalid entry then b the first unused unlocked LRU but clear entry will be replaced measuring from entry 0 If there is no unused unlocked entry then c all used bits are reset and the process is repeated from Step 3b If fTLB is the target of the a...

Page 117: ...ntents The relation stxa_VA 11 3 ASI_TAG_ACCESS_REGISTER 21 13 and stxa_VA 13 0 should be satisfied Only if this condition is satisfied can the 8 Kbyte sTLB entry be replaced as designated The relation stxa_VA 11 3 ASI_TAG_ACCESS_REGISTER 30 22 and stxa_VA 13 1 should be satisfied Only if this condition is satisfied can the 4 Mbyte sTLB entry be replaced as designated Otherwise the stxa instructio...

Page 118: ...F APPENDIX 107 G Assembly Language Syntax Please refer to Appendix G of Commonality ...

Page 119: ...108 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 120: ...F APPENDIX 109 H Software Considerations Please refer to Appendix H of Commonality ...

Page 121: ...110 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 122: ...F APPENDIX 111 I Extending the SPARC V9 Architecture Please refer to Appendix I of Commonality ...

Page 123: ...112 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 124: ...F APPENDIX 113 J Changes from SPARC V8 to SPARC V9 Please refer to Appendix K of Commonality ...

Page 125: ...114 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 126: ...F APPENDIX 115 K Programming with the Memory Models Please refer to Appendix J of Commonality ...

Page 127: ...116 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 128: ...SIs are not only used to differentiate address spaces but are also used for other functions such as referencing registers in the MMU unit Please refer to Commonality for Sections L 1 and L 2 L 3 SPARC64 V ASI Assignments For SPARC64 V all accesses made with ASI values in the range 0016 7F16 when PSTATE PRIV 0 cause a privileged_action exception Warning The software should follow the ASI assignment...

Page 129: ...SCRATCH_REG0 RW 00 120 4F16 ASI_SCRATCH_REG1 RW 08 120 4F16 ASI_SCRATCH_REG2 RW 10 120 4F16 ASI_SCRATCH_REG3 RW 18 120 4F16 ASI_SCRATCH_REG4 RW 20 120 4F16 ASI_SCRATCH_REG5 RW 28 120 4F16 ASI_SCRATCH_REG6 RW 30 120 4F16 ASI_SCRATCH_REG7 RW 38 120 5016 6616 JPS1 6716 ASI_ALL_FLUSH_L1I W 129 6816 6916 JPS1 6A16 ASI_L2_CTRL RW 130 6B16 ASI_L2_DIAG_TAG_READ R 0016 7FFC016 130 6C16 ASI_L2_DIAG_TAG_READ...

Page 130: ...s ID is unique for each processor chip In conjunction with the Version Register please refer to Version VER Register on page 20 software can attain completely unique chip identification code This register is defined as read only write operation is ignored 6F16 ASI_C_BSTWBUSY RW C0 123 7016 EE16 JPS1 EF16 ASI_LBSYR0 RW 00 124 EF16 ASI_LBSYR1 RW 08 124 EF16 ASI_BSTW0 RW 80 124 EF16 ASI_BSTW1 RW 88 1...

Page 131: ...nment is generated but a data_access_exception is generated see case 3 below n 2 4 byte alignment LDDF_mem_address_not_aligned exception is generated n 1 2 byte alignment mem_address_not_aligned exception is generated 3 If the memory address is correctly aligned a data_access_exception with an AFSR FTYPE invalid ASI is generated Partial Store ASIs ASIs C016 C516 and C816 CD16 exist for use with th...

Page 132: ...em Barrier assist is highly dependent on the barrier mechanism in the memory system A description of the barrier mechanism is beyond the scope of this supplement see appropriate system documents for details L 4 1 Interface Definition FIGURE L 4 illustrates the interface between CPU and the memory system FIGURE L 4 CPU Interface of Barrier Assist High Speed LBSY Read Mechanism 1 The CPU has a copy ...

Page 133: ...on to the system controller 3 The system controller writes the BST A write to BST is faster than a noncacheable store L 4 2 ASI Registers LBSY Control Register ASI_C_LBSYR0 ASI_C_LBSYR1 The LBSY control register designates which bit in the copy of LBSY is read through ASI_LBSYRx 1 Register Name ASI_C_LBSYR0 ASI_C_LBSYR1 2 ASI 6F16 3 VA 0016 ASI_C_LBSYR0 0816 ASI_C_LBSYR1 4 RW Supervisor read write...

Page 134: ...s are ignored or a write to wrong BST is sent to the SB 1 Register Name ASI_C_BSTW0 ASI_C_BSTW1 2 ASI 6F16 3 VA 8016 ASI_C_BSTW0 8816 ASI_C_BSTW1 4 RW Supervisor read write Bit Name RW Description 63 V RW Valid When V 0 BL_num and SB_BPU_num are ignored and a write to ASI_BSTWx is discarded When V 1 data in the ASI_BSTWx is written to the selected bit in SB_BPU 6 SB_BPU_num RW SB BPU number on the...

Page 135: ...ASI_BSTWx is a write interface to LBSY on the SB On read 0 is returned 1 Register Name ASI_LBSYR0 ASI_LBSYR1 2 ASI EF16 3 VA 0016 ASI_LBSYR0 0816 ASI_LBSYR1 4 RW Read Write is ignored Bit Name RW Description 0 RV R Read value The bit designated by ASI_C_LBSYRx is shown 1 Register Name ASI_BSTW0 ASI_BSTW1 2 ASI EF16 3 VA 8016 ASI_BSTW0 8816 ASI_BSTW1 4 RW Write 0 is returned on read Bit Name RW Des...

Page 136: ...he is unified Level 1 caches are virtually indexed physically tagged VIPT and level 2 caches are physically indexed physically tagged PIPT All caches are 64 bytes in line size All lines in the level 1 caches are included in the level 2 cache Between level 1 caches or level 1 and level 2 caches coherency is maintained by hardware In other words eviction of a cache line from a level 2 cache causes f...

Page 137: ...ree conditions PSTATE RED 1 DCUCR IM 0 TLB CP 0 When MCNTL NC_CACHE 1 SPARC64 V treats all instructions as cacheable regardless of the conditions listed above See page 92 for details Programming Note This feature is intended to be used by the OBP to facilitate diagnostics procedures When the OBP uses this feature it must clear MCNTL NC_CACHE and invalidate all L1I data by ASI_FLUSH_L1I before it e...

Page 138: ...UCR DM 0 TLB CP 0 Unlike the L1I cache the L1D cache does not use MCNTL NC_CACHE M 1 3 Level 2 Unified Cache L2 Cache The level 2 unified cache is a writeback cache Its characteristics are shown in TABLE M 3 The L2 cache is bypassed when the access is noncacheable MCNTL NC_CACHE is not used on the L2 cache TABLE M 2 L1D Cache Characteristics Feature Value Size 128 Kbytes Associativity 2 way Line S...

Page 139: ...ed to manipulate the caches The following conventions are common to all of the load and store alternate instructions defined in this section M Exclusive modified O Shared modified owned E Exclusive clean S Shared clean I Invalid TABLE M 4 Relationships Between Cache Coherency Protocols L2 Cache L1D Cache SAT store ownership L1I Cache Invalid I Invalid I Invalid I Invalid I Shared Clean S Invalid I...

Page 140: ...mat in DATA are read as zero and ignored on write 6 The instruction operations are not affected by PSTATE CLE They are always treated as big endian 7 The instructions are all strongly ordered regardless of load or store and the memory model Therefore no speculative executions are performed Multiple Asynchronous Fault Address Registers are maintained in hardware one for each major source of asynchr...

Page 141: ..._ERROR_TRAP Reserved NUMINSWAY Reserved U2_FLUSH 63 25 24 23 19 18 16 15 1 0 TABLE M 6 ASI_L2_CTRL Register Bits Bit Field RW Description 24 URGENT_ERROR_TRAP RW1C This bit is set to 1 when one of the error exceptions instruction_access_error data_access_error or asynchronous_data_error exception is generated The bit remains set to 1 until supervisor software explicitly clears it by writing 1 to t...

Page 142: ..._READ_REG0 6 M 3 4 L2 Diagnostics Tag Read Registers ASI_L2_DIAG_TAG_READ_REG ASI_L2_DIAG_TAG_READ_REG0 6 holds the tag that is specified by the read of ASI_L2_DIAG_TAG_READ 1 Register Name ASI_L2_DIAG_TAG 2 ASI 6B16 3 VA VA 18 6 Index number of the tag 000016 7FFC016 4 RW Supervisor read 5 Data 0 is read 1 Register Name ASI_L2_DIAG_TAG_READ_REG 2 ASI 6C16 3 VA VA 6 3 internal register number 4 RW...

Page 143: ...132 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 144: ...the interrupt data registers ASI_INTR_W data 0 7 with the outgoing interrupt packet data by using ASI instructions It then performs an ASI_INTR_W interrupt dispatch write to trigger delivery of the interrupt The interrupt packet and the associated data are forwarded to the target UPA by the system controller The processor polls the BUSY bit in the INTR_DISPATCH_STATUS register to determine whether...

Page 145: ...INTR_DISPATCH_STATUS Error begin atomic sequence PSTATE IE 0 Write ASI_INTR_W data 0 Write ASI_INTR_W data 7 Write ASI_INTR_W interrupt MEMBAR Busy Y N dispatch read ASI_INTR_DISPATCH_STATUS Busy Y N end atomic sequence PSTATE IE 1 Nack Y N dispatch complete FIGURE N 1 Dispatching an Interrupt ...

Page 146: ...E 1 then the processor takes a trap and the interrupt data registers are read by the software to determine the appropriate trap handler The handler may reprioritize this interrupt packet to a lower priority FIGURE N 2 is an example of the interrupt receive flow read ASI_INTR_RECEIVE Error Read ASI_INTR_R data 0 Read ASI_INTR_R data 7 Determine Trap Handler Busy Y N clear ASI_INTR_RECEIVE interrupt...

Page 147: ...all 10 bits of VA 38 29 when the Interrupt Vector Dispatch Register is written impl dep 246 N 4 3 Interrupt Vector Dispatch Status Register In SPARC64 V 32 BUSY NACK pairs are implemented in the Interrupt Vector Dispatch Status Register impl dep 243 N 4 5 Interrupt Vector Receive Register SPARC64 V sets a 5 bit physical module ID MID value in the SID_L field of the Interrupt Vector Receive Registe...

Page 148: ...e the UPA_RESET_L pin is asserted low or the Power ready signal is deasserted the processor stops and executes only the specified JTAG command The processor does not change any software visible resources in the processor except the change by JTAG command execution and does not change any memory system state The sequence for the two types of power on reset in SPARC64 V hard power on reset and soft ...

Page 149: ...ved causing an entry into error_state O 1 3 Externally Initiated Reset XIR The CPU has an externally initiated reset XIR pin named UPA_XIR_L asserted low This pin must be asserted while the power supply is at full operational voltage and the UPA clock is running The assertion of XIR generates a trap of TT 3 and causes the processor to transfer execution to RSTVaddr 6016 and enter RED_state O 1 4 S...

Page 150: ...U Fatal Error Fatal Error Fatal Error WDT1 is the first watchdog timeout WDT2 is the second watchdog timeout WDT2 takes the CPU into error_state In a normal setting error_state immediately generates a watchdog reset trap and brings the CPU into RED_state Thus the state is transient When OPSR Operation Status Register specifies the stop on error_ state an entry into error_state does not cause a wat...

Page 151: ...y hardware to disable several hardware features Software must set these bits when required for example when the processor exits from RED_state When the processor enters RED_state not because of a trap or reset that is when the PSTATE RED bit has been set by WRPR these register bits are unchanged unlike the case above The only side effect is the disabling of the instruction MMU When the processor i...

Page 152: ... this table it is assumed that RED_state entry happens as a result of resets or traps If RED_state entry occurs because the WRPR instruction sets the PSTATE RED bit no processor state will be changed except the PSTATE RED bit itself the effects of this are described in RED_state on page 140 TABLE O 1 Nonprivileged and Privileged Register State after Reset and in RED_state Name POR1 WDR2 XIR SIR RE...

Page 153: ...RE Unknown Unchanged Unchanged OTHERWIN Unknown Unchanged Unchanged CLEARWIN Unknown Unchanged Unchanged WSTATE OTHER NORMAL Unknown Unchanged Unknown Unchanged Unchanged Unchanged VER MANUF IMPL MASK MAXTL MAXWIN 000416 516 Mask dependent 516 716 1 Hard POR occurs when power is cycled Values are unknown following hard POR Soft POR occurs when UPA_RESET_L is asserted Values are unchanged following...

Page 154: ...d 2 CCR Unknown Unchanged Unchanged 3 ASI Unknown Unchanged Unchanged 4 TICK NPT Counter 1 Restart at 0 Unchanged Unchanged Unchanged Restart at 0 Unchanged Unchanged 6 FSR 0 Unchanged 16 PCR UT ST Others 0 0 Unknown Unchanged Unchanged 17 PIC Unknown Unchanged Unchanged 18 DCR Always 0 19 GSR IM STE Others 0 0 Unknown Unchanged Unchanged Unchanged Unchanged 22 SOFTINT Unknown Unchanged Unchanged ...

Page 155: ...SCRATCH_REGs Unknown Unchanged Unchanged 50 00 IMMU_TAG_TARGET Unknown Unchanged Unchanged 50 18 IMMU_SFSR Unknown Unchanged Unchanged 50 28 IMMU_TSB_BASE Unknown Unchanged Unchanged 50 30 IMMU_TAG_ACCESS Unknown Unchanged Unchanged 50 48 IMMU_TAG_TSB_PEXT Unknown Unchanged Unchanged 50 58 IMMU_TAG_TSB_NEXT Unknown Unchanged Unchanged 51 IMMU_TSB_8KB_PTR Unknown Unchanged Unchanged 52 IMMU_TSB_64K...

Page 156: ...U_DEMAP Unknown Unchanged Unchanged 60 IIU_INST_TRAP 0 Unchanged 6E EIDR 0 Unchanged Unchanged 6F BARRIER_SYNC_P Unknown Unchanged Unchanged 77 40 68 INTR_DATA0 5_W Unknown Unchanged Unchanged 77 70 INTR_DISPATCH_W Unknown Unchanged Unchanged 77 80 88 INTR_DATA6 7_W Unknown Unchanged Unchanged 7F 40 88 INTR_DATA0 7_R Unknown Unchanged Unchanged EF BARRIER_SYNC Unknown Unchanged Unchanged 1 Hard PO...

Page 157: ...U are masked to 41 bits Otherwise the CPU operates in 43 bit PA mode and physical addresses issued by CPU are masked to 43 bits 2 The value of UPA_configuration_register MCAP field OPSR can be set so that when error_state is entered the processor remains halted in error_state instead of generating a watchdog_reset impl dep 254 TABLE O 4 UPA slave register State after Reset and in RED_state PA Name...

Page 158: ...Release 1 0 1 July 2002 F Chapter O Reset RED_state and error_state 147 O 3 2 Hardware Power On Reset Sequence To be defined later O 3 3 Firmware Initialization Sequence To be defined later ...

Page 159: ...148 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 160: ...to which it obstructs program execution 1 Fatal error 2 Error state transition error 3 Urgent error 4 Restrainable error The subsections below describe each error class P 1 1 Fatal Error A fatal error is one of the following errors that damages the entire system a Error breaking data integrity on the system excluding the SDC All errors except the SDC system data corruption error that break cache c...

Page 161: ...t Error An urgent error UGE is an error that requires immediate processing by privileged software which is reported by an error trap The types of urgent errors are listed below and then described in further detail Instruction obstructing error I_UGE Instruction urgent error IAE Instruction access error DAE Data access error Urgent error that is independent of the instruction execution A_UGE Autono...

Page 162: ...instruction access error The instruction_access_error exception as specified in JPS1 Commonality On SPARC64 V only an uncorrectable error in the cache or main memory during instruction fetch is reported to software as an IAE IAE is a precise error DAE data access error The data_access_error exception as specified in JPS1 Commonality On SPARC64 V only an uncorrectable error in the cache or main mem...

Page 163: ...t masked the error is reported to privileged software by the following exceptions I_UGE A_UGE async_data_error exception IAE instruction_access_error exception DAE data_access_error exception P 1 4 Restrainable Error A restrainable error is one that does not adversely affect the currently executing program and that does not require immediate handling by privileged software A restrainable error cau...

Page 164: ...ASI registers in TABLE P 1 except ASI_EIDR and ASI_ERROR_CONTROL are used to specify the nature of an error to privileged software ASI_ERROR_CONTROL Controls error action This register designates error detection masks and error trap enable masks ASI_EIDR Marks errors This register identifies the error source ID for error marking TABLE P 1 lists the registers related to error handling TABLE P 1 Reg...

Page 165: ...y A_UGE Error detection except the register usage is suppressed when ASI_ECR WEAK_ED 1 or upon a condition unique to each error Error detection at the register usage is suppressed by conditions unique to each error Only some A_UGEs have the above unique conditions to suppress error detection most do not None Trap mask the condition to suppress the error trap occurrence None None I_UGE IAE IAE None...

Page 166: ...SI_AFSR 2 When the trap condition for the pending error detection is enabled the ECC_error exception is generated Deviation in SPARC64 V An ECC_error trap can occur even though ASI_AFSR does not indicate any detected error s corresponding to any trap enable bit RTE_UE or RTE_CEDG set to 1 in ASI_ECR in the following cases 1 A pending detected error is erased from ASI_ASFR by writing 1 to ASI_AFSR ...

Page 167: ...struction subsequent in the control flow to the one indicated by TPC For a TLB write error the instruction pointed to by TPC or the already executed instruction previous in the control flow to the one indicated by TPC wrote a TLB entry and the TLB write failed The TLB write error is detected after the instruction execution and before any trap RETRY or DONE instruction A_UGE None IAE DAE The instru...

Page 168: ...memory DIMM it is expected that privileged software will correct the error in memory P 2 4 Error Marking for Cacheable Data Error Error Marking for Cacheable Data Error marking for cacheable data involves the following action Number of errors indicated at trap All FEs are detected and accumulated in ASI_STCHG_ ERROR_INFO All EEs are detected and accumulated in ASI_STCHG_ ERROR_INFO Single ADE trap...

Page 169: ...nnel U2P detect an uncorrected error in the above cacheable data that is not yet marked the CPU and channel execute error marking for the data block with an UE Whether the data with UE is marked or not is determined by the syndrome of the doubleword data as shown in TABLE P 2 The syndrome 7F16 indicates a 3 bit error in the specified location in the doubleword The error marking replaces the origin...

Page 170: ... is the pattern causing the 7F16 syndrome TABLE P 5 ERROR_MARK_ID Bit Description Bit Value 13 12 Module_ID Indicates the type of error source hardware as follows 002 Memory system including DIMM 012 Channel 102 CPU 112 Reserved 11 0 Source_ID When Module_ID 002 the 12 bit Source_ID field is always set to 0 Otherwise the identification number of each Module type is set to Source ID TABLE P 6 ERROR...

Page 171: ...or UPA ECC for UPA Trigger of error marking The detection of a raw UE The detection of a raw UE ERROR_MARK_ID value Value specified in TABLE P 6 Value specified in TABLE P 6 Target data of error marking Note 5 is different 1 D1 cache data 2 U2 cache data 3 Incoming cacheable data from UPA 4 Outgoing cacheable data to UPA for writeback or copyback 5 Incoming interrupt packet data from UPA 1 4 as de...

Page 172: ...E P 8 TABLE P 8 ASI_EIDR Bit Description Bit Name RW Description 63 14 Reserved R Always 0 13 0 ERROR_MARK_ID RW ERROR_MARK_ID for the error caused by the CPU 1 Register name ASI_ERROR_CONTROL ASI_ECR 2 ASI 4C16 3 VA 1016 4 Error checking None 5 Format function See TABLE P 9 6 Initial value at reset Hard POR ASI_ERROR_CONTROL WEAK_ED is set to 1 Other fields are set to 0 Other resets After UGE_HAN...

Page 173: ...ned in TABLE P 2 When a multiple ADE trap is caused I_UGE IAE or DAE detection while ASI_ERROR_CONTROL UGE_HANDLER 1 WEAK_ED is set to 1 by hardware 0 UGE_HANDLER RW Designates whether hardware can expect a UGE handler to run in privileged software operating system when a UGE error occurs 0 Hardware recognizes that the privileged software UGE handler does not run 1 Hardware expects that the privil...

Page 174: ...indications in ASI_STCHG_ERROR_INFO sets all bits in the register including bit 0 to 0 TABLE P 10 Format of ASI_STCHG_ERROR_INFO Bit Description Bit Name RW Description 63 34 Reserved R Always 0 33 ECR_WEAK_ED R ASI_ERROR_CONTROL WEAK_ED is copied into this field at the beginning of a POR or watchdog reset 32 ECR_UGE_HANDLER R ASI_ERROR_CONTROL UGE_HANDLER is copied into this field at the beginnin...

Page 175: ...setting register OSPR is not visible to software and is set by a JTAG command EE_TRAP_ADDR_UNCORRECTED_ERROR When hardware calculated the trap address to cause a trap the valid address could not be obtained because of a UE in ASI_TBA a UE in tt or a UE in the address calculator Other error_state transition errors Current SPARC64 V implementation When hardware detects an error_state transition erro...

Page 176: ...ribes the fields of the ASI_UGESR register In the table the prefixes in the name field have the following meaning IUG_ Instruction Urgent error IAG_ Autonomous Urgent error IAUG_ The error detected as both I_UGE and A_UGE 1 Register name ASI_URGENT_ERROR_STATUS 2 ASI 4C16 3 VA 0816 4 Error checking None 5 Format function See TABLE P 11 6 Initial value at reset Hard POR All fields are set to 0 Othe...

Page 177: ...is not erased by instruction retry IA SOFTINT IA STICK IA STICK_COMP 21 IAUG_TSBCTXT R Uncorrectable error in any of the following IA ASI_DMMU_TSB_BASE IA ASI_DMMU_TSB_PEXT IA ASI_DMMU_TSB_SEXT IA ASI_DMMU_TSB_NEXT IA ASI_PRIMARY_CONTEXT IA ASI_SECONDARY_CONTEXT IA ASI_IMMU_TSB_BASE IA ASI_IMMU_TSB_PEXT IA ASI_IMMU_TSB_SEXT 20 IUG_TSBP R Uncorrectable error in any of the following I ASI_DMMU_TAG_T...

Page 178: ...during a data TLB access An uncorrectable error in TLB data or TLB tag was detected when an LDXA instruction attempted to read ASI_DTLB_DATA_ACCESS or ASI_DTLB_TAG_ACCESS TPC indicates either the instruction causing the error or the previous instruction A store to the data TLB or a demap of the data TLB failed TPC indicates either the instruction causing the error or the instruction following the ...

Page 179: ...tryable See Section P 4 3 for the instruction end method for the async_data_error trap When a watchdog timeout is detected the instruction end method is undefined 3 PRIV R Privileged mode Upon a single async_data_error trap the PRIV field is set as follows When the value of PSTATE PRIV immediately before the single ADE trap is unknown because of an uncorrectable error in PSTATE ASI_UGESR PRIV is s...

Page 180: ...s are updated a Update and validation of specific registers Hardware writes the registers listed in TABLE P 12 The error s in a written register are removed by setting the correct value to the error checking parity code during the full write of the register TABLE P 12 Registers Written for Update and Validation Register Condition For Writing Value Written PSTATE Always AG 1 MG 0 IG 0 IE 0 PRIV 1 A...

Page 181: ...he ADE trap the trapped instruction referenced by TPC ends by using one of the following instruction end methods Precise Retryable but not precise not included in JPS1 Not retryable not included in JPS1 Upon a single ADE trap the trapped instruction end method is indicated in ASI_UGESR INSTEND TABLE P 13 ASI_UGESR Update for Single and Multiple ADE Exceptions Bit Field Update upon a Single ADE Tra...

Page 182: ...ion The trapped instruction referenced by TPC Not executed The output of the instruction is incomplete Part of the output may be changed or the invalid value may be written to the instruction output However the modification to the invalid target that is not defined as instruction output is not executed The following modifications are not executed Store to the cacheable area including cache Store t...

Page 183: ...red r1 r7 to the ADE trap save area using rX rY ASI_SCRATCH_REGp and ASI_SCRATCH_REGq whole r save and restore is required to retry the context with PSTATE AG 1 if ASI_UGESR IUG_PSTATE 1 tstate pstate r0 tpc r0 pil r0 wstate r0 All general purpose registers in the register window r0 Set the register window control registers CWP CANSAVE CANRESTORE OTHERWIN CLEANWIN to appropriate values Point 1 Pro...

Page 184: ...INSTEND 1 ADE_trap_retry_per_unit_of_time if ADE_trap_retry_per_unit_of_time threshold resume the trapped context by use of the RETRY instruction else invoke panic routine because of too many ADE trap retries else if ASI_UGESR bits22 18 0 ASI_UGESR bits15 14 0 ASI_UGESR PRIV 0 ADE_trap_kill_user_per_unit_of_time if ADE_trap_kill_user_per_unit_of_time threshold kill one user process trapped and con...

Page 185: ...BLE P 15 row as follows If the Prio_D1 column for the error shown in the table row is blank the error is never recorded into ASI_AFAR_D1 Otherwise the Prio_D1 column for the error shown in the table row indicates the ASI_AFAR_D1 recording priority as follows Let P_D1 be the Prio_D1 column value for the error E1 Then Upon detection of the error E1 if P_D1 ASI_AFAR_D1 CONTENTS the error E1 is record...

Page 186: ...sable condition specified in the TABLE P 2 is not satisfied an ECC_error trap is generated 10 DG_L1 U2 STLB RW1C Degradation in L1 U2 and sTLB This bit is set when automatic way reduction is applied in I1 D1 U2 sITLB or sDTLB See Section P 9 5 and Section P 10 2 for further details about when this bit is set 9 CE_INCOMED RW1C 4016 Correctable error in incoming data from the UPA bus CE is detected ...

Page 187: ...rror should be detected in the following cases L2 cache data is read to fill D1 cache or I1 cache L2 cache data is read for copyback or writeback The doubleword containing the raw UE in the read data and the doubleword in the L2 cache data are marked with ERROR_MARK_ID ASI_EIDR Implementation Deviation SPARC64 V sets UE_RAW_L2 INSD to 1 only when a raw UE is detected during L2 cache writeback 0 UE...

Page 188: ...er fields of ASI_AFAR_D1 as defined in TABLE P 15 Controls the recording of newly detected restrainable errors Upon detection of a new restrainable error recordable in ASI_AFAR_D1 if the current ASI_AFAR_D1 CONTENTS the AFSR Prio_D1 value of the new error the new error is recorded into ASI_AFAR_D1 If the current ASI_AFAR_D1 CONTENTS the AFSR Prio_D1 value of the new error the error is not recorded...

Page 189: ... is expected TABLE P 17 ASI_ASYNC_FAULT_ADDR_U2 ASI_AFAR_U2 Register Bit Description Bit Name R W Description 63 56 CONTENTS R Contents of ASI_AFAR_U2 This field has the following two functions Indicates the type of error held in the other fields of ASI_AFAR_U2 as defined in TABLE P 15 Controls the recording of newly detected restrainable errors Upon the detection of a new restrainable error recor...

Page 190: ...nce to correct the memory block is expected a Make the U2 cache line with the CE detection dirty without changing the data Use the CASA instruction to write that same data to the U2 cache line 42 3 PA_BIT42_3 R Physical address bit 42 3 Contains the value indicated by ASI_AFAR_U2 CONTENTS as shown below Others Reserved R Always read as 0 All W Any write access sets all fields in this register to 0...

Page 191: ...entry is specified or Invalid memory access instruction with physical address access ASI is executed in privileged software This error is always caused by a mistake in privileged software Record the error and correct the erroneous privileged software ASI_AFSR UE_RAW_L2 FILL UE_RAW_L2 INSD and UE_RAW_D1 INSD Software handles these errors as follows Correct the cache line data containing the uncorre...

Page 192: ...hen an instruction performs a full write to the register ADE trap The error is removed by a full write to the register in the async_data_error hardware trap sequence TABLE P 18 Register Error Handling Excluding ASRs and ASI Registers Register Name RW Error Protect Error Detect Condition Error Type Correction rn RW Parity InstAccess IUG_ R W fn RW Parity InstAccess IUG_ F W PC Parity Always IUG_PST...

Page 193: ...sses the register Error Type I AUG_xxx The error is indicated by ASI_UGESR IAUG_xxx 1 and the error is an autonomous urgent error I A UG_xxx The error is indicated by ASI_UGESR IAUG_xxx 1 and the error is an instruction urgent error Correction W The error is removed by a full write to the register by an instruction ADE trap The error is removed by a full write to the register in the async_data_err...

Page 194: ...ways InstAccess I AUG_CRE I A UG_CRE W W 23 TICK_COMPARE RW None 24 STICK RW Parity AUG always InstAccess I AUG_CRE I A UG_CRE W W 25 STICK_COMPARE RW Parity AUG always InstAccess I AUG_CRE I A UG_CRE W W 1 of 3 Column Term Meaning Error Protect Parity Parity protected ECC ECC double bit error detection single bit error correction protected Gecc Generated ECC PP Parity propagation The parity error...

Page 195: ...UE and the register is used for the calculation of ASI_DMMU_TSB_PTR registers the UE is propagated to the ASI_DMMU_TSB_PTR registers Upon execution of the LDXA instruction to read ASI_DMMU_TSB_PTR with the propagated UE the IUG_TSBP error is detected ITLB write Error is checked at the ITLB update timing after completion of the STXA instruction to write or demap an ITLB entry DTLB write Error is ch...

Page 196: ...gent errors is exceeded on the processor Others The name of the bit set to 1 in ASI_UGESR indicates the error type Correction RED trap The whole register is updated and corrected when a RED_state trap occurs W The whole register is updated and corrected by use of an STXA instruction to write the register W1AC The whole register is updated and corrected by use of an STXA instruction to write 1 to t...

Page 197: ...G_TARGET R Parity LDXA I IUG_TSBP WotherI 5016 1816 IMMU_SFSR RW None 5016 2816 IMMU_TSB_BASE RW Parity LDXA I I A UG_TSBCTXT W 5016 3016 IMMU_TAG_ACCESS RW Parity LDXA I IUG_TSBP W WotherI 5016 4816 IMMU_TSB_PEXT RW Parity ITSB_BASE IAUG_TSBCTXT W 5016 5816 IMMU_TSB_NEXT R Parity ITSB_BASE IAUG_TSBCTXT W 5116 IMMU_TSB_8KB_PTR R PP LDXA IUG_TSBP WotherI 5216 IMMU_TSB_64KB_PTR R PP LDXA IUG_TSBP Wo...

Page 198: ...UG_DTLB DemapAll 5D16 DTLB_DATA_ACCESS RW Parity LDXA DTLB write IUG_DTLB IUG_DTLB DemapAll DemapAll 5E16 DTLB_TAG_READ R Parity LDXA IUG_DTLB DemapAll 5F16 DMMU_DEMAP W Parity DTLB write IUG_DTLB DemapAll 6016 IIU_INST_TRAP RW Parity LDXA No match at error W 6E16 0016 EIDR RW Parity Always IAUG_CRE W 6F16 parallel barrier assist RW Parity AUG always LDXA BV interface Not detected dv COREERROR dv ...

Page 199: ...tic way reduction in the I1 D1 and U2 caches P 9 1 Handling of a Cache Tag Error Error in D1 Cache Tag and I1 Cache Tag Both the D1 cache Data level 1 and the I1 cache Instruction level 1 maintain a copy of their cache tags in the U2 unified level 2 cache The D1 cache tags the D1 cache tags copy the I1 cache tags and the I1 cache tags copy are each protected by parity TABLE P 21 Ideal Handling of ...

Page 200: ...ction ECC code When a correctable error is detected in a U2 cache tag hardware automatically corrects the error by rewriting the corrected data into the U2 cache tag entry The error is not reported to software When an uncorrectable error is detected in a U2 cache tag one of following actions is taken depending on the setting of OPSR internal mode register set by the JTAG command 1 A fatal error is...

Page 201: ...illing data b When the doubleword has a marked UE set the parity bit in the I1 cache doubleword to indicate a parity error and supply the parity error data for the instruction fetch if required 3 Treat a fetched instruction with an error as follows When the instruction with a parity error is fetched but not executed in any way visible to software the fetched instruction with the error is discarded...

Page 202: ...The restrainable error ASI_AFSR UE_RAW_D1 INSD is detected Raw Uncorrectable Error in D1 Cache Data on Access by Load or Store Instruction When a raw unmarked UE is detected in D1 cache data during access by a load or store instruction hardware executes the following sequence 1 Hardware writes back the D1 cache line and refills it from U2 cache The D1 cache line containing the raw UE whether it is...

Page 203: ...is stored without modification in the target U2 cache line When a marked uncorrectable error is detected in incoming data from the D1 cache to writeback D1 cache line the doubleword with the marked UE is stored without modification in the target U2 cache line Note that there is no raw UE in D1 writeback data because error marking is applied for D1 writeback data as described in Handling of a D1 Ca...

Page 204: ...ache For each way of the I1 cache Parity error in I1 cache tag or I1 cache tag copy I1 cache data parity error For each way of the D1 cache Parity error in D1 cache tag or D1 cache tag copy Correctable error in D1 cache data Raw UE in D1 cache data For each way of U2 cache Correctable error and uncorrectable error in U2 cache tag Correctable error in U2 cache data Raw UE in U2 cache data If an err...

Page 205: ...Way Reduction When a way reduction condition is recognized for a U2 cache way the U2 cache way reduction procedure is executed as follows 1 When ASI_L2CTL WEAK_SPCA 0 the U2 cache way reduction procedure below is started immediately 2 Otherwise when ASI_L2CTL WEAK_SPCA 1 is set the U2 cache way reduction procedure below becomes pending until ASI_L2CTL WEAK_SPCA is changed to 0 When ASI_L2CTL WEAK_...

Page 206: ...uction Virtual address translation sTLB Virtual address translation fTLB Error in TLB Entry Detected on LDXA Instruction Access If a parity error is detected in a DTLB entry when an LDXA instruction attempts to read ASI_DTLB_DATA_ACCESS or ASI_DTLB_TAG_ACCESS hardware automatically demaps the entry and an instruction urgent error is indicated in ASI_UGESR IUG_DTLB TABLE P 22 Error Protection and D...

Page 207: ... as the locked TLB entry A parity error in fTLB entry data is detected only when the tag of the fTLB entry matches a virtual address When a parity error in the fITLB is detected at the time of an instruction fetch a precise instruction_access_error exception is generated The parity error in the fITLB entry and the fITLB entry index is indicated in ASI_IFSR When a parity error in fDTLB is detected ...

Page 208: ...he extended UPA address bus is protected by a parity bit attached to every 8 bits When the SPARC64 V processor detects a parity error in the extended UPA address bus the processor takes one of the following actions depending on the OPSR setting 1 Upon detection of the error the processor enters the CPU fatal error state 2 Upon detection of the autonomous urgent error ASI_UGESR AUG_SDC the processo...

Page 209: ...processor detects a marked UE in such data the processor transfers that data to the destination register or cache without modification The error is not reported to software when the marked UE is received at the extended UPA data bus interface Raw UE in incoming data from the extended UPA data bus When the processor detects a raw UE in such data the processor applies error marking to that data The ...

Page 210: ...ta Bus At the time data is sent to the extended UPA bus a SPARC64 V processor handles a UE in data outgoing data as follows Marked UE in outgoing data to the extended UPA data bus When the processor detects such data the processor transfers the data without modification and does not report the error to software on the processor Raw UE in outgoing data to the extended UPA data bus When the processo...

Page 211: ...200 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 212: ...age 208 UPA Event Counters on page 210 Miscellaneous Counters on page 211 Q 1 Performance Monitor Overview For the definitions of performance counter registers please refer to Performance Control Register PCR ASR16 and Performance Instrumentation Counter PIC Register ASI 17 in Chapter 5 of Commonality Q 1 1 Sample Pseudocodes Counter Clear Set The PICs are read write registers see Performance Inst...

Page 213: ...nts and enables counters assuming privileged access pcr ut 0x0 initially disable user counts pcr st 0x0 initially disable system counts pcr ulro 0x0 make sure read only disabled pcr ovro 0x1 do not modify overflow bits select the events without enabling counters for i 0 i pcr nc i pcr sc i pcr sl select an event pcr su select an event wr_pcr pcr start counting pcr ut 0x1 pcr st 0x1 pcr ulro 0x1 fo...

Page 214: ...vents in Group 1 are counted on commit of the instructions The instructions executed speculatively are not counted Events in groups 2 through 5 are counted when they occur All event counters implemented in SPARC64 V are listed in TABLE Q 1 TABLE Q 1 Events and Encoding of Performance Monitor Encoding Counter picu0 picl0 picu1 picl1 picu2 picl2 picu3 picl3 000000 cycle_counts 000001 instruction_cou...

Page 215: ... Reserved 010110 trap_all trap_int_vector trap_int_level trap_spill trap_fill trap_trap_inst trap_IMMU _miss trap_DMMU _miss 010111 Reserved 100000 Reserved write_if_uTLB write_op_uTLB if_r_iu_req_mi _go op_r_iu_req _mi_go if_wait_all op_wait_all 100001 Reserved 100010 Reserved 100011 Reserved 110000 sx_miss _wait_dm sx_miss_wait _pf sx_miss_count _dm sx_miss_count_ pf sx_read_count _dm sx_read_co...

Page 216: ...ore_instructions Counts the committed load store instructions Also counts atomic load store instructions Branch Instruction Count branch_instructions Counts the committed branch instructions Also counts CALL JMPL and RETURN instructions Floating Point Instruction Count floating_instructions Counts the committed floating point operations FPop1 and FPop2 Does not count Floating Point Multiply and Ad...

Page 217: ...Interrupt Vector Trap Count trap_int_vector Counts the occurrences of interrupt_vector_trap Level Interrupt Trap Count trap_int_level Counts the occurrences of interrupt_level_n Spill Trap Count trap_spill Counts the occurrences of spill_n_normal spill_n_other Fill Trap Count trap_fill Count the occurrences of fill_n_normal fill_n_other Counter Any Encoding 0011002 Counter picu0 Encoding 0101102 C...

Page 218: ...ss Counts the occurrences of fast_data_instruction_access_MMU_miss Q 2 3 MMU Event Counters Instruction uTLB Miss write_if_uTLB Counts the occurrences of instruction uTLB misses Data uTLB Miss write_op_uTLB Counts the occurrences of data uTLB misses Note Occurrences of main TLB misses are counted by trap_IMMU_miss trap_DMMU_miss Counter picl2 Encoding 0101102 Counter picu3 Encoding 0101102 Counter...

Page 219: ... the total latency of D1 cache misses L2 Cache Miss Wait Cycle by Demand Access sx_miss_wait_dm Counts the number of cycles from the occurrence of an L2 cache miss to data returned caused by demand access L2 Cache Miss Wait Cycle by Prefetch sx_miss_wait_pf Counts the number of cycles from the occurrence of an L2 cache miss to data returned caused by both software prefetch and hardware prefetch ac...

Page 220: ...es by demand read access L2 Cache Reference by Prefetch sx_read_count_pf Counts L2 cache references by both software prefetch and hardware prefetch access DVP Count by Demand Miss dvp_count_dm Counts the occurrences of L2 cache miss by demand with writeback request DVP Count by Prefetch Miss dvp_count_pf Counts the occurrences of L2 cache miss by both software prefetch and hardware prefetch with w...

Page 221: ...number of S_CPB_REQ packets received CPD Receive Count sreq_cpd_count Counts the number of S_CPD_REQ packets received UPA Address Bus Busy Cycle upa_abus_busy Counts the number of bus busy cycles of the UPA address bus in units of UPA bus clocks not in units of CPU clocks UPA Data Bus Busy Cycle upa_data_busy Counts the number of bus busy cycles of the UPA data bus in units of UPA bus clocks not i...

Page 222: ...nters Barrier Assist ASI Read Count asi_rd_bar Counts the number of read accesses to the barrier assist ASI registers Barrier Assist ASI Write Count asi_wr_bar Counts the number of write accesses to the barrier assist ASI registers Counter picu3 Encoding 1100012 Counter picl3 Encoding 1100012 ...

Page 223: ...212 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 224: ... CPU s UPA Port Slave Area on page 213 UPA PortID Register on page 214 UPA Config Register on page 215 R 1 Mapping of the CPU s UPA Port Slave Area TABLE R 1 shows the mapping of the CPU s UPA port slave area TABLE R 1 CPU s UPA Port Slave Area Mapping Relative Address Hex Length Possible Access Contents 0 0000 0000 8 Slave read from other UPA port UPA PortID Register defined in Section R 2 0 0000...

Page 225: ...SREQs 34 ECC ECCNotValid Signifies that this UPA port does not support ECC Set to 0 33 ONE ONE_READ Signifies that this UPA port supports only one outstanding slave read P_REQ transaction at a time Set to 0 32 31 PINT_RDQ PINT_RDQ 1 0 Encodes the size of the PINT_RQ and PINT_DQ queues Specifies the number of incoming P_INT_REQ requests that the slave port can receive Specifies the number of 64 byt...

Page 226: ... an interrupt handler UPACAP 3 Set CPU is an interrupter UPACAP 2 Clear CPU does not use UPA Slave_Int_L signal UPACAP 1 Set CPU is a cache master UPACAP 0 Set CPU has a master interface 1 Register Name ASI_UPA_CONFIGURATION_REGISTER 2 ASI 4A16 3 VA 0 4 RW Supervisor read a write is ignored 5 Data Reserved WB_S WRI_ S INT_S Reserved UC_S Reserved AM MCAP Reserved CLK_MODE PCON UPC_ CAP2 MID UPC_CA...

Page 227: ...2 2 MB 42 41 Reserved Read as 0 40 39 AM Address Mode Specifies the physical address size of UPA address field 002 41 bits 012 43 bits 102 112 Reserved 38 35 MCAP The value set by OPSR is indicated Consult the system document for the meaning and encoding of this field 34 Reserved Read as 0 33 30 CLK_MODE Specify the ratio between CPU clock and UPA clock 00002 00112 Reserved 01002 4 1 01012 5 1 011...

Page 228: ...class 0 request queue in the System Controller SC 00002 1 00012 00102 1 but should not be specified for the extension 00112 4 01002 11102 4 but should not be specified for the extension 11112 16 22 UPC_CAP2 This field is connected to the UPA Port ID register bit 35 SREQ_S field 21 17 MID Module Processor ID register Identifies the unique processor ID This value is loaded from the UPA_MasterID 4 0 ...

Page 229: ...218 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 230: ...64 V supports a 43 bit physical address In addition the CV bit is ignored and unaliasing is maintained by hardware 86 UltraSPARC III supports a 43 bit physical address Millennium will support a 47 bit PA F 2 TLB locking mechanism Lock entries are supported in both fully associative ITLB fITLB and fully associative DTLB fDTLB 32 entry each 86 Lock entries supported only in the 16 entry fully associ...

Page 231: ...is not needed Because the data cache uses one virtual address bit for indexing a displacement flushing algorithm or a cache diagnostic write is required when a virtual address alias is created 1 4 4 M 2 TPC TNPC state after power on reset Both TPC and TNPC values are undefined after a power on reset 141 TPC 5 0 is zero after any reset trap TNPC will be equal to TNPC 4 C 2 5 W cache SPARC64 V does ...

Page 232: ...n Array Not supported ASIs 6616 through 6816 and ASI 6F16 support instruction cache and branch prediction array diagnostic access V 4 V 5 MCU Control Register SPARC64 V does not have an MCU ASI 7216 MCU Control Register App U Module ID bits Implements 5 bit IDs 136 Implements 10 bit IDs R 2 Performance counters SPARC64 V implements a different set of performance counters than those of UltraSPARC I...

Page 233: ...222 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 234: ...223 F CHAPTER Bibliography General References Please refer to Bibliography in Commonality ...

Page 235: ...224 SPARC JPS1 Implementation Supplement Fujitsu SPARC64 V Release 1 0 1 July 2002 ...

Page 236: ... method170 registers written for update validation169 software handling171 state transition169 AFSR FTYPE field120 121 ASI_AFAR221 ASI_AFAR_D1166 ASI_AFAR_D1 register186 ASI_AFAR_U2166 178 CONTENTS179 ASI_AFAR_U2 register186 ASI_AFSR174 220 ASI_ASYNC_FAULT_ADDR_D1153 177 ASI_ASYNC_FAULT_ADDR_U2153 178 ASI_ASYNC_FAULT_STATUS153 174 ASI_ATOMIC_QUAD_LDD_PHYS54 104 117 ASI_ATOMIC_QUAD_LDD_PHYS_LITTLE5...

Page 237: ...MU_TSB_PEXT166 ASI_DMMU_TSB_PTR184 ASI_DMMU_TSB_SEXT166 ASI_DTLB_DATA_ACCESS195 ASI_DTLB_TAG_ACCESS195 ASI_ECR161 UGE_HANDLER155 ASI_EIDR153 161 166 187 191 221 ASI_ERROR_CONTROL153 161 UGE_HANDLER168 189 update after ADE170 WEAK_ED150 189 ASI_FLUSH_L1I126 129 ASI_IESR118 ASI_IMMU_SFSR153 ASI_IMMU_TAG_ACCESS166 ASI_IMMU_TAG_TARGET166 ASI_IMMU_TSB_64KB_PTR166 ASI_IMMU_TSB_8KB_PTR166 ASI_IMMU_TSB_BA...

Page 238: ...BYPASS_EC_WITH_E_BIT_LITTLE127 ASI_PHYS_BYPASS_WITH_EBIT26 ASI_PRIMARY57 98 101 ASI_PRIMARY_AS_IF_USER57 ASI_PRIMARY_AS_IF_USER_LITTLE57 ASI_PRIMARY_CONTEXT166 ASI_PRIMARY_LITTLE57 101 ASI_SCRATCH120 ASI_SECONDARY57 ASI_SECONDARY_AS_IF_USER57 ASI_SECONDARY_AS_IF_USER_LITTLE57 ASI_SECONDARY_CONTEXT166 ASI_SECONDARY_LITTLE57 ASI_SERIAL_ID119 ASI_STCHG_ERROR_INFO153 164 ASI_UGESR165 IUG_DTLB195 ASI_U...

Page 239: ... busy status register123 BSTW control register123 bus busy cycle count210 bypass attribute bits104 C cache coherence128 140 data cache tag error handling188 189 characteristics127 data error detection190 description7 flushing220 modification125 protection190 uncorrectable data error191 way reduction194 error protection3 event counting208 209 instruction characteristics126 data protection190 descri...

Page 240: ...CE correction157 counting in D1 cache data193 in D1 cache data190 detection175 197 effect on CPU152 permanent180 in U2 cache tag189 CLEANWIN register75 166 CLEAR_SOFTINT register183 cmask field56 committed definition9 compare and swap instructions37 completed definition9 context ID hashing93 counter disabling reading202 enabling202 instruction statistics204 overflow in PIC 22 trap related statisti...

Page 241: ...II221 error handling183 nonprivileged access22 DCU_CONTROL register186 DCUCR access data format23 CP cacheability field23 CV cacheability field23 data watchpoint masks57 DC data cache enable field24 DM DMMU enable field23 field setting after POR23 IC instruction cache enable field24 IM field126 140 IMI IMMU enable field23 PM PA data watchpoint mask field23 PR PW PA watchpoint enable fields23 updat...

Page 242: ... register187 DMMU_TAG_TARGET register186 DMMU_TSB_64KB_PTR register187 DMMU_TSB_8KB_PTR register187 DMMU_TSB_BASE register186 DMMU_TSB_DIRECT_PTR register187 DMMU_TSB_NEXT register187 DMMU_TSB_PEXT register187 DMMU_TSB_SEXT register187 DMMU_VA_WATCHPOINT register187 DSFAR on JMPL instruction error53 update during MMU trap90 DSFSR bit description100 differences from UltraSPARC III221 format97 FT fi...

Page 243: ...ing ASI errors186 ASR errors182 most registers181 isolation3 marking differences between SPARC64 IV and SPARC64 V160 restrainable152 source identification159 transition150 U2 cache tag189 uncorrectable189 D1 cache data191 without direct damage152 urgent150 ERROR_CONTROL register186 ERROR_MARK_ID158 159 191 error_state36 72 138 140 155 169 error_state transition error164 exceptions catastrophic37 d...

Page 244: ...on_access_MMU_miss exception46 89 99 100 207 fatal error behavior of CPU150 cache tag189 definition149 detection163 types164 U2 cache tag189 fDTLB77 85 90 91 fe_other164 fe_u2tag_uncorrected_error164 fe_upa_addr_uncorrected_error164 fetched definition9 fill_n_normal exception206 fill_n_other exception206 finished definition9 fITLB77 85 90 floating point deferred trap queue FQ 17 24 denormal operan...

Page 245: ...n28 fp_disabled exception30 48 53 57 74 fp_exception_ieee_754 exception53 65 fp_exception_other exception46 62 79 FQ17 24 FSR aexc field19 cexc field18 19 conformance19 NS field62 TEM field19 VER field18 fTLB78 87 94 G GSR register183 H high speed synchronization121 I I_UGE definition151 error detection action155 162 error detection mask154 type150 IAE error detection action155 error detection mas...

Page 246: ...uctions49 50 impl field of VER register18 implementation number impl field of VER register71 initiated definition9 instruction execution25 formats28 prefetch26 instruction fields reserved45 instruction_access_error exception46 90 98 100 130 152 196 199 instruction_access_exception exception46 90 99 100 instruction_access_MMU_miss exception46 instructions atomic load store37 blocked10 cache manipul...

Page 247: ...atch Register136 Interrupt Vector Receive Register136 interrupt_level_n exception206 interrupt_vector_trap exception38 206 INTR_DATA0 7_R register error handling187 INTR_DATA0 7_W register error handling187 INTR_DISPATCH_STATUS register133 186 INTR_DISPATCH_W register187 INTR_RECEIVE register186 I SFSR update during MMU trap90 ISFSR bit description98 differences from UltraSPARC III221 format97 FT ...

Page 248: ... LDXA instruction178 185 195 load quadword atomic54 LoadLoad MEMBAR relationship56 load store instructions compare and swap37 D1 cache data errors191 memory model47 LoadStore MEMBAR relationship56 Lookaside MEMBAR relationship56 M machine sync10 MAXTL36 73 138 140 MCNTL NC_CACHE126 127 mem_address_not_aligned exception54 80 90 103 120 129 MEMBAR LoadLoad56 LoadStore56 Lookaside56 MemIssue56 StoreL...

Page 249: ...dd Subtract instructions53 N noncacheable access54 126 nonleaf routine53 nonspeculative distribution10 nonstandard floating point NS field of FSR register18 71 nonstandard floating point mode18 62 O OBP facilitating diagnostics126 notification of error163 resetting WEAK_ED150 validating register error handling181 with urgent error151 Operating Status Register OPSR 37 140 216 221 OTHERWIN register7...

Page 250: ...field21 OVRO field21 PRIV field20 58 59 SC field21 202 SL field202 ST field204 SU field202 UT field204 performance monitor events encoding203 groups203 pessimistic overflow65 pessimistic zero64 PIC register clearing201 counter overflow22 error handling183 nonprivileged access22 OVF field22 PIL register38 POR reset155 161 163 174 resets POR178 power on reset POR DCUCR settings23 implementation depe...

Page 251: ...5 program order26 PSTATE register AM field29 49 53 75 IE field134 135 MM field42 PRIV field20 58 59 RED field20 126 140 141 PTE E field26 Q quadword load ASI54 queues11 R RDPCR instruction20 58 RDTICK instruction19 reclaimed status10 RED_state156 169 entry after failure reset36 entry after SIR138 entry after WDR140 entry after XIR138 entry trap17 processor states140 141 restricted environment36 se...

Page 252: ...t SIR 138 WDR146 resets POR155 161 163 174 WDR155 163 restorable windows CANRESTORE register75 restrainable error definitions152 handling ASI_AFSR CE_INCOMED179 ASI_AFSR UE_DST_BETO180 ASI_AFSR UE_RAW_L2 FILL180 UE_RAW_D1 INSD180 UE_RAW_L2 INSD180 software handling179 types152 Return Address Stack use in JMPL instruction53 with CALL and JMP instructions30 return prediction hardware30 rs3 field of ...

Page 253: ...ction 10 STBAR instruction59 STCHG_ERROR_INFO register186 STD instruction37 STDA instruction37 STDFA instruction120 STICK register166 183 STICK_COMP register166 STICK_COMPARE register183 sTLB78 87 94 store order STO memory model75 store queue7 StoreLoad MEMBAR relationship56 StoreStore MEMBAR relationship56 STQF_mem_address_not_aligned exception46 STXA instruction ASI read method178 stxa instructi...

Page 254: ...cteristics77 in TLB organization85 main10 36 multiple hit detection86 replacement algorithm93 TNP register166 total store order TSO memory model41 42 TPC register166 transition error150 traps deferred37 disrupting17 37 precise17 TSB Base Register97 Extension Register97 size97 TSTATE register CWP field19 error bit in ASI_UCESR register166 TTE CV field126 differences from UltraSPARC III219 U U2 cach...

Page 255: ...area213 PortID register214 UPA_CONFIGUATION register error handling186 UPA_XIR_L pin138 urgent error definition150 types A_UGE150 DAE150 IAE150 instruction obstructing150 URGENT_ERROR_STATUS register186 uTLB10 36 86 V VA_watchpoint exception103 var field of instructions28 VER register20 119 221 version ver field of FSR register71 W watchdog timeout164 167 189 watchdog_reset WDR 37 80 140 146 221 w...

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