Fujitsu MJA2080BH Page 236 Product/Maintenance Manual Download

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Interface

5-162

C141-E293

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SCT COMMAND SET (SN = E0h)

Refer to SMART Command Transport (SCT).

At command issuance (Shadow Block Registers setting)

0 0 1 1 1 1 1 1

DH 1

CH EXP

CL EXP

SN EXP

SC EXP

FR EXP

00h

E0h

00h

01h

At command completion (Shadow Block Registers contents to be read)

ST Status

information

DH x

CH EXP

CL EXP

SN EXP

SC EXP

Error information

Summary of Contents for MJA2080BH

Page 1: ...C141 E293 01EN MJA2500BH MJA2400BH MJA2320BH MJA2250BH MJA2160BH MJA2120BH MJA2080BH DISK DRIVES PRODUCT MAINTENANCE MANUAL ...

Page 2: ...ncidental or consequential damages arising therefrom FUJITSU DISCLAIMS ALL WARRANTIES REGARDING THE INFORMATION CONTAINED HEREIN WHETHER EXPRESSED IMPLIED OR STATUTORY FUJITSU reserves the right to make changes to any products described herein without further notice and without obligation This product is designed and manufactured for use in standard applications such as office work personal device...

Page 3: ...Revision History 1 1 Edition Date Revised section 1 Added Deleted Altered Details 01 2008 10 01 1 Section s with asterisk refer to the previous edition when those were deleted C141 E293 ...

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Page 5: ...rview of the disk drive and describes their features CHAPTER 2 Device Configuration This chapter describes the internal configurations of the disk drive and the configuration of the systems in which they operate CHAPTER 3 Installation Conditions This chapter describes the external dimensions installation conditions and switch settings of the disk drive CHAPTER 4 Theory of Device Operation This cha...

Page 6: ...her property may occur if the user does not perform the procedure correctly This indicates information that could help the user use the product more efficiently In the text the alert signal is centered followed below by the indented message A wider line space precedes and follows the alert message to show where the alert message begins and ends The following is an example Example Data corruption A...

Page 7: ...ity depends on the operating environment and formatting Attention Please forward any comments you may have regarding this manual To make this manual easier for users to understand opinions from readers are needed Please write your opinions or requests on the Comment at the back of this manual and forward it to the address described in the sheet Liability Exception Disk drive defects refers to defe...

Page 8: ...nditions of use i e without hot plugging observe the important alert messages and notes on safety precautions given in this manual For the electrical recommendation to the host system which supports hot plugging with this drives refer to Section 5 1 6 Compliance with Administration on the Control of Pollution Caused by Electronic Information Products of the People s Republic of China This product ...

Page 9: ... sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device disconnect the body ground 500 kΩ or greater Do not touch the printed circuit board but hold it by the edges 3 7 Mai...

Page 10: ...ver under any circumstances Doing so may cause irreparable damage to the cover Device damage The DE is completely sealed Do not open the DE in the field 7 3 Data corruption When asking for repair save all data stored in the disk drive beforehand Fujitsu Limited is not responsible for any loss of data during service and repair 7 4 Device damage The disk enclosure DE must never to be opened in the f...

Page 11: ... MJA2250BH MJA2160BH MJA2120BH MJA2080BH DISK DRIVES PRODUCT MAINTENANCE MANUAL C141 E293 This manual Device Overview Device Configuration Installation Conditions Theory of Device Operation Interface Operations Maintenance and Diagnosis C141 E293 vii ...

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Page 13: ...ifications 1 10 1 5 Acoustic Noise 1 11 1 6 Shock and Vibration 1 11 1 7 Reliability 1 12 1 8 Error Rate 1 13 1 9 Media Defects 1 13 1 10 Load Unload Function 1 13 1 10 1 Recommended power off sequence 1 14 1 11 Advanced Power Management APM 1 14 1 12 Interface Power Management IPM 1 16 1 12 1 Host initiated interface power management HIPM 1 16 1 12 2 Device initiated interface power management DI...

Page 14: ... cable connection 3 11 3 3 5 Note about SATA interface cable connection 3 11 CHAPTER 4 Theory of Device Operation 4 1 4 1 Outline 4 2 4 2 Subassemblies 4 2 4 2 1 Disk 4 2 4 2 2 Spindle 4 2 4 2 3 Actuator 4 2 4 2 4 Air filter 4 3 4 3 Circuit Configuration 4 3 4 4 Power on Sequence 4 6 4 5 Self calibration 4 8 4 5 1 Self calibration contents 4 8 4 5 2 Execution timing of self calibration 4 9 4 5 3 C...

Page 15: ...outs 5 7 5 1 5 P11 function 5 8 5 1 6 Hot Plug 5 10 5 2 Logical Interface 5 11 5 2 1 Communication layers 5 12 5 2 2 Outline of the Shadow Block Register 5 13 5 2 3 Outline of the frame information structure FIS 5 14 5 2 4 Shadow block registers 5 22 5 3 Host Commands 5 27 5 3 1 Command code and parameters 5 27 5 3 2 Command descriptions 5 30 1 RECALIBRATE X 10 to X 1F 5 31 2 READ SECTOR S X 20 or...

Page 16: ...AD BUFFER X E4 5 100 24 FLUSH CACHE X E7 5 101 25 WRITE BUFFER X E8 5 102 26 IDENTIFY DEVICE X EC 5 103 27 IDENTIFY DEVICE DMA X EE 5 104 28 SET FEATURES X EF 5 119 29 SECURITY SET PASSWORD X F1 5 126 30 SECURITY UNLOCK X F2 5 128 31 SECURITY ERASE PREPARE X F3 5 130 32 SECURITY ERASE UNIT X F4 5 131 33 SECURITY FREEZE LOCK X F5 5 133 34 SECURITY DISABLE PASSWORD X F6 5 135 35 READ NATIVE MAX ADDR...

Page 17: ...nd Protocol 5 175 5 4 1 Non data command protocol 5 176 5 4 2 PIO data in command protocol 5 178 5 4 3 PIO data out command protocol 5 180 5 4 4 DMA data in command protocol 5 182 5 4 5 DMA data out command protocol 5 183 5 4 6 Native Command Queuing protocol 5 184 5 5 Power on and COMRESET 5 187 CHAPTER 6 Operations 6 1 6 1 Reset and Diagnosis 6 2 6 1 1 Response to power on 6 2 6 1 2 Response to ...

Page 18: ...aintenance levels 7 5 7 1 4 Disk drive revision number 7 6 7 1 5 Tools and test equipment 7 8 7 1 6 Self diagnostics 7 8 7 1 7 Test 7 8 7 2 Operation Confirmation 7 11 7 2 1 Operation test 7 11 7 2 2 Diagnostic test 7 11 7 3 Troubleshooting Procedure 7 12 7 3 1 Troubleshooting procedure 7 12 7 3 2 Troubleshooting disk drive replaced in field 7 12 7 3 3 Troubleshooting at factory 7 14 7 4 Disk Driv...

Page 19: ...ure 4 2 Circuit configuration 4 5 Figure 4 3 Power on operation sequence 4 7 Figure 4 4 Read write circuit block diagram 4 10 Figure 4 5 Block diagram of servo control circuit 4 12 Figure 4 6 Physical sector servo configuration on disk surface 4 15 Figure 4 7 Servo frame format 4 16 Figure 5 1 Interface signals 5 2 Figure 5 2 Example of the circuit for driving Activity LED 5 9 Figure 5 3 Conceptua...

Page 20: ...ure 5 19 WRITE FP DMA QUEUED command protocol 5 186 Figure 5 20 Power on sequence 5 187 Figure 5 21 COMRESET sequence 5 188 Figure 6 1 Response to power on when the host is powered on earlier than the device 6 2 Figure 6 2 Response to power on when the device is powered on earlier than the host 6 3 Figure 6 3 Response to COMRESET 6 4 Figure 6 4 Response to a software reset 6 7 Figure 6 5 Data buff...

Page 21: ...ure of data 640K Bytes A0000h Bytes of microcode 5 45 Table 5 9 Features Field values subcommands and functions 5 55 Table 5 10 Format of device attribute value data 5 59 Table 5 11 Format of guarantee failure threshold value data 5 59 Table 5 12 Off line data collection status 5 62 Table 5 13 Self test execution status 5 62 Table 5 14 Off line data collection capability 5 63 Table 5 15 Failure pr...

Page 22: ...e 5 36 Relationship between combination of Identifier and Security level and operation of the lock function 5 126 Table 5 37 Contents of security password 5 128 Table 5 38 Contents of Security Erase Unit Password 5 131 Table 5 39 Data format of Read Log Ext log page 10h 5 150 Table 5 40 Tag field information 5 150 Table 5 41 Data format of Read Log Ext log page 11h 5 151 Table 5 42 Counter Identif...

Page 23: ...a Defects 1 10 Load Unload Function 1 11 Advanced Power Management APM 1 12 Interface Power Management IPM Overview and features are described in this chapter and specifications and power requirement are described The disk drive is 2 5 inch hard disk drives with built in disk controllers These disk drives use the SATA interface protocol which has a high speed interface data transfer rate C141 E293...

Page 24: ... High speed Transfer rate The disk drive the MJA2xxxBH Series has an internal data rate up to 116 2 MB s The disk drive supports an external data rate 3 0 Gbps 300 MB s Serial ATA Generation 2 or 1 5 Gbps 150 MB s Serial ATA Generation 1 by each model And the disk drive realizes a high performance by high speed transfer rate combined with Native Command Queuing NCQ 5 Average positioning time Use o...

Page 25: ...ata between the host and the disk media In combination with the read ahead cache system described in item 3 and the write cache described in item 6 the buffer contributes to efficient I O processing 3 Read ahead cache system After the execution of a disk read command the disk drive automatically reads the subsequent data block and writes it to the data buffer read ahead operation This cache system...

Page 26: ...e cache When the disk drive receives a write command the disk drive posts the command completion at completion of transferring data to the data buffer completion of writing to the disk media This feature reduces the access time at writing ...

Page 27: ... Gen2i Data Transfer Rate 3 To From Media To From Host 4 116 2 MB s Max 1 5 Gbps 150 MB s Gen1i 1 5 Gbps model 1 5 Gbps 150 MB s Gen1i 3 0 Gbps 300 MB s Gen2i 3 0 Gbps model Data Buffer Size 5 8 MB 8 388 608 bytes Physical Dimensions Height Width Depth 9 5 mm 100 0 mm 70 0 mm 6 Weight 101 g Max 96 g Max 1 Capacity under the LBA mode 2 One gigabyte GB one billion bytes and One megabyte MB one milli...

Page 28: ...t drive the product number must be the same as that of the drive being replaced Table 1 2 Examples of model names and product numbers Model Name Capacity 1 user area Mounting screw Order No MJA2500BH 500 GB M3 Depth 3 CA07083 B391 1 5 Gbps model CA07083 B341 3 0 Gbps model 2 MJA2400BH 400 GB M3 Depth 3 CA07083 B390 1 5 Gbps model CA07083 B340 3 0 Gbps model 2 MJA2320BH 320 GB M3 Depth 3 CA07083 B0...

Page 29: ... Maximum 100 mV peak to peak Frequency DC to 1 MHz 3 Slope of an input voltage at rise The following figure shows the restriction of the slope which is 5 V input voltage at rise The permissible range of 5 V slope is from 1V 20 μsec to 1V 20 msec under the voltage range is between 2 0V and 4 5V Figure 1 1 Permissible range of 5V rise slope C141 E293 1 7 ...

Page 30: ...bottom figure isn t to occur at 5 V when power is turned off and a thing with no ringing Permissible level 0 2 V Voltage V 5 0 100 200 300 400 500 600 700 800 Time ms 4 3 2 1 0 1 Figure 1 2 The example of negative voltage waveform at 5 V when power is turned off ...

Page 31: ...k 0 0015 W GB MJA2400BH e rank 0 0019 W GB MJA2320BH d rank 0 0024 W GB MJA2250BH d rank 0 0038 W GB MJA2160BH d rank 0 0050 W GB MJA2120BH d rank 0 0075 W GB MJA2080BH 1 Power requirements reflect typical values for 5 V power 2 Maximum current and power at starting spindle motor 3 IPM mode Slumber mode 4 Current and power level when the operation command that accompanies a transfer of 63 sectors ...

Page 32: ...vironmental specifications Table 1 4 Environmental specifications Item Specification Temperature Operating Non operating Thermal Gradient 5 C to 55 C ambient 5 C to 60 C disk enclosure surface 40 C to 65 C 20 C h or less Humidity Operating Non operating Maximum Wet Bulb 8 to 90 RH Non condensing 5 to 95 RH Non condensing 29 C Operating 40 C Non operating Altitude relative to sea level Operating No...

Page 33: ...ise from the cover top surface 1 6 Shock and Vibration Table 1 6 lists the shock and vibration specification Table 1 6 Shock and vibration specification Item Specification Vibration Swept sine 1 4 octave per minute Operating Non operating 5 to 500 Hz 9 8m s 2 0 peak 1G 0 peak without non recovered errors 5 to 500 Hz 49m s 2 0 peak 5G 0 peak no damage Shock half sine pulse Operating Non operating 3...

Page 34: ...ean time to repair MTTR is 30 minutes or less if repaired by a specialist maintenance staff member 3 Service life In situations where management and handling are correct the disk drive requires no overhaul for five years when the DE surface temperature is less than 48 C When the DE surface temperature exceeds 48 C the disk drives require no overhaul for five years or 20 000 hours of operation whic...

Page 35: ...ors are replaced with alternates when the disk drive is formatted prior to shipment from the factory low level format Thus the hosts see a defect free device Alternate sectors are automatically accessed by the disk drive The user need not be concerned with access to alternate sectors 1 10 Load Unload Function The Load Unload function is a mechanism that loads the head on the disk and unloads the h...

Page 36: ...ing whether bit 7 of the status register was set to 0 wait to complete STANDBY IMMEDIATE command 4 HDD power supply cutting 1 11 Advanced Power Management APM The disk drive automatically shifts to the power saving mode according to the setting of the APM mode under the idle condition The APM mode can be chosen with a Sector Count register of the SET FEATURES EF command The disk drive complies wit...

Page 37: ...HDD is waiting for commands has been exceeded Mode 0 Mode shifts from Active condition to Active Idle in 0 2 1 2 seconds and to Low Power Idle in 15 minutes Mode 1 Mode shifts from Active condition to Active Idle in 0 1 0 2 seconds and to Low Power Idle in 10 0 27 5 seconds Mode 2 Mode shifts from Active condition to Active Idle in 0 1 0 2 seconds and to Low Power Idle in 10 0 27 5 seconds After 1...

Page 38: ...automatically under the Idle condition 1 Partial mode PMREQ_P is sent when the disk drive requests the Partial mode 2 Slumber mode PMREQ_S is sent when the disk drive requests the Slumber mode I F power states 1 Active state The SATA interface is active and data can be sent and received 2 Partial state The SATA interface is in the Power Down state In this state the interface is switched to the Par...

Page 39: ...le 1 8 Interface power management IPM Mode I F power state Return time to active I F condition Active Active State Active Partial Partial State 5 to 10 μs maximum Power Down Slumber Slumber State 5 to 10 ms maximum Power Down C141 E293 1 17 ...

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Page 41: ...ice Configuration 2 1 Device Configuration 2 2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate C141 E293 2 1 ...

Page 42: ...L type The head unloads the disk out of while the disk is not rotating and loads on the disk when the disk starts 3 Spindle motor The disks are rotated by a direct drive Sensor less DC motor 4 Actuator The actuator uses a revolving voice coil motor VCM structure which consumes low power and generates very little heat The head assembly at the edge of the actuator arm is controlled and positioned by...

Page 43: ...te circuit uses a LSI chip for the read write preamplifier It improves data reliability by preventing errors caused by external noise 7 Controller circuit The controller circuit supports Serial ATA interface and it realized a high performance by integration into LSI 2 2 System Configuration 2 2 1 SATA interface Figure 2 2 shows the SATA interface system configuration The disk drive complies with A...

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Page 45: ...ion Conditions 3 1 Dimensions 3 2 Mounting 3 3 Connections with Host System This chapter gives the external dimensions installation conditions surface temperature conditions cable connections and switch settings of the hard disk drives ...

Page 46: ...nnectors are not included in these dimensions 2 Dimension from the center of the user tap to the base of the connector pins 3 Length of the connector pins 4 Dimension from the outer edge of the user tap to the center of the connector pins 5 Dimension from the outer edge of the user tap to the innermost edge of the connector pins Figure 3 1 Dimensions ...

Page 47: ...e MR head bias of the HDD disk enclosure DE is zero The mounting frame is connected to Signal Ground SG Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3 2 The tightening torque must be 0 49N m 5kgf cm When attaching the HDD to the system frame do not allow the system frame to touch parts cover and base other than parts to which the HDD is attach...

Page 48: ...ons are recommended values if it is not possible to satisfy them contact us Screw Screw Details of A 3 0 or less 3 0 or less Frame of system cabinet Frame of system cabinet B PCA A 2 2 5 2 5 2 5 2 5 DE Side surface mounting Bottom surface mounting Figure 3 2 Mounting frame structure ...

Page 49: ...breather hole mounted to the HDD do not allow this to close during mounting Locating of breather hole is shown as Figure 3 3 For breather hole of Figure 3 3 at least do not allow its around φ 3 to block Figure 3 3 Location of breather hole ...

Page 50: ...erature from exceeding 60 C Provide air circulation in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface cover temperatures of the DE Regardless of the ambient temperature this surface cover temperature must meet the standards listed in Table 3 1 Figure 3 4 shows the temperature measurement point Figure 3 4 Surface cove...

Page 51: ...t affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device disconnect the body ground 500 kΩ or greater Do not touch the printed circuit board but hold it by the edges 6 Handling cautions Please keep the following cautions and handle the ...

Page 52: ...ue of the screw strictly M3 0 49N m 5 kgf cm Recommended equipments Contents Model Maker Wrist strap JX 1200 3056 8 SUMITOMO 3M ESD ESD mat SKY 8A Color Seiden Mat Achilles Shock Low shock driver SS 6500 HIOS Place the shock absorbing mat on the operation table and place ESD mat on it Use the Wrist strap Do not hit HDD each other Do not stack when carrying Do not place HDD vertically to avoid fall...

Page 53: ...th Host System 3 3 1 Device connector The disk drive has the SATA interface connectors listed below for connecting external devices Figure 3 7 shows the locations of these connectors and terminals Figure 3 7 Connector locations PCA SATA interface and power connectors ...

Page 54: ...nector specifications for host system The connector of host system for mating with the disk drive must be compliant with Serial ATA Revision 2 6 specification For detail of requirements about SATA interface connector refer to the Serial ATA Revision 2 6 The connection reliability per number of insertion extractions varies with the condition of the connection with the host system Therefore we recom...

Page 55: ...the SATA interface connector of the disk drive and plugging the connector into a host receptacle When plugging together the disk drive SATA interface connector and the host receptacle or SATA interface cable connector do not apply more than 10 kgf of force in the connection direction once they are snugly and securely in position Connecting removing the cable without releasing the SATA interface La...

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Page 57: ...guration 4 4 Power on Sequence 4 5 Self calibration 4 6 Read write Circuit 4 7 Servo Control This chapter explains basic design concepts of the disk drive Also this chapter explains subassemblies of the disk drive each sequence servo control and electrical circuit blocks C141 E293 4 1 ...

Page 58: ...n outer diameter of 65 mm and an inner diameter of 20 mm Servo data is recorded on each cylinder total 228 Servo data written at factory is read out by the read head For servo data see Section 4 7 4 2 2 Spindle The spindle consists of a disk stack assembly and spindle motor The disk stack assembly is activated by the direct drive sensor less DC spindle motor which has a speed of 5 400 rpm 1 The sp...

Page 59: ... HDC The PreAMP consists of the write current switch circuit that flows the write current to the head coil and the voltage amplifier circuit that amplitudes the read output from the head The RDC is the read demodulation circuit using the MEEPRML Modified Extended Extended Partial Response Maximum Likelihood and contains the Viterbi detector programmable filter adaptable transversal filter times ba...

Page 60: ...e control and data transfer control Data buffer management Sector format control Defect management ECC control Error recovery and self diagnosis SVC 2 5V DC DC Converter 1 15V DC DC Converter SIP RDC MCU DRAM FROM Integration HDC 3V Generator Circuit PreAMP 5 0V 2 5V 3 0V 1 15V Figure 4 1 Power supply configuration ...

Page 61: ...n C141 E293 4 5 SIP MCU HDC RDC Buffer RAM FROM HDC MCU RDC Data Buffer DDR SDRAM Flash ROM SVC Resonator R W Pre Amp Thermistor VCM HEAD SP Motor Media DE PCA Serial ATA Interface Shock Sensor Figure 4 2 Circuit configuration ...

Page 62: ...is terminates successfully the disk drive starts the spindle motor c The disk drive executes self diagnosis data buffer read write test d After confirming that the spindle motor has reached rated speed the head assembly is loaded on the disk e The disk drive positions the heads onto the SA area and reads out the system information f The drive becomes ready The host can issue commands g The disk dr...

Page 63: ...e read test The spindle motor starts Self diagnosis 2 Data buffer write read test b Confirming spindle motor speed c Load the head assembly Drive ready state command waiting state g Execute self calibration f Initial on track and read out of system information e End SATA I F Initialization d Figure 4 3 Power on operation sequence ...

Page 64: ...ng by the cylinder the disk is divided into 13 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration The measured values are stored in the SA cylinder In the self calibration the compensating value is updated using the value in the SA cylinder 2 Compensating open loop gain Torque constant value o...

Page 65: ... latter is interrupted when the disk drive receives a Host command and it resumes after next transfer to Active Idle state The number of retries to write or seek data reaches the specified value The error rate of data reading writing or seeking becomes lower than the specified value 4 5 3 Command processing during self calibration This enables the host to execute the command without waiting for a ...

Page 66: ...nt in writing Each channel is connected to each data head and PreAMP switches channel by serial I O In the event of any abnormalities including a head short circuit or head open circuit the write unsafe signal is generated so that abnormal write does not occur 4 6 2 Write circuit The write data is transferred from the hard disk controller HDC to the RDC in LSI The write data is sent to the PreAMP ...

Page 67: ...el block The MPU optimizes the cut off frequency and boost up gain according to the transfer frequency of each zone 3 FIR circuit This circuit is 10 tap sampled analog transversal filter circuit that equalizes the head read signal to the Modified Extended Partial Response MEEPR waveform 4 A D converter circuit This circuit changes Sampled Read Data Pulse from the FIR circuit into Digital Read Data...

Page 68: ...ator motor is controlled according to the servo data that is written on the data side beforehand 4 7 1 Servo control circuit Figure 4 5 is the block diagram of the servo control circuit The following describes the functions of the blocks Head Spindle motor CSR VCM Position Sense VCM current CSR Current Sense Resister VCM Voice Coil Motor 1 MPU HDC RDC 2 Servo burst capture 3 DAC 4 SVC Power Amp 5 ...

Page 69: ... head position from the servo data on the data surface From the servo area on the data area surface via the data head the burst signals of EVEN1 ODD EVEN2 are output as shown in Figure 4 7 in subsequent to the servo mark gray code that indicates the cylinder position and index information The servo signals do A D convert by Fourier demodulator in the servo burst capture circuit At that time the AG...

Page 70: ...face servo format Figure 4 6 describes the physical layout of the servo frame The three areas indicated by 1 to 3 in Figure 4 6 are described below 1 Inner guard band This area is located inside the user area and the rotational speed of the VCM can be controlled on this cylinder area for head moving 2 Data area This area is used as the user data area and SA area 3 Outer guard band This area is loc...

Page 71: ... CYLn CYLn 1 n even number W R Recovery Servo Mark Gray Code W R Recovery Servo Mark Gray Code W R Recovery Servo Mark Gray Code EVEN1 ODD EVEN2 Post code PAD Diameter direction Servo frame 228 servo frames per revolution Figure 4 6 Physical sector servo configuration on disk surface ...

Page 72: ...rmat 1 Write read recovery This area is used to absorb the write read transient and to stabilize the AGC 2 Servo mark This area generates timing for demodulating the gray code and position demodulating the burst signal by detecting the servo mark 3 Gray code including sector address bits This area is used as cylinder address The data in this area is converted into the binary data by the gray code ...

Page 73: ...d is stopped at the reference cylinder from there Track following control starts 2 Seek operation Upon a data read write request from the host the MPU confirms the necessity of access to the disk If a read write instruction is issued the MPU seeks the desired track The MPU feeds the VCM current via the D A converter and power amplifier to move the head The MPU calculates the difference speed error...

Page 74: ...o V phase U phase to W phase and V phase to W phase after that repeating this order The above operations mean the generation of rotational magnetic field d During phase switching the spindle motor starts rotating in low speed and generates a back electromotive force The SVC detects this back electromotive force and reports to the MPU using a PHASE signal for speed detection e The MPU is waiting fo...

Page 75: ...CHAPTER 5 Interface 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Power on and COMRESET This chapter gives details about the interface and the interface commands and timings ...

Page 76: ...end Device analog front end GND Figure 5 1 Interface signals An explanation of each signal is provided below TX TX These signals are the outbound high speed differential signals that are connected to the serial ATA cable RX RX These signals are the inbound high speed differential signals that are connected to the serial ATA cable TxData Serially encoded 10b data attached to the high speed serial d...

Page 77: ...dicates the COMWAKE out of band signal is being detected COMRESET COMINIT Host Signal from the out of band detector that indicates the COMINIT out of band signal is being detected Device Signal from the out of band detector that indicates the COMRESET out of band signal is being detected 5VDC GND 5VDC 5 V power supply to the disk drive GND Ground for each signal and 5 V power supply ...

Page 78: ...band signaling During OOB signaling transmissions the differential and common mode levels of the signal lines shall comply with the same electrical specifications as for in band data transmission specified as follows COMRESET COMINIT 106 7 ns 320 ns COMWAKE 106 7 ns 106 7 ns ...

Page 79: ...a frame when the transmitter does not have the next payload data ready for transmission HOLD is also transmitted on the backchannel when a receiver is not ready to receive additional payload data HOLDA Hold acknowledge This primitive is sent by a transmitter as long the HOLD primitive is received by its companion receiver PMNAK Power management denial Sent in response to a PMREQ_S or PMREQ_P when ...

Page 80: ... frame Start of a frame Payload and CRC follow to EOF SYNC Synchronization Synchronizing primitive always idle WTRM Wait for frame termination After transmission of any of the EOF the transmitter will transmit WTRM while waiting for reception status from receiver X_RDY Transmission data ready Current node host or device has payload ready for transmission 5 1 3 Electrical specifications For the ele...

Page 81: ...pen P3 V33 N C Open P4 Gnd 1st mate P5 Gnd 2nd mate P6 Gnd 2nd mate P7 V5 5 V power pre charge 2nd mate P8 V5 5 V power P9 V5 5 V power P10 Gnd 2nd mate P11 Staggered Spin up Mode Activity LED Staggered Spin up mode detect for input Activity LED drive for output For the specification of P11 see Section 5 1 5 in next page When the host system does not use these functions the corresponding pin to be...

Page 82: ...does not spin up until after successful Phy initialization at power on Default setting b P11 Grounded 0 8 V or less Staggered Mode Disable The disk drive spins up at power on c P11 High level The P11 line in the host system is pulled up by resistor recommended value 1 to 5 1 kΩ to power supply in the host system Recommended voltage 2V 3 3V or less Staggered Mode Enable The drive does not spin up u...

Page 83: ...5 1 Physical Interface C141 E293 5 9 Table 5 2 Requirements for P11 as an output pin Asserted Deasserted VACT 0 7V 0 7V IACT 50uA Figure 5 2 Example of the circuit for driving Activity LED ...

Page 84: ...er supply at Hot Plugging is in the following figure It is necessary to choose pre charge resistor RL value which is in permissible range of 5V power supply specification at the host system Refer to the equivalent circuit when the optimized value of pre charge resistor RL It is recommended to choose the minimum value which is in permissible range of 5V power supply specification at the host system...

Page 85: ...ithin the host or device and between layers at the same level that link the host and device Figure 5 3 is a conceptual diagram of the communication layers Host Software control Buffer Memory DMA engine s Host located layers Physical Layer Link Layer Transport Layer Device located layers Physical Layer Link Layer Transport Layer Device Software control Buffer memory DMA engine s Application layer 4...

Page 86: ...nsfer requests between the host system and device Encodes serial data as 10 or 8 bit data then converts it into DWORD data Inserts auxiliary signals SOF CRC and EOF deletes auxiliary signals and communicates with the transport and physical layers Transport layer Exchanges data in communication with the link layer and builds the frame information structure FIS Contains a Shadow Block Register Refle...

Page 87: ...ector Count Sector Count exp Sector Count Sector Number exp Sector Number Sector Number exp Sector Number Cylinder Low exp Cylinder Low Cylinder Low exp Cylinder Low Cylinder High exp Cylinder High Cylinder High exp Cylinder High Device Head Status Command Control Block registers Alternate Status Device Control Note Each of the Sector Count Sector Number Cylinder Low and Cylinder High fields has a...

Page 88: ... 5 2 3 1 FIS types The types of FIS are as follows Each FIS is referred to as abbreviation in square brackets in this manual Register Host to Device RegHD Register Device to Host RegDH DMA Active Device to Host DMA Active DMA Setup Device to Host or Host to Device Bidirectional DMA Setup Set Device Bits Device to Host SetDB BIST Active Bidirectional BIST Active PIO Setup Device to Host PIO Setup D...

Page 89: ...w exp 2 Control Reserved 0 Sector Count exp Sector Count 3 Reserved 0 Reserved 0 Reserved 0 Reserved 0 4 Figure 5 4 Register Host to Device FIS layout The host system uses the Register Host to Device FIS when information in the Register Block is transferred from the host system to the device This is the mechanism for issuing the ATA command from the host system to the device C To update the Comman...

Page 90: ...ning the Shadow Register Block in the host adapter is updated This FIS indicates that the device has completed a command operation Furthermore this is a mechanism for changing information concerning the Shadow Register Block of the host adapter I If this bit is set an interrupt request is issued to the host system 5 2 3 4 DMA Active Device to Host The DMA Active Device to Host FIS has the followin...

Page 91: ... Reserved 0 6 Figure 5 7 DMA Setup Device to Host or Host to Device FIS layout The DMA Setup Device to Host or Host to Device FIS communicates the start of a first party DMA access to the host system This FIS is used to request the host system or device to set up the DMA controller before the start of a DMA data transfer A Auto Active bit If this bit is cleared 0 is set for the bit it indicates th...

Page 92: ...ack mode This FIS can be sent by either the host system or device The following combinations of pattern definitions are supported Table 5 4 BIST combinations T A S L F P V SC Reg Contents 1 1 09h SATA Phy Analog Loopback Mode 1 10h Far End Retimed Loopback Mode 1 1 C0h No ALIGN Transmit_only Mode Scramble ON 1 1 1 1 E0h No ALIGN Transmit_only Mode Scramble OFF 1 1 1 C4h No ALIGN Transmit_only with...

Page 93: ...Reserved 0 FIS Type 5Fh 0 Dev Head Cyl High Cyl Low Sector Number 1 Reserved 0 Cyl High exp Cyl Low exp Sector Num exp 0 2 E_Status Reserved 0 Sector Count exp Sector Count 3 Reserved 0 Transfer Count 4 Figure 5 10 PIO Setup Device to Host FIS layout The PIO Setup FIS is a device to host FIS FIS Type 5Fh The PIO Setup FIS is used by the device to provide the host adapter with the data transfer cou...

Page 94: ...adow Register Block E_Status Contains the new value of the status register of the task file block for correct synchronization of data transfers to host Error Contains the new value of the Error register of the Command Block at the conclusion of all subsequent Data to Device frames I Interrupt bit This bit reflects the interrupt bit line of the device R Reserved 0 Sector Count Holds the contents of...

Page 95: ...pending state if both the BSY bit and the DRQ bit in the shadow Status register are zero when the frame is received Error Contains the new value of the Error register of the Shadow Register Block Status Hi Contains the new value of bits 6 5 and 4 of the Status register of the Shadow Register Block Status Lo Contains the new value of bits 2 1 and 0 of the Status register of the Shadow Register Bloc...

Page 96: ... found Or SATA Frame Error Write SFRW This bit indicates that a SATA communication error has been encountered during the write process In this case bit4 and bit2 are set both Bit 3 SATA Frame Error Read SF RR This bit indicates that a SATA communication error has been encountered during the read process In this case bit3 and bit2 are set both Bit 2 Aborted Command ABRT This bit indicates that the ...

Page 97: ...g sectors that the data has not been transferred due to the error However as of the last sector of PIO transfer SC 1 indicates the normal completion The contents of this field also have other definitions Refer to 5 4 4 Sector Number Field exp The contents of this field indicate the starting sector number for the subsequent command The sector number should be between X 01 and the number of sectors ...

Page 98: ...The contents of this field indicate the device and the head number When executing INITIALIZE DEVICE PARAMETERS command the contents of this field defines the number of heads minus 1 a maximum head No Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X L X X HS3 HS2 HS1 HS0 Bit 7 Unused Bit 6 L 0 for CHS mode and 1 for LBA mode Bit 5 Unused Bit 4 Unused Bit 3 HS3 CHS mode head address 3 2 3 bit 27 fo...

Page 99: ...set Bit 6 Device Ready DRDY bit This bit indicates that the device is capable to respond to a command The IDD checks its status when it receives a command If an error is detected not ready state the IDD clears this bit to 0 This is cleared to 0 at power on and it is cleared until the rotational speed of the spindle motor reaches the steady speed Bit 5 Device Write Fault DF bit This bit indicates t...

Page 100: ...evice is not required to execute the DASP handshake 11 E_Status Field This field is in the PIO Setup FIS The field contents are the same as those described in 8 Status Field However the values in the Status field are those before a PIO data transfer and the values in the E_Status field are those when a PIO data transfer is completed 12 DMA Buffer Offset Field This field is in the DMA Setup FIS rep...

Page 101: ... code and parameters Table 5 5 lists the supported commands command code and the related fields to be written necessary parameters at command execution Table 5 5 Command code and parameters 1 3 COMMAND CODE Bit PARAMETER USED COMMAND NAME 7 6 5 4 3 2 1 0 FR SC SN CY DH RECALIBRATE 0 0 0 1 X X X X N N N N D READ SECTOR S 0 0 1 0 0 0 0 R N Y Y Y Y WRITE SECTOR S 0 0 1 1 0 0 0 R N Y Y Y Y WRITE VERIF...

Page 102: ...FER 1 1 1 0 0 1 0 0 N N N N D FLUSH CACHE 1 1 1 0 0 1 1 1 N N N N D WRITE BUFFER 1 1 1 0 1 0 0 0 N N N N D IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D IDENTIFY DEVICE DMA 1 1 1 0 1 1 1 0 N N N N D SET FEATURES 1 1 1 0 1 1 1 1 Y N N N D SECURITY SET PASSWORD 1 1 1 1 0 0 0 1 N N N N D SECURITY UNLOCK 1 1 1 1 0 0 1 0 N N N N D SECURITY ERASE PREPARE 1 1 1 1 0 0 1 1 N N N N D SECURITY ERASE UNIT 1 1 1 1...

Page 103: ...CORRECTABLE EXT 0 1 0 0 0 1 0 1 N Y Y Y D READ LOG DMA EXT 0 1 0 0 0 1 1 1 N Y Y Y D WRITE LOG DMA EXT 0 1 0 1 0 1 1 1 N Y Y Y D READ FP DMA QUEUED 0 1 1 0 0 0 0 0 Y Y Y Y D WRITE FP DMA QUEUED 0 1 1 0 0 0 0 1 Y Y Y Y D WRITE MULTIPLE FUA EXT 1 1 0 0 1 1 1 0 N Y Y Y D FLUSH CACHE EXT 1 1 1 0 1 0 1 0 N N N N D CY cylinder field DH device head field FR features field SC sector count field SN sector ...

Page 104: ...ress LSB LBA 15 8 SN EXP LBA 31 24 SN EXP LBA 31 24 SN Start sector No LBA 7 0 SN End sector No LBA 7 0 SC EXP Transfer sector count 15 8 SC EXP X 00 SC Transfer sector count 7 0 SC X 00 FR EXP xx FR xx ER Error information CH EXP Cylinder High Field EXP CL EXP Cylinder Low Field EXP CM Command Field DH Device Head Field ER Error Field FR EXP Features Field EXP L LBA Logical Block Address setting ...

Page 105: ...r reporting conditions 1 An error was detected during head positioning ST 51h ER 02h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 0 0 0 1 x x x x DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error inform...

Page 106: ...block registers contain the cylinder head and sector addresses in the CHS mode or logical block address in the LBA mode of the last sector read If an unrecoverable disk read error occurs in a sector the read operation is terminated at the sector where the error occurred Shadow block registers contain the cylinder the head and the sector addresses of the sector in the CHS mode or the logical block ...

Page 107: ...LSB LBA Start sector No LBA LSB Transfer sector count xx R Retry At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 01 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred ...

Page 108: ...d sector addresses of the last sector written If a disk error occurs during multiple sector write operation the write operation is terminated at the sector where the error occurred Shadow block registers contain the cylinder the head the sector addresses in the CHS mode or the logical block address in the LBA mode of the sector where the error occurred Error reporting conditions 1 A specified addr...

Page 109: ...tart sector No LBA LSB Transfer sector count xx R Retry At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command was terminated because of an error the number of sectors for which data has not been written is set in this fiel...

Page 110: ...tion after a transfer of dummy data ST 51h ER 10h 3 A write fault was detected when the write cache was disabled ST 71h ER 10h 4 While the write cache is enabled if the status indicating a completed transfer STS 50h is returned and a data write operation failed because a write fault was detected during the data write operation Abort will be returned for all subsequent ATA commands ST 71h ER 04h Th...

Page 111: ...atus information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command is terminated because of an error the number of remaining sectors for which data has not been written or verified is set in this register ...

Page 112: ...k address in the LBA mode of the sector where the error occurred The Sector Count field indicates the number of sectors that have not been verified Error reporting conditions 1 A specified address exceeds the range where read operations are allowed ST 51h ER 10h 2 The range where read operations are allowed will be exceeded by an address during a read operation ST 51h ER 10h 3 An uncorrectable dis...

Page 113: ...ead ST Status information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register ...

Page 114: ...ress exceeds the range where the head can be positioned ST 51h ER 10h 2 Head positioning is not possible because an error occurred ST 51h ER 10h 3 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 0 1 1 1 x x x x DH x L x x HD No LBA CH CL SN SC FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB xx xx At com...

Page 115: ...pleted No error detected HDC diagnostic error Data buffer diagnostic error Memory diagnostic error Reading the system area is abnormal Calibration abnormal Note The device responds to this command with the result of power on diagnostic test Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 0 0 1 0 0 0 0 D...

Page 116: ...d are retained even after soft reset and COMRESET issuance or power save operation regardless of the setting of disabling the reverting to default setting The operation is always performed in CHS mode with the command ignoring any setting of LBA mode Error reporting conditions 1 00h is specified in the SC field ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance S...

Page 117: ... ER Error information This command rewrites the microcode of the device firmware When this command is accepted the device does beginning the data transfer of the microcode or the microcode rewriting according to Subcommand code Rewriting is also possible simultaneously with the data transfer Refer to Table 5 7 In the data transfer of Subcommand code 01h and 03h transfer by which data is divided in...

Page 118: ...g 01h 03h and 07h Abort 1 When FR Field 03 Mode3 is specified Abort is returned as an error when the specification of doing Sector Offset CH CL Field is the transfer end the last sector and is not consecutive Moreover Sector Offset CH CL Field is invalid in specification other than FR Field 03 Mode3 2 In the following cases Subcommand code 07h returns Abort as an error though becomes Microcode rew...

Page 119: ... 0100h FR 0lh 4 CMD 92h SN SC 0100h FR 0lh 5 CMD 92h SN SC 0100h FR 07h Transfer of 128 KB 0 to 127 KB from the beginning Transfer from 128 to 255 KB Transfer from 256 to 383 KB Transfer from 384 to 511 KB Transfer from 512 to 639 KB and Firmware rewriting execution The Aborted Command error is reported if any of the following conditions is satisfied transferred microcode data is incorrect firmwar...

Page 120: ...and does not support the APS timer function Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 94 or X E0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 121: ...he host system This command does not support the APS timer function Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 95 or X E1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error...

Page 122: ... the normal not emergency load unload guarantee count per the device life Even if the device executes reading look ahead operation or executes writing operation the device unloads the head s to the ramp position as soon as possible when received the IDLE IMMEDIATE command with the Unload Feature When the writing operation is stopped the device keeps the unwritten data And the device keeps the unlo...

Page 123: ...not received within the period specified as the APS timer value the device automatically enters Standby mode If the Sector Count field value is 0 the APS timer is disabled when the command is received Under the standby mode the spindle motor is stopped Thus when the command involving a seek such as READ SECTOR s command is received the device processes the command after driving the spindle motor E...

Page 124: ...enters standby mode The APS timer is set to prohibition if the Sector Count field s value was 0 when device has received this command The period of timer count is set depending on the value of the Sector Count register as shown below Sector Count field value Point of timer 0 X 00 Timeout disabled 1 to 240 X 01 to X F0 Value 5 seconds 241 to 251 X F1 to X FB Value 240 30 min 252 X FC 21 minutes 253...

Page 125: ...5 3 Host Commands C141 E293 5 51 At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 126: ...evice reports the status to the host system Power save mode Sector Count field During moving to Standby mode Standby mode X 00 Idle mode X FF Active mode X FF Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 98 or X E5 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registe...

Page 127: ...red the sleep mode In the sleep mode the spindle motor is stopped The only way to release the device from sleep mode is to execute a software or COMRESET Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 99 or X E6 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers co...

Page 128: ...Fh in the Cylinder Low field and C2h in the Cylinder High field If the key values are incorrect the Aborted Command error is issued If the failure prediction function is disabled the device returns the Aborted Command error to subcommands other than those of the SMART Enable Operations with the Features field set to D8h If the failure prediction function is enabled the device collects and updates ...

Page 129: ... time that attributes were saved then the attributes are saved However if the automatic attribute save function is disabled the attributes are not saved Upon receiving this subcommand a device enables or disables the automatic attribute save function and transfers the RegDH then reports the status In this drive this function is enabled at the shipment from the factory X D3 SMART SAVE ATTRIBUTE VAL...

Page 130: ... log data format See Table 5 21 concerning the SMART selective self test log data format See Table 5 24 concerning the SCT Status Request data format X D6 SMART WRITE LOG A device which receives this sub command when it has prepared to receive data from the host computer it transfers the PIOSU Next it receives data from the host computer and writes the specified log sector in the Sector Number Fie...

Page 131: ...tion 00h or disabled when the Sector Count field specification 00 state This setting is preserved whether the drive s power is switched on or off If 24 hours have passed since the power was switched on or since the last time that off line data were collected off line data collection is performed without relation to any command from the host computer The host must regularly issue the SMART READ DAT...

Page 132: ...ediction status C2h 2Ch Key failure prediction status 4Fh F4h xx xx Error information The attribute value information is 512 byte data the format of this data is shown the following Table 5 10 The host can access this data using the SMART READ DATA subcommand Features field D0h The guarantee failure threshold value data is 512 byte data the format of this data is shown the following Table 5 11 The...

Page 133: ...uble prediction capability flag 172 Error logging capability 173 Self test error detection point 174 Simple self test Quick Test execution time min 175 Comprehensive self test Comprehensive Test execution time min If Byte 175 FFh use bytes 177h and 178h 176 Conveyance self test execution time min 177 178 Comprehensive self test Comprehensive Test execution time min 179 to 181 Reserved 182 to 1FE V...

Page 134: ...e name 0 Indicates unused attribute data 1 Read Error Rate 2 Throughput Performance 3 Spin Up Time 4 Start Stop Count 5 Reallocated Sector Count 7 Seek Error Rate 8 Seek Time Performance 9 Power On Hours Count 10 Spin Retry Count 12 Drive Power Cycle Count 192 Emergency Retract Cycle Count 193 Load Unload Cycle Count 194 HDA Temperature 195 ECC On the Fly Count 196 Reallocated Event Count 197 Curr...

Page 135: ... saved even if SMART is disabled 6 to 15 Reserve bit Current attribute value It indicates the normalized value of the original attribute value The value deviates in a range of 01h to 64h range of 01h to C8h for the Ultra ATA CRC error rate and communication error rate It indicates that the closer the value is to 01h the higher the possibility of a failure The host compares the attribute value with...

Page 136: ...cution status Table 5 13 Self test execution status Bit Meaning 0 to 3 Remainder of the self test is indicated as a percentage in a range of 0h to 9h corresponding to 0 to 90 4 to 7 Self test execution status 0h Self test has ended successfully or self test has not been executed 1h Self test is suspended by the host 2h Self test is interrupted by a soft reset COMRESET from the host 3h Self test ca...

Page 137: ...hen a new command is received 3 If this bit is 1 it indicates that the SMART Off line Read Scanning Technology is supported 4 If this bit is 1 it indicates that the SMART Self test function is supported 5 If this bit is 1 it indicates that the SMART Conveyance Self test is supported 6 If this bit is 1 it indicates that the SMART Selective Self test is supported 7 Reserved bits Failure prediction c...

Page 138: ...limit of a varying attribute value The host compares the attribute values with the thresholds to identify a failure Table 5 17 Log Directory Data Format Byte hex Item 00 01 SMART Logging Version 02 Number of sectors of Address 01h 03 Reserved 04 Number of sectors of Address 02h 05 to 0B Reserved 0C Number of sectors of Address 06h 0D to 11 Reserved 12 Number of sectors of Address 09h 13 to FF Rese...

Page 139: ...atures field D5h Sector Number field 02h Sector Count field 33h and can read the SMART Comprehensive Error Log Table 5 18 Data format of SMART Summary Error Log 1 2 Byte hex Item 00 Version of this function 01 Pointer for the latest Error Log Data Structure 02 to 0D Forth last command data structure 0E to 19 Third last command data structure 1A to 25 Second last command data structure 26 to 31 Las...

Page 140: ... 5B Error data structure Power on time unit h 5C to 1C3 Error log data structure 2 to Error log data structure 5 1C4 1C5 Total number of drive errors 1C6 to 1FE Reserved 1FF Check sum Command data structure Indicates the command received when an error occurs Error data structure Indicates the status register when an error occurs Total number of drive errors Indicates total number of errors registe...

Page 141: ...ata Structure 5n 2 B6 to 10F 3 rd Error Log Data Structure3 Error Log Data Structure 5n 3 110 to 169 4 th Error Log Data Structure4 Error Log Data Structure 5n 4 16A to 1C3 5 th Error Log Data Structure5 Error Log Data Structure 5n 5 1C4 to 1C5 Total number of drive errors Reserved 1C6 to 1FE Reserved Reserved 1FF Check sum Check sum n indicates sector number in the Error Log The first sector is 0...

Page 142: ...unique 1A to 1F9 Self test log 2 to 21 Each log data format is the same as that in byte 02 to 19 1FA 1FB Vendor unique 1FC Self test index 1FD 1FE Reserved 1FF Check sum Self test number Indicates the type of self test executed Self test execution status Same as byte 16Bh of the attribute value Self test index If this is 00h it indicates the status where the self test has never been executed Check...

Page 143: ...o 151 Reserved 152 to 1EB Vender Unique 1EC to 1F3 Current LBA under test 1F4 to 1F5 Current Span under test 1F6 to 1F7 Feature Flags 1F8 Offline Execution Flag 1F9 Selective Offline Scan Number 1FA 1FB Vender Unique Reserved 1FC 1FD Selective Self test pending time min 1FE 1FF Checksum Test Span Selective self test log provides for the definition of up to five test spans If the starting and endin...

Page 144: ...ne scan after selective test is active 5 to 15 Reserved Bit l shall be written by the host and returned unmodified by the device Bit 3 4 shall be written as zeros by the host and the device shall modify them as the test progress Selective Self test pending time min The selective self test pending time is the time in minutes from power on to the resumption of the off line testing if the pending bit...

Page 145: ... specific operation for which the action code For information about the format of the Key Sector Format see Table 5 27 to Table 5 30 X E1 X D5 SCT READ DATA A device that received this subcommand transfers the data table of the number of sectors specified with Sector Count field to the host It is necessary to issue the SCT COMMAND SET immediately before when this command is issued X E1 X D6 SCT WR...

Page 146: ...T shown in Table 5 24 of the device At command issuance Shadow Block Registers setting CM 1 0 1 1 0 0 0 0 DH x x x DV xx CH CL SN SC FR Key C2h Key 4Fh E0h 01h D5h At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH CL SN SC ER xx xx xx xx Error information ...

Page 147: ...ve is changed via SET MAX EXT DCO 1 A WRITE SAME command to all logical blocks has completed without error 0A Drive State 00h Active 01h not support Standby 02h not support Sleep 03h DST executing in background 04h SMART Off line Data collection executing in background 05h SCT command executing in background 06h FFh Reserved 0B to 0D Reserved 0E 0F Extended Status Code Status of last SCT command i...

Page 148: ...urrent drive HDA temperature C9 Minimum HDA temperature in this power cycle CA Max Temp C Maximum HDA temperature in this power cycle CB Minimum HDA temperature for the life of the device CC Life Max Temp C Maximum HDA temperature for the life of the device CD Reserved CE to D1 Over Limit Count HDA temperature D2 to D5 Under Limit Count HDA temperature D6 to 1DF Reserved 1E0 to 1FF Vender specific...

Page 149: ...nd 0009 Background SCT command was terminated because of unrecoverable error 000A Invalid function code in LONG SECTOR ACCESS command 000B SCT data transfer command was issued without first issuing an SCT command 000C Invalid function code in Feature Control command 000D Invalid Feature Code in Feature Control command 000E Invalid New State in Feature Control command 000F Invalid Option Flag in Fe...

Page 150: ...e device and executes each function to show in Table 5 27 to Table 5 30 28 bit command At command issuance Shadow Block Registers setting CM 1 0 1 1 0 0 0 0 DH x x x DV xx CH CL SN SC FR Key C2h Key 4Fh E0h 01h D6h At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH CL SN SC ER xx xx xx xx Error information ...

Page 151: ...d 0006 to BFFF Reserved C000 to FFFF Vender specific Table 5 27 WRITE SAME 1 2 Byte hex Name Value Description 00 01 Action Code 0002h WRITE SAME 0001h Repeat Write Pattern It initializes it by data pattern of 32bit specified with byte 014h 017h 0002h Repeat Write data block It initializes it by data pattern of 1sct transfer by the SCT Write data 0101h Repeat Write Pattern Foreground 02 03 Functio...

Page 152: ...L Byte hex Name Value Description 00 01 Action Code 0003h ERROR RECOVERY CONTROL 0001h Set New Value The retry processing when making an error in the specified timer 02 03 Function Code 0002h Return Current Value The timer value of the error recovery being set now is displayed in SN SC field 0001h Read Timer 04 05 Selection Code 0002h Write Timer 06 07 Value 2 byte Set to Timer Value x 100 ms Mini...

Page 153: ... Code 0001h Set Write Cache 0001h Allow write cache operation to be determined by ATA Set Feature command 0002h Force Write Cache enabled 0003h Force Write Cache disable Feature Code 0002h Set Write Reordering 0001h Enable Write Reordering 0002h Disable Write Reordering 06 07 New State 2 byte Feature Code 0003h Set time interval 0000h Invalid 0001h FFFFh Logging interval in minutes ex 0001h Temper...

Page 154: ... Description 00 01 Action Code 0005h SCT DATA TABLE 02 03 Function Code 0001h Read Data Table 0000h Invalid 0001h Reserved 0002h HDA Temperature History Table See Table 5 31 0003h to CFFFh Reserved 04 05 Table ID D000h to FFFFh Vender specific 06 to 1FF Reserved Reserved ...

Page 155: ...ime of temperature log of interval min 00 Max Operation Limit C 07 Over Limit C 08 Min Operation Limit C 09 Under Limit C 0A to 1D Reserved 1E 1F Number of logs that can be recorded in temperature log 20 21 Index of temperature log 22 to 1FF Temperature log 478 data Entry 80h temperature log at Power cycle and default value is 80h 022h Temp Log No 0 023h Temp Log No 1 to 1FFh Temp Log No 478 ...

Page 156: ...egisters setting CM 1 0 1 1 0 0 0 0 DH x x x DV xx CH CL SN SC FR Key C2h Key 4Fh E1h xx D5h At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH CL SN SC ER xx xx xx xx Error information SCT READ DATA Command issue procedure 1 Issue the SCT set command of action code 0005h 2 Issue the SCT READ DATA command and receive the HDA temperature data fr...

Page 157: ...ance Shadow Block Registers setting CM 1 0 1 1 1 1 1 1 DH x x x DV xx CH CL SN SC FR Key C2h Key 4Fh E1h xx D6h At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH CL SN SC ER xx xx xx xx Error information SCT WRITE DATA Command issue procedure 1 Issue the SCT set command of action code 0002h and function code 0002h 2 Issue the SCT write command...

Page 158: ...n aborted command error is posted FR field Command C0h DEVICE CONFIGURATION RESTORE C1h DEVICE CONFIGURATION FREEZE C2h DEVICE CONFIGURATION IDENTIFY C3h DEVICE CONFIGURATION SET 00h to BFh C4h to FFh Reserved At command issuance Shadow Block Registers setting contents CM 1 0 1 1 0 0 0 1 DH x x x x xx CH CL SN SC xx xx xx xx FR C0h C1h C2h C3h At command completion Shadow Block Registers contents ...

Page 159: ...sued ST 51h ER 04h 3 The SET MAX ADDRESS EXT command F9h 37h has been specified with a value in the Host Protected Area ST 51h ER 04h 4 A SATA communication error occurred ST 51h ER 14h DEVICE CONFIGURATION FREEZE LOCK Features Field C1h The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the Device Configuration Overlay settings After successful execution of a DEVICE ...

Page 160: ... reflected in IDENTIFY information When the bits in these words are cleared the device no longer supports the indicated command mode or feature set If a bit is set in the overlay transmitted by the device that is not set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit After execution of this command the settings are kept regardless of the power ...

Page 161: ...low are supported Bit 1 1 Ultra DMA mode 1 and below are supported Bit 0 1 Ultra DMA mode 0 is supported 3 to 6 Maximum LBA address Reflected in IDENTIFY information WORD60 61 WORD100 103 7 X 79CF Command set feature set supported Reflected in IDENTIFY information WORD82 87 Bit 15 Reserved Bit 14 1 Write Read Verify feature set supported Bit 13 1 SMART Conveyance self test supported Bit 12 1 SMART...

Page 162: ...tup FIS supported Bit 0 1 Native command queuing supported 9 X 0000 Reserved for Serial ATA 10 to 20 X 0000 Reserved 21 X 2000 X 2800 1 Bits 15 14 Reserved Bit 13 Write uncorrectable is supported Bit 12 Reserved Bit 11 Freefall Control feature set is supported 1 Bit 10 0 Reserved 22 to 254 X 0000 Reserved 255 X xxA5 Bits 15 8 Check sum code This is obtained by calculating the sum of all upper byte...

Page 163: ... of sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the READ MULTIPLE command is issued when the READ MULTIPLE command is disabled the device rejects the READ MULTIPLE command with an ABORTED COMMAND error If an uncorrectable disk read error occurs the read operation stops at the sector where the error occurred even if the read operation ha...

Page 164: ...here read operations are allowed ST 51h ER 10h 2 The range where read operations are allowed will be exceeded by an address during a read operation ST 51h ER 10h 3 An uncorrectable disk read error occurred ST 51h ER 40h 4 The sync byte indicating the beginning of a sector was not found ST 51h ER 01h 5 The READ MULTIPLE command is disabled ST 51h ER 04h 6 A SATA communication error occurred ST 51h ...

Page 165: ...ount xx At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 1 Error information 1 If the command is completed normally the number of remaining sectors is set in this field If the command is terminated because of an error the number of sectors for which data ha...

Page 166: ...ter a disk write operation has been attempted for the transferred blocks and partial block The write operation stops at the sector where the error occurred even if the write operation has not reached the end of the block At this time the number of remaining sectors the error sector and subsequent sectors and either cylinder head and sector addresses of the error sector CHS mode or the logical bloc...

Page 167: ...t sector No LBA LSB Transfer sector count xx R Retry At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command was terminated because of an error the number of sectors for which data has not been written is set in this f...

Page 168: ...en enabled If the value of the Sector Count register is not a supported block count an ABORTED COMMAND error is posted and the READ MULTIPLE and WRITE MULTIPLE commands are disabled If the contents of the Sector Count field are 0 when the SET MULTIPLE MODE command is issued the READ MULTIPLE and WRITE MULTIPLE commands are disabled When the SET MULTIPLE MODE command operation is completed the devi...

Page 169: ...5 3 Host Commands C141 E293 5 95 At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx Sector count block Error information ...

Page 170: ... detected is transferred The device notifies the host of the status by sending the RegDH FIS At this time the number of remaining sectors including the sector where the error was detected and either cylinder head and sector addresses CHS mode or the logical block address LBA mode of the sector where the error was detected are stored in the Shadow Block Register The host system can select the DMA t...

Page 171: ...rt sector No LBA LSB Transfer sector count xx At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this regis...

Page 172: ...ere the error was detected and either cylinder head and sector addresses CHS mode or the logical block address LBA mode of the sector where the error was detected are stored in the Shadow Block Register A host system can select the following transfer mode using the SET FEATURES command however the transfer speed does not change Multiword DMA transfer mode 0 to 2 Ultra DMA transfer mode 0 to 5 Erro...

Page 173: ...Start sector No LBA LSB Transfer sector count xx At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command was terminated because of an error the number of sectors for which data has not been written is set in this field...

Page 174: ...r that the host system can read up to 512 bytes of data from the buffer Error reporting conditions 1 A SATA communication error occurred ST 51h ER 0Ch At command issuance Shadow Block Registers setting contents CM 1 1 1 0 0 1 0 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx x...

Page 175: ... are to be written In case a non recoverable disk write error has occurred while the data is being read the error generation address is put into the shadow block register before ending the command This error sector is deleted from the write cache data Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 ...

Page 176: ...tes of data are transferred from the host and the device writes the data to the buffer then reports the status Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 0 0 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information ...

Page 177: ...he host then sends the parameter information including a 512 byte data Table 5 33 shows the values of the parameter words and the meaning in the buffer Error reporting conditions 1 A SATA communication error occurred ST 51h ER 0Ch At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 1 0 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers c...

Page 178: ... Identify Device command Error reporting conditions 1 A SATA communication error occurred ST 51h ER 84h At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 1 1 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 179: ...00 22 X 0000 Reserved 23 26 Firmware revision ASCII code 8 characters left 27 46 Set by a device Model name ASCII code 40 characters left 47 X 8010 Maximum number of sectors per block on READ WRITE MULTIPLE command 48 X 0000 Reserved 49 X 2F00 Capabilities 4 50 X 4000 Capabilities 5 51 X 0200 PIO data transfer mode 6 52 X 0200 Reserved 53 X 0007 Enable disable setting of words 54 58 and 64 70 88 7...

Page 180: ... X 004C Support of Serial ATA function 13 79 X 00xx Valid of Serial ATA function 14 80 X 01F8 Major version number ATA8 ACS 15 81 X 0042 Minor version number ATA8 ACS Revision 3f 82 16 Support of command sets 16 83 17 Support of command sets 17 84 18 Support of command sets function 18 85 19 Valid of command sets function 19 86 20 Valid of command sets function 20 87 21 Default of command sets fun...

Page 181: ...000 Reserved 128 X 0xxx Security status 29 129 159 X xxxx Undefined 160 205 X 0000 Reserved 206 X 003D SCT Command sets supported 30 207 209 X 0000 Reserved 210 211 X xxxx Write Read Verify Sector Count Mode 3 Only 31 212 213 X xxxx Write Read Verify Sector Count Mode 2 Only 32 214 219 X 0000 Reserved 220 X 00xx Write Read Verify Mode 33 221 X 0000 Reserved 222 X 100F Transport major version numbe...

Page 182: ... Word MJA2160BH MJA2120BH MJA2080BH 1 X 3FFF X 3FFF X 3FFF 3 X 10 X 10 X 10 6 X 3F X 3F X 3F 60 61 X FFFFFFF X DF94BB0 X 950F8B0 100 103 X 12A19EB0 X DF94BB0 X 950F8B0 3 Status of the Word 2 Identify information is shown as follows 37C8h The device requires the SET FEATURES sub command after the power on sequence in order to spin up The Identify information is incomplete 8C73h The device requires ...

Page 183: ...of the device is the smallest value 6 Word 51 PIO data transfer mode Bits 15 8 PIO data transfer mode X 02 PIO mode 2 supported Bits 7 0 Undefined 7 Word 53 Enable disable setting of word 54 58 and 64 70 Bits 15 3 Reserved Bit 2 1 Enable the word 88 Bit 1 1 Enable the word 64 70 Bit 0 1 Enable the word 54 58 8 Word 59 Transfer sector count currently set by READ WRITE MULTIPLE command Bits 15 9 Res...

Page 184: ... Mode 0 10 Word 64 Advance PIO transfer mode support status Bits 15 8 Reserved Bits 7 0 Advance PIO transfer mode Bit 1 1 Mode 4 supported Bit 0 1 Mode 3 supported 11 WORD 75 X 001F 0 to 31 32 12 WORD 76 Bits 15 11 Reserved Bit 10 1 Supports the PHY event counter Bit 9 1 Supports the Power Management initiation request from the host system Bit 8 1 Supports the Native command queueing Bits 7 4 Rese...

Page 185: ...WORD 79 Bits 15 7 Reserved Bit 6 1 Enables the software settings preservation Bit 5 Reserved Bit 4 1 Enables the in order data delivery Bit 3 1 Enables the Power Management initiation function from Bit2 1 Enables the Auto Activate optimization function in the DMA Setup FIS Bit 1 1 Enables the non zero buffer offset function in the DMA Setup FIS Bit 0 Reserved 15 WORD 80 Bits 15 9 Reserved Bit 8 1 ...

Page 186: ...CKET command feature set Bit 3 1 Supports the power management feature set Bit 2 1 Supports the Removable Media feature set Bit 1 1 Supports the Security Mode feature set Bit 0 1 Supports the SMART feature set 17 WORD 83 Bit 15 0 Bit 14 1 Bit 13 1 Supports the FLUSH CACHE EXT command Bit 12 1 Supports the FLUSH CACHE command Bit 11 1 Supports the Device Configuration Overlay feature set Bit 10 1 4...

Page 187: ...its 12 9 Reserved Bit 8 1 Support the World wide name Bit 7 1 Support the WRITE DMA QUEUED FUA EXT command Bit 6 1 Support the WRITE DMA FUA EXT and WRITE MULTIPLE FUA EXT commands Bit 5 1 Support the General Purpose Logging feature Bits 4 2 Reserved Bit 1 1 Supports the SMART SELF TEST Bit 0 1 Supports the SMART Error Logging 19 WORD 85 Bit 15 Undefined Bit 14 1 Supports the NOP command Bit 13 1 ...

Page 188: ...coustic Management function from the SET FEATURES command Bit 8 1 From the SET MAX SET PASSWORD command Bits 7 6 Same definition as WORD 83 Bit 5 1 Enables the Power Up In Standby function Bit 4 1 Enables the Removable Media Status Notification function Bit 3 1 Enables the Advanced Power Management function Bits 2 0 Same definition as WORD 83 21 WORD 87 Bit 15 0 The device always returns the fixed...

Page 189: ...ports the Mode 2 Bit 1 1 Supports the Mode 1 Bit 0 1 Supports the Mode 0 23 WORD 89 Execution time of SECURITY ERASE UNIT command Value Time 0 Undefined 1 254 Display Value 2 minutes 255 More than 508 minutes 24 WORD 94 Bits 15 8 X FE Recommended acoustic management value Bits 7 0 X XX Current set value FE C0 Performance mode BF 80 Acoustic mode 00 Acoustic management is unused it It is same as FE...

Page 190: ...CODE is supported Bit 3 1 READ and WRITE DMA EXT GPL optional commands are supported Bit 2 1 WRITE UNCORRECTABLE EXT is supported Bit 1 1 Write Read Verify feature set is supported Bit 0 1 Clearing DRQ bit to zero when error bit is set is supported No Dummy transferring function is supported 28 WORD 120 Bit 15 0 Bit 14 1 Bits 13 5 0 Bit 4 1 Segmented feature for DOWNLOAD MICROCODE is supported Bit...

Page 191: ...Data Tables supported Bit 4 1 SCT Features Control supported Bit 3 1 SCT Error Recovery Control supported Bit 2 1 SCT Write Same supported Bit 1 1 SCT Long Sector Access supported Bit 0 1 SCT Command Transport supported 31 WORD 210 211 Write Read Verify Sector Count Mode 3 Only The number of sectors to be verified If Write Read Verify features set is enabled Mode 3 Value 400h 40000h sectors 32 WOR...

Page 192: ...mand mode 3 When the command for which mode 3 FR reg 03h is specified with DOWNLOAD MICROCODE 0x92 is issued the host is a unit of possible transfer of the minimum transfer sector Value 0001h sector 35 WORD 235 Maximum number of 512Byte units per DOWNLOAD MICROCODE command mode3 When the command for which mode 3 FR reg 03h is specified with DOWNLOAD MICROCODE 0x92 is issued the host is a unit of p...

Page 193: ...r mode 1 X 04 Enables the automatic reassign Note 1 X 05 Enables the advanced power management function 2 X 06 Enables the Power Up In Standby function Note 1 X 07 Spin up the Power Up In Standby status device Note 1 X 0B Enable Write Read Verify feature set Optional 5 X 10 Enables the Serial ATA function 3 X 33 Undefined Note 1 X 42 Enables the Acoustic management function 4 X 54 Undefined Note 1...

Page 194: ...transferring Note 2 Note 1 Although there is a response to the command nothing is done Note 2 Although there is a response to the command and this command reflects on Identify Device information DRQ bit is always cleared to zero when error is occurred in PIO read command This drive always doesn t the dummy transferring At power on the default mode is set as follows Write cache function Enabled Tra...

Page 195: ... communication error occurred ST 51h ER 14h At command issuance Shadow Block O registers setting contents CM 1 1 1 0 1 1 1 1 DH x x x x xx CH CL SN SC FR xx xx xx or 5 xx or 1 to 5 See Table 5 34 At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC E xx xx xx xx Error information ...

Page 196: ... in WORD 63 and 88 in Identify Device information However the actual data transfer rate depends on the serial ATA signaling rate in WORD 76 in Identify Device information Transfer mode Sector Count file PIO default transfer mode 00000 000 X 00 00001 000 X 08 Mode 0 00001 001 X 09 Mode 1 00001 010 X 0A Mode 2 00001 011 X 0B Mode 3 PIO flow control transfer mode X 00001 100 X 0C Mode 4 00010 000 X 1...

Page 197: ...om Active Idle to Low Power Idle to Standby The Mode 2 level requires the longest shifting time depending on the APM level settings The settings of the APM level revert to their default values Mode 1 when power on or COMRESET occurs for the drive APM Level Sector Count Field Mode 0 Active Idle Low Power Idle Mode 1 Active Idle Low Power Idle Mode 2 Active Idle Low Power Idle Standby Reserve State ...

Page 198: ...Guaranteed In Order Data Delivery 04h 1 Asynchronous Notification 05h 1 Software Settings Preservation 06h 4 1 The device normally responds to the command but performs no operation 2 This feature is disabled when power is on While this function is enabled the device does not return the DMA Activate FIS for the first data sector after the WRITE FP DMA QUEUED command is issued 3 This feature is disa...

Page 199: ...ormance operates as for Performance mode and low speed seek by which the seek sound is suppressed operates as for Acoustic mode Setting the seek mode by this command is applied to the seek operation in all command processing 5 Write Read Verify feature optional SN SC Description 00h Mode 0 Enabled Always 01h Mode 1 The first 65 536 logical sectors written by the host after every spin up or reset o...

Page 200: ...word version number This value is valid only when Word 0 Bit 0 is set to one 18 to 255 Reserved Table 5 36 Relationship between combination of Identifier and Security level and operation of the lock function Identifier Level Description User High The specified password is set as a new user password The lock function is enabled after the device is turned off and then on LOCKED MODE can be canceled ...

Page 201: ...Frozen mode ST 51h ER 04h 3 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 0 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Register contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 202: ...ned When the user password is selected The password is compared with the user password already set If the passwords are the same LOCKED MODE is canceled Otherwise the Aborted Command error is returned If the password comparison fails the device decrements the UNLOCK counter The UNLOCK counter initially has a value of five When the value of the UNLOCK counter reaches zero this command or the SECURI...

Page 203: ...ozen mode ST 51h ER 04h 3 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 0 1 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Register contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 204: ...erased unnecessarily by the SECURITY ERASE UNIT command Error reporting conditions 1 The device is in Security Frozen mode ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 0 1 1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information D...

Page 205: ...set The device erases user data invalidates the user password and releases the lock function if the passwords are the same Although this command invalidates the user password the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password Table 5 38 Contents of Security Erase Unit Password Word Contents 0 Control Word Bit 0 Identif...

Page 206: ...1h ER 04h 3 The device is in Security Frozen mode ST 51h ER 04h 4 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 1 0 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 207: ...when the power is turned off If this command is reissued in FROZEN MODE the command is completed and FROZEN MODE remains unchanged The following medium access commands return the Aborted Command error when the device is in LOCKED MODE READ DMA EXT READ MULTIPLE EXT READ SECTORS EXT READ VERIFY SECTORS EXT WRITE DMA EXT WRITE MULTIPLE EXT WRITE SECTORS EXT WRITE VERIFY SECURITY DISABLE PASSWORD SEC...

Page 208: ...LE FUA EXT Error reporting conditions 1 The device is in Security Locked mode ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 1 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error...

Page 209: ...ready set and releases the lock function if the passwords are the same Although this command invalidates the user password the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password If the user password or master password transferred from the host does not match the Aborted Command error is returned Issuing this command while ...

Page 210: ...evice is in Security Frozen mode ST 51h ER 04h 4 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 1 1 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 211: ...CH CL and SN field Then reports the status to the host system Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 0 DH x L x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x Max head LBA MSB CH CL SN SC ER CYL No...

Page 212: ...alue set by this command is held even after power on When the VV bit is 0 the value set by this command becomes invalid when the power is turned on and the maximum address returns to the value most lately set when VV bit 1 When the command with VV 1 has not issued before the maximum address returns to the default value When the READ NATIVE MAX ADDRESS command has been issued immediately preceding ...

Page 213: ... issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 DH x L x x HD No LBA CH CL SN CYL No MSB LBA CYL No LSB LBA SCT No LBA LSB SC xx VV FR xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER CYL No MSB LBA CYL No LSB LBA SCT No LBA LSB xx Error information SET MAX SET PASSWORD Features Field 01h This command reques...

Page 214: ...rred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx 01 At command completion Shadow Block Registers contents to be read ST Status information DH CH CL SN SC ER xx xx xx xx xx Error information Password information Words Contents 0 Reserved 1 to 16 Password 32 bytes 17 to 255 Reserved ...

Page 215: ...T MAX LOCK state until a power cycle or the acceptance of SET MAX UNLOCK or SET MAX FREEZE LOCK command Error reporting conditions 1 The device is in Set Max Locked mode or Set Max Freeze Locked mode ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx 02 At command ...

Page 216: ...n this counter reaches zero then SET MAX UNLOCK command returns command aborted until a power cycle If the password compare matches then the device makes a transition to the Set Max Unlocked state and all SET MAX commands will be accepted Error reporting conditions 1 The device is in Set Max Locked mode or Set Max Freeze Locked mode ST 51h ER 04h 2 The device is in Set Max Unlocked mode ST 51h ER ...

Page 217: ...MAX ADDRESS SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK SET MAX FREEZE LOCK Error reporting conditions 1 The device is in Set Max Locked mode or Set Max Freeze Locked mode ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx 04 At command completion Shadow Block...

Page 218: ...The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ SECTOR S command At command issuance Shadow Block Registers setting contents CM 0 0 1 0 0 1 0 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion ...

Page 219: ...he command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ DAM command At command issuance Shadow Block Registers setting contents CM 0 0 1 0 0 1 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow...

Page 220: ... ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 0 0 1 0 0 1 1 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx xx xx xx xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER Native max address LBA ...

Page 221: ...s 1 The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ MULTIPLE command At command issuance Shadow Block Registers setting contents CM 0 0 1 0 1 0 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command complet...

Page 222: ...dress 10h For the data format of Read Log Ext log page 10h see Table 5 39 The events of the PHY level on an interface are collected and it registers with Read Log Extend page 11h This Read Log Ext log page can be read by specifying Sector offset 00h Sector count 01h and Log address 11h For the data format of Read Log Ext log page 11h see Table 5 42 If this command is not supported or if an invalid...

Page 223: ...EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx Sector offset 15 8 Sector offset 7 0 xx Log address Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information ...

Page 224: ...07 Dev Head field value 08 Sector Number Exp field value 09 Cylinder Low Exp field value 0A Cylinder High Exp field value 0B Reserved 0C Sector Count field value 0D Sector Count Exp field value 0E to FF Reserved 100 to 1FE Vendor Unique 1FF Check sum Table 5 40 Tag field information Bit Description 0 to 4 If bit 7 is 0 this field has an error tag number 5 6 Reserved 7 If this bit is 0 the field co...

Page 225: ...unters in the page 1 Command failed due to an ICRC error 2 Data FIS R_ERR ending status transmitted and received 3 Data FIS R_ERR ending status transmitted 4 Data FIS R_ERR ending status received 5 Non data FIS R_ERR ending status transmitted and received 6 Non data FIS R_ERR ending status transmitted 8 Non data FIS retries transmitted 9 Transitions from drive PhyRdy to drive PhyNRdy A Signature D...

Page 226: ...Registers setting CM 0 0 1 0 1 1 1 1 DH 1 L 1 DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx 00h 00h xx E0h 00h 01h xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information ...

Page 227: ...Block Registers setting CM 0 0 1 0 1 1 1 1 DH 1 L 1 DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx 00h 00h xx E1h xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information ...

Page 228: ... The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the WRITE SECTOR S command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 0 1 0 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completio...

Page 229: ...The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the WRITE DMA command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 0 1 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shad...

Page 230: ... bit 1 When the command with VV 1 has not issued before the maximum address returns to the default value After power on the host can issue this command only once when VV bit 1 If this command with VV bit 1 is issued twice or more any command following the first time will result in an ID Not Found error When the SET MAX ADDRESS command is executed SET MAX ADDRESS EXT command is aborted The address ...

Page 231: ...T MAX LBA 23 16 SET MAX LBA 39 32 SET MAX LBA 15 8 SET MAX LBA 31 24 SET MAX LBA 7 0 xx SC xx VV FR EXP FR xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER SET MAX LBA 47 40 SET MAX LBA 23 16 SET MAX LBA 39 32 SET MAX LBA 15 8 SET MAX LBA 31 24 SET MAX LBA 7 0 xx xx Error information ...

Page 232: ... The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the WRITE MULTIPLE command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 1 0 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completio...

Page 233: ...same as those of the WRITE DMA EXT command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 1 1 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EX...

Page 234: ...or Sector offset the Aborted Command error occurs Error reporting conditions 1 An error was detected during power on processing ST 51h ER 04h 2 An error was detected during wake up processing in cases where wake up processing is required before execution of this command ST 51h ER 04h 3 A write fault was detected while the write cache was disabled ST 71h ER 10h 4 While the write cache is enabled if...

Page 235: ...EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx Sector offset 15 8 Sector offset 7 0 xx Log address Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information ...

Page 236: ...egisters setting CM 0 0 1 1 1 1 1 1 DH 1 L 1 DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx 00h 00h xx E0h 00h 01h xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information ...

Page 237: ...ck Registers setting CM 0 0 1 1 0 0 0 0 DH 1 L 1 DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx 00h 00h xx E1h xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information ...

Page 238: ...ions 1 The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ VERIFY SECTOR S command At command issuance Shadow Block Registers setting contents CM 0 1 0 0 0 0 1 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At comma...

Page 239: ...nsaction is done disk write error that occurs while executing this command is reported The write operation ends in the sector Even if it is during the block where the error occurs In this case the number of sectors of remainder since the sector where the logical block address and the error where the error occurs occur is set in the shadow block register Error reporting conditions 1 The command was...

Page 240: ...completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 xx xx Error information Table 5 43 Operation mode Feature bit 7 0 1 Operation Support situation 55h Create a pseudo uncorrectable error Support AAh Create a flagged error A pseudo uncorrectable error is not cre...

Page 241: ...and issuance Shadow Block Registers setting contents CM 0 1 0 0 0 1 1 1 DH x x x x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx Sector offset 15 8 Sector offset 7 0 xx Log address Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx ...

Page 242: ...d issuance Shadow Block Registers setting contents CM 0 1 0 1 0 1 1 1 DH x x x x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx Sector offset 15 8 Sector offset 7 0 xx Log address Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx...

Page 243: ... CL SN EXP SN SC EXP LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 xx SC TAG xx FR EXP FR xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information FUA If this bit is 1 the device always reads data from media regardless of whether the data requested by th...

Page 244: ...CH EXP CH CL EXP CL SN EXP SN SC EXP LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 xx SC TAG xx FR EXP FR xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information FUA If this bit is 1 the device always reports the status after data is written to a medium...

Page 245: ...he same as those of the WRITE MULTIPLE EXT command At command issuance Shadow Block Registers setting contents CM 1 1 0 0 1 1 1 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP ...

Page 246: ...s 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 0 1 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx xx xx xx xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error...

Page 247: ... V EXECUTE DEVICE DIAGNOSTIC V 1 1 1 1 INITIALIZE DEVICE PARAMETERS V V V V V DOWNLOAD MICROCODE V V V V V STANDBY IMMEDIATE V V V V V IDLE UNLOAD IMMEDIATE V V V V V STANDBY V V V V V IDLE V V V V V CHECK POWER MODE V V V V V SLEEP V V V V V SMART V V V V V V V DEVICE CONFIGURATION V V V V V V READ MULTIPLE V V V V V V V WRITE MULTIPLE V V V V V V SET MULTIPLE MODE V V V V V READ DMA V V V V V V ...

Page 248: ... V V V V V READ MULTIPLE EXT V V V V V V V READ LOG EXT V V V V V V V WRITE SECTOR S EXT V V V V V V WRITE DMA EXT V V V V V V SET MAX ADDRESS EXT V V V V V V WRITE MULTIPLE EXT V V V V V V WRITE DMA FUA EXT V V V V V V WRITE LOG EXT V V V V V V READ VERIFY SECTOR S EXT V V V V V V V WRITE UNCORRECTABLE EXT V V V V V V READ LOG DMA EXT V V V V V V V WRITE LOG DMA EXT V V V V V V READ FP DMA QUEUED...

Page 249: ...e following commands can be executed even if DRDY bit is 0 EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS Note Each FIS type is referred to as follows in this section FIS Frame Information Structure type Abbreviation Register Host to Device RegHD Register Device to Host RegDH DMA Active Device to Host DMA Active DMA Setup Device to Host or Host to Device Bidirectional DMA Setup Set Device ...

Page 250: ...EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS SET FEATURES SET MULTIPLE MODE READ NATIVE MAX ADDRESS EXT SET MAX ADDRESS EXT SET MAX LOCK SET MAX FREEZE LOCK IDLE IDLE UNLOAD IMMEDIATE STANDBY STANDBY IMMEDIATE CHECK POWER MODE SMART DISABLE OPERATION SMART ENABLE DISABLE AUTOSAVE SMART ENABLE OPERATION SMART EXECUTE OFFLINE IMMEDIATE SMART RETURN STATUS SECURITY ERASE PREPARE SECURITY FR...

Page 251: ...for command execution without data transfer 1 The device receives a non data command with the RegHD FIS 2 The device executes the received command 3 Command execution is completed 4 The device reports the completion of command execution by sending to the host the RegDH FIS with 1 set in the I bit Device Host RegHD RegDH Figure 5 13 Non data command protocol ...

Page 252: ...ents command execution the device sends the RegDH FIS with 1 set in the I bit 3 When the device is ready to send data it sets 0 in the BSY bit 1 in the DRQ bit and 1 in the I bit of the Status field of the PIO Setup FIS then sends this FIS to the host At this time if the requested data is read from the last sector to be processed the device sets 0 in both the BSY bit and DRQ bit of the E_Status fi...

Page 253: ...5 4 Command Protocol C141 E293 5 179 Device Host RegHD PIO Setup DATA Figure 5 14 PIO data in command protocol ...

Page 254: ... device An outline of this protocol is as follows 1 The device receives a PIO data out command with the RegHD FIS 2 If an error remaining in the device prevents command execution the device sends the RegDH FIS with 1 set in the I bit 3 When the device is ready to receive data it sets 0 in the BSY bit and 1 in the DRQ bit of the Status field of the PIO Setup FIS At this time the device sets 0 in th...

Page 255: ...sends the RegDH FIS with 1 set in the I bit to complete execution of the command If the device has an error it reports the error If any data remains to be received by the device this protocol is repeated starting from step 3 The maximum data size is 8 KB Device Host RegHD PIO Setup DATA RegDH Figure 5 15 PIO data out command protocol ...

Page 256: ...eceives a DMA data in command with the RegHD FIS 2 If an error remaining in the device prevents command execution the device sends the RegDH FIS with 1 set in the I bit 3 When the device is ready to send data it sends the Data FIS to the host 4 When all data has been transferred the device sends the RegDH FIS with 1 set in the I bit to complete execution of the command If any data remains to be se...

Page 257: ... the RegHD FIS 2 If an error remaining in the device prevents command execution the device sends the RegDH FIS with 1 set in the I bit 3 When the device is ready to receive data it sends the DMA Active FIS to the host 4 The device receives the Data FIS from the host 5 When all data has been transferred the device sends the RegDH FIS with 1 set in the I bit to complete execution of the command If a...

Page 258: ...the SetDB FIS corresponding to the tag number of the completed command is set by the device and the device sets 0 in the Err bit and 0 in the Error register in the Set Device Bits FIS Then it sends the Set Device Bits FIS to the host 5 For the data transfer of the WRITE FP DMA QUEUED command if the DMA Setup Auto Activate function is disabled the device sends to the host the DMA Setup FIS with the...

Page 259: ...SoftReset and COMRESET The device reports abort for other commands 10 If the device receives the READ LOG EXT command with page 10h specified queued commands are aborted Then after the device sends to the host the SetDB FIS ERR 0 ERRReg 0 I 0 and SActive 0xFFFFFFFF it sends to the host the log data for the READ LOG EXT command with page 10h specified and reports the status of this command Next the...

Page 260: ...Interface 5 186 C141 E293 Device Host RegHD RegDH DMA Setup SetDB DATA DMACT Figure 5 19 WRITE FP DMA QUEUED command protocol ...

Page 261: ... the SATA interface is established the host sets 0xFFh in the Status field of the Shadow Block Register The device completes the power on sequence within 10 ms so that communication with the SATA interface can be established Device TX Host RX Host TX Device RX Host power on Host ComReset Host releases ComReset Host calibrate Host ComWake Host releases ComWake Host Align Host data Device ComInit De...

Page 262: ...vice RX Host device on Host ComReset Host releases ComReset Host calibrate Host ComWake Host releases ComWake Host Align Host data Device ComInit Device releases ComInit Device Calibrate Device ComWake Device Align Device data Figure 5 21 COMRESET sequence ...

Page 263: ...Operations 6 1 Reset and Diagnosis 6 2 Power Save 6 3 Power Save Controlled by Interface Power Management IPM 6 4 Read ahead Cache 6 5 Write Cache This chapter explains each of the above operations C141 E293 6 1 ...

Page 264: ...ication with the SATA interface is established the host sets 0xFFh in the Status field of the Shadow Block The device establishes communication with the SATA interface PHY Ready within 10 ms The device sends the FIS STS 50h to notify the host that the device is ready Note Figure 6 1 assumes that power is turned on after the power off state continued for more than five seconds Figure 6 1 Response t...

Page 265: ...6 1 Reset and Diagnosis Figure 6 2 Response to power on when the device is powered on earlier than the host C141 E293 6 3 ...

Page 266: ...e when power is turned on and a power on reset is then cancelled The device establishes communication with the SATA interface PHY Ready and sends the RegDH FIS STS 50h to notify the host that the device is ready Then the COMRESET sequence is completed Figure 6 3 Response to COMRESET 6 4 C141 E293 ...

Page 267: ...fer to Section 5 3 2 28 If a device supports software settings preservation the feature shall be enabled by default 6 1 2 2 COMRESET preservation requirements The software settings that shall be preserved across COMRESET are listed below The device is only required to preserve the indicated software setting if it supports the particular feature command the setting is associated with INITIALIZE DEV...

Page 268: ...ment enable disable setting established by the SET FEATURES command with subcommand code of 05h or 85h The advanced power management level established in the Sector Count field when advanced power management is enabled SET FEATURES subcommand code 05h shall also be preserved SET FEATURES Read Look Ahead The read look ahead enable disable setting established by the SET FEATURES command with subcomm...

Page 269: ...reset When a software reset is accepted the device performs a self diagnosis and it sends the RegDH FIS STS 50h to notify the host that the device is ready Then the software reset sequence is completed Figure 6 4 Response to a software reset C141 E293 6 7 ...

Page 270: ...mode all the electric circuit in the device are active or the device is under seek read or write operation A device enters the active mode under the following conditions The media access system is received 2 Active idle mode In this mode circuits on the device are set to power save mode The device enters the Active idle mode under the following conditions After completion of the command execution ...

Page 271: ...the low power idle state APM Mode 2 The time specified by the STANDBY or IDLE command has elapsed after completion of the command A reset is issued in the sleep mode When one of following commands is issued the command is executed normally and the device is still stayed in the standby mode Reset hardware or software STANDBY command STANDBY IMMEDIATE command INITIALIZE DEVICE PARAMETERS command CHE...

Page 272: ...Operations 6 2 2 Power commands The following commands are available as power commands IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE SET FEATURES APM setting 6 10 C141 E293 ...

Page 273: ...ich the device must switch to Active mode from the Interface Power Down state Period in which the device must switch to Active mode Partial mode Maximum 10 μs Slumber mode Maximum 10 ms 1 Active mode The interface is in the Active state and commands can be accepted 2 Partial mode In this mode shallow Power Save mode is set for the interface circuit The device switches to Partial mode when the foll...

Page 274: ...h the PMACK signal The device sends the PMREQ_S signal and the host responds with PMACK signal The device cannot switch to Slumber mode if the following condition is satisfied The device responds with the PMNAK signal because it is not waiting for commands The device returns to Active mode from Slumber mode when the following condition is satisfied The device receives the COMRESET or ComWake signa...

Page 275: ...erred without accessing the disk media As the result faster data access becomes possible for the host 6 4 1 Data buffer structure This device contains a data buffer This buffer is divided into two areas one area is used for MPU work and the other is used as a read cache for another command See Figure 6 5 Example of 8 MB buffer For MPU work For R W command 8 192 KB 8 388 608 bytes Figure 6 5 Data b...

Page 276: ...nction is prohibited by the SET FEATURES command the caching operation is not performed 2 Data that is a target of caching The data that is a target of caching are as follows 1 Read ahead data that is read from disk media and saved to the data buffer upon completion of execution of a command that is a target of caching 2 Pre read data that is read from disk media and saved to the data buffer befor...

Page 277: ...E CONFIGURATION DOWNLOAD MICROCODE WRITE UNCORRECTABLE EXT READ LOG DMA EXT WRITE LOG DMA EXT UNSUPPORT COMMAND INVALID COMMAND 1 2Commands that partially invalidate caching data READ DMA READ MULTIPLE READ SECTOR S READ DMA EXT READ MULTIPLE EXT READ SECTOR S EXT READ FP DMA QUEUED WRITE DMA WRITE MULTIPLE WRITE SECTOR S WRITE DMA EXT WRITE MULTIPLE EXT WRITE SECTOR S EXT WRITE DMA FUA EXT WRITE ...

Page 278: ...AP is set at the requested data reading position HAP host address Read segment pointer DAP disk address pointer 2 During reading of read requested data the request data that has already been read is sent to the host system Read requested data Free space HAP DAP Read requested data is stored until this point 3 When reading of read requested data is completed and transfer of the read requested data ...

Page 279: ...e Read requested data HAP host address pointer DAP disk address pointer 2 During reading of read requested data the request data that has already been read is sent to the host system Cache valid data Free space Read requested data HAP host address pointer DAP disk address pointer 3 When reading of read requested data is completed and transfer of the read requested data to the host system is comple...

Page 280: ...during the read ahead operation a transfer of the read requested data starts while the read ahead operation is in progress 1 An example is the state shown below where the previous read command is executing sequential reading First HAP is set at the location where hit data is stored HAP It is reset to the hit data location for transfers HAP end location of the previous read command DAP end location...

Page 281: ...T LBA LAST LBA 1 HAP is set at the address where partial hit data is stored and Transfer is started Cache valid data Partial hit data HAP host address pointer 2 DAP and HAP are set at the head of Buffer newly allocated and insufficient data is read Read segment HAP host address pointer DAP disk address pointer 3 When reading the read requested data ends and the transmission of the read requested d...

Page 282: ...aching function is prohibited by the SET FEATURES command 2 Invalidation of cached data If an error occurs during writing onto media write processing is repeated up to as many times as specified for retry processing If retry fails for a sector because the retry limit is reached automatic alternate sector processing is executed for the sector If the automatic alternate sector processing fails the d...

Page 283: ...re reset is received while cached data is stored on the data buffer data of the data buffer is written on the media and reset processing is then performed This is true for both a hard reset and soft reset 6 Cashing function when power supply is turned on The cashing function is invalid until Calibration is done after the power supply is turned on about 10 sec It is effective in Default after that ...

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Page 285: ...eplacement of the disk drive The following are explained Rules for regular maintenance and troubleshooting Display of maintenance level field and factory Display of machine revision number and number change in the field Tools and test devices needed for each maintenance level Standard testing for each maintenance level Recommended procedure for troubleshooting and fault diagnosis Disk drive remova...

Page 286: ... touching a PCA or the drive wear a wrist strap and perform the human body grounding to discharge static electricity from your body This will prevent irreparable damage to the PCA and the head of the drive 2 Don t install or remove a PCA or connect or disconnect a cable or connector plug when the drive is powered This will prevent electrical damage to the disk drive 3 Operating the disk drive with...

Page 287: ...k drive service system and repair facility When making a request for repair or parts replacement you should provide related information usually including a Model name of disk drive part number P N disk drive revision number manufacture serial number S N and date of manufacture of the disk drive b Circumstances when the fault occurred Date of trouble occurred System configuration Environmental cond...

Page 288: ...rist strap Hold by the DE section do not directly touch the PCA unit unnecessarily b Unpacking a Use a flat workplace find which side of the pack is up and be careful not to have the wrong side facing upwards Do not place the device directly on a hard table place it on something soft such as a rubber mat b Be careful not to apply any excessive force to the packed device when removing the shock abs...

Page 289: ...ither of the allowable packed positions Refer to Section 3 2 f Storage a Store in dampproof packaging b Take care that the environmental requirements satisfy the non operating environmental specifications described in Section 1 4 c To prevent condensation do not subject the device to sudden changes of temperature 7 1 3 Maintenance levels Because of its compact size and special repair requirements ...

Page 290: ...gle alphabetic character followed by a single alphanumeric character It is stuck on the DE and marked on the revision number label Figure 7 1 shows the disk drive revision number label format Disk drive revision number Firmware code revision Figure 7 1 Disk drive revision number label 7 6 C141 E293 ...

Page 291: ...t the relevant number in the relevant alphabetic character row using marks see Figure 7 2 3 Firmware code and revision First 4 digit indicates a firmware code and rest 4 digit indicates its revision Note For a change of revision number after delivery Fujitsu issues a Change Request Notice and the disk drive revision number after the change When a change is made at the user site the revision number...

Page 292: ...k drive has the following self diagnostics These self diagnostics allow normal basic operation of an isolated disk drive can be checked Initial self diagnostics SMART command SMART Execute Off Line Immediate command 7 1 7 Test The disk drive test can be divided into the following three levels Operating test See Subsection 7 2 1 Operating test Diagnostic test See Subsection 7 2 2 Diagnostic test Fi...

Page 293: ...t acceptable Test acceptable Disk drive normal System normal Test acceptable Start Yes Yes Yes No Disk drive failure analysis Table 7 2 Diagnostic test with the host computer or test equipment No No Analyze the system related failure Disk drive replacement or repair Check the host system Table 7 1 Yes Yes Yes No No Figure 7 3 Test flowchart C141 E293 7 9 ...

Page 294: ...d 2 Check the power cable and connector 3 If it is concluded that the disk drive is the cause replace the disk drive Table 7 2 Disposition for Error Field contents Error bit Method of disposition BIT0 BIT1 BIT4 BIT6 Any of these bits are 1 If it is concluded that the disk drive is the cause replace the drive BIT4 1 and BIT2 1 or BIT3 1 and BIT2 1 or BIT2 BIT7 Any of these bits are 1 1 Check the st...

Page 295: ...he host determines the processing return or halt following the detected failure state To troubleshoot the failure reported in the test at this level accurately reproduce the condition that caused the failure Then by replacing the disk drive try to separate the fault from the other sections of the disk drive host system 7 2 2 Diagnostic test The diagnostic test is used to separate a confirmed disk ...

Page 296: ...n When a cause of failure is clear for example abnormal sound in the DE or burnt parts on the PCA a level of troubleshooting is low 7 3 2 Troubleshooting disk drive replaced in field It is recommended that the whole drive be replaced in maintenance of this level If replacing the drive corrects the fault return the old drive to the factory for testing and repair If the new drive shows the same faul...

Page 297: ... host receptacle System cable Confirm that all cable connections throughout the system correctly connected System diagnostic test To further isolate the failure if it can be done execute the system level diagnostic routine described in the host computer manual Intermittent or indefinite error Check the AC voltage level at the power supply section and recheck the DC voltage level at the disk drive ...

Page 298: ...nd a reappearance test is performed To reappearance a same trouble at user the failed drive is connected to the host system If no trouble occurs by the normal test the reappearance test is performed by adding the voltage temperature load using a disk drive tester or tools according to the user environment When a trouble reappeared troubleshoot the cause of failure Then replace the failed unit or p...

Page 299: ... antistatic bag in compliance with section 7 1 2 5 d and 5 e To protect the device from damage and prevent the worker getting hurt observe the following cautions and precautions in Subsection 7 1 1 Damage or Device damage 1 Perform any removal after the system power is completely disconnected The cable must not be disconnected and the screws that attach the drive must not be removed with the power...

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Page 301: ...tacle described in this Glossary when a drive is connected to a host system without use an interface cable In case of use an interface cable for connecting to a host system it means the connector plug which consists of terminals and housing of the cable Cover A lid of DE It is a metallic part labeled the model name and its revision This part is attached to the opposite side from PCBA on the disk d...

Page 302: ...l delay Power save mode The power save modes are idle mode standby mode and sleep mode In idle mode the drive is neither reading writing nor seeking data In standby mode the spindle motor is stopped and circuits other than the interface control circuit are sleeping The drive enters sleep mode when the host issues the SLEEP command Reserved Reserved bits bytes and fields are set to zero and unusabl...

Page 303: ...vice 1 The slave is a second drive that can operate on the AT bus The slave is daisy chained with the first drive operating in conformity with the ATA standard Status The status is a piece of one byte information posted from the drive to the host when command execution is ended The status indicates the command termination state VCM Voice coil motor The voice coil motor is excited by one or more ma...

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Page 305: ...rite fault E ECC Error checking and correction ER Error field ERR Error EU European Union F FR Feature field G GB Gigabyte H HA Host adapter HDD Hard disk drive I IDNF ID not found IRQ14 Interrupt request 14 L LED Light emitting diode M MB Megabyte MB s Megabyte per seconds MPU Micro processor unit P PCA Printed circuit assembly PIO Programmed input output R RLL Run length limited RoHS The Restric...

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Page 307: ...6 15 caching operation 6 14 capability off line data collection 5 63 cashing function at power on 6 21 caution handling 3 7 CHECK POWER MODE 5 52 checksum 5 64 5 66 5 68 circuit controller 2 3 read write 2 3 circuit configuration 4 3 4 5 circulation filter 2 3 CN1 3 10 code command 5 27 5 173 diagnostic 5 41 command code 5 27 5 173 command code and parameter 5 27 command data structure 5 66 comman...

Page 308: ...REEZE LOCK 5 85 DEVICE CONFIGURATION IDENTIFY 5 86 DEVICE CONFIGURATION IDENTIFY data structure 5 87 5 88 DEVICE CONFIGURATION RESTORE 5 85 DEVICE CONFIGURATION SET 5 86 device connector 3 9 device control field 5 26 device overview 1 1 device ready DRDY bit 5 25 device seek complete DSC bit 5 25 device specification 1 5 device write fault DF bit 5 25 device head field 5 24 device initiated interf...

Page 309: ...4 frame structure mounting 3 4 FSN E0h 5 162 full hit 6 18 function and performance 1 2 G gray code 4 16 guarantee failure threshold 5 64 guarantee failure threshold value data format of 5 59 H handling caution 3 7 head 2 2 high resistance against shock 1 3 high speed transfer rate 1 2 HIPM 1 16 hit full 6 18 partial 6 19 sequential 6 17 host command 5 27 host system connection 3 9 host system con...

Page 310: ...and protocol 5 176 5 177 O off line data collection capability 5 63 off line data collection status 5 61 5 62 operation 6 1 cache 6 20 caching 6 14 DOWNLOAD MICROCODE 5 44 operation confirmation 7 11 operation mode 5 166 operation test 7 11 operation to move head to reference cylinder 4 17 orientation 3 3 out of band signaling 5 4 outer guard band 4 14 outerview disk drive 2 2 outline 4 2 outline ...

Page 311: ... 4 response to power on 6 2 response to software reset 6 7 rewriting microcode data 640 K bytes example of 5 45 ripple 1 7 rule for maintenance 7 2 S SATA interface 2 3 SATA interface cable connection 3 11 SCT COMMAND SET 5 76 5 162 SCT READ DATA 5 82 5 153 SCT STATUS REQUEST 5 72 5 152 SCT WRITE DATA 5 83 5 163 sector count field 5 23 sector number field 5 23 SECURITY DISABLE PASSWORD 5 135 SECUR...

Page 312: ...tus after command execution 5 22 status field 5 25 status field content 7 10 status flag 5 61 status report on error occurrence 6 21 status off line data collection 5 61 structure data buffer 6 13 subassembly 4 2 subcommand 5 55 surface temperature measurement point 3 6 surface temperature standard value 3 6 system configuration 2 3 system level 7 13 T tag field information 5 150 5 151 temperature...

Page 313: ...Index C141 E293 IN 7 WRITE UNCORRECTABLE EXT 5 165 WRITE VERIFY 5 36 write read recovery 4 16 write read verify feature 5 125 ...

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Page 315: ...ach item E Excellent G Good F Fair P Poor General appearance Technical level Organization Clarity Accuracy Illustration Glossary Acronyms Abbreviations Index Comments Suggestions List any errors or suggestions for improvement Page Line Contents Please send this form to the address below We will use your comments in planning future editions Address Fujitsu Learning Media Limited 1 6 34 Kounan Minat...

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Page 317: ...2320BH MJA2250BH MJA2160BH MJA2120BH MJA2080BH DISK DRIVES PRODUCT MAINTENANCE MANUAL C141 E293 01EN MJA2500BH MJA2400BH MJA2320BH MJA2250BH MJA2160BH MJA2120BH MJA2080BH DISK DRIVES PRODUCT MAINTENANCE MANUAL C141 E293 01EN ...

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