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5.5 Ultra DMA Feature Set

C141-E192-01EN

5-125

2)

The host shall generate an HSTROBE edge to latch the new word no sooner
than t

DVS

after changing the state of DD (15:0). The host shall generate an

HSTROBE edge no more frequently than t

CYC

for the selected Ultra DMA

Mode. The host shall not generate two rising or falling HSTROBE edges
more frequently than 2 t

CYC

for the selected Ultra DMA mode.

3)

The host shall not change the state of DD (15:0) until at least t

DVH

after

generating an HSTROBE edge to latch the data.

4)

The host shall repeat steps (1), (2) and (3) until the data transfer is complete
or an Ultra DMA burst is paused, whichever occurs first.

5.5.4.3 Pausing an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.3.9 and 5.6.3.2 for specific timing requirements).

a)

Host pausing an Ultra DMA data out burst

1)

The host shall not pause an Ultra DMA burst until at least one data word
of an Ultra DMA burst has been transferred.

2)

The host shall pause an Ultra DMA burst by not generating an
HSTROBE edge.

Note: The device shall not immediately negate DMARQ to initiate Ultra

DMA burst termination when the host stops generating
HSTROBE edges. If the host does not assert STOP, in order to
initiate Ultra DMA burst termination, the device shall negate
DDMARDY- and wait t

RP

before negating DMARQ.

3)

The host shall resume an Ultra DMA burst by generating an HSTROBE
edge.

b)

Device pausing an Ultra DMA data out burst

1)

The device shall not pause an Ultra DMA burst until at least one data
word of an Ultra DMA burst has been transferred.

2)

The device shall pause an Ultra DMA burst by negating DDMARDY-.

3)

The host shall stop generating HSTROBE edges within t

RFS

of the device

negating DDMARDY-.

4)

If the device negates DDMARDY- within t

SR

after the host has generated

an HSTROBE edge, then the device shall be prepared to receive zero or
one additional data words. If the device negates DDMARDY- greater
than t

SR

after the host has generated an HSTROBE edge, then the device

shall be prepared to receive zero, one or two additional data words. The
additional data words are a result of cable round trip delay and t

RFS

timing

for the host.

5)

The device shall resume an Ultra DMA burst by asserting DDMARDY-.

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Summary of Contents for MHT2020AT

Page 1: ...C141 E192 01EN MHT2080AT MHT2060AT MHT2040AT MHT2030AT MHT2020AT DISK DRIVES PRODUCT MANUAL ...

Page 2: ...ncidental or consequential damages arising therefrom FUJITSU DISCLAIMS ALL WARRANTIES REGARDING THE INFORMATION CONTAINED HEREIN WHETHER EXPRESSED IMPLIED OR STATUTORY FUJITSU reserves the right to make changes to any products described herein without further notice and without obligation This product is designed and manufactured for use in standard applications such as office work personal device...

Page 3: ...C141 E192 01EN Revision History 1 1 Edition Date Revised section 1 Added Deleted Altered Details 01 2003 01 20 1 Section s with asterisk refer to the previous edition when those were deleted ...

Page 4: ...This page is intentionally left blank ...

Page 5: ... an overview of the MHT Series and describes their features CHAPTER 2 Device Configuration This chapter describes the internal configurations of the MHT Series and the configuration of the systems in which they operate CHAPTER 3 Installation Conditions This chapter describes the external dimensions installation conditions and switch settings of the MHT Series CHAPTER 4 Theory of Device Operation T...

Page 6: ...y In the text the alert signal is centered followed below by the indented message A wider line space precedes and follows the alert message to show where the alert message begins and ends The following is an example Example Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields The main...

Page 7: ...t at the back of this manual and forward it to the address described in the sheet Liability Exception Disk drive defects refers to defects that involve adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system o...

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Page 9: ...rform the procedure correctly Task Alert message Page Normal Operation Data corruption Avoid mounting the disk near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handl...

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Page 11: ...ES PRODUCT MANUAL C141 E192 This manual Device Overview Device Configuration Installation Conditions Theory of Device Operation Interface Operations MHT2080AT MHT2060AT MHT2040AT MHT2030AT MHT2020AT DISK DRIVES MAINTENANCE MANUAL C141 F063 Maintenance and Diagnosis Removal and Replacement Procedure ...

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Page 13: ...number 1 5 1 3 Power Requirements 1 5 1 4 Environmental Specifications 1 8 1 5 Acoustic Noise 1 9 1 6 Shock and Vibration 1 9 1 7 Reliability 1 10 1 8 Error Rate 1 11 1 9 Media Defects 1 11 1 10 Load Unload Function 1 11 1 11 Advanced Power Management 1 12 CHAPTER 2 Device Configuration 2 1 2 1 Device Configuration 2 2 2 2 System Configuration 2 3 2 2 1 ATA interface 2 3 2 2 2 1 drive connection 2...

Page 14: ...ting 3 12 3 4 3 Master drive slave drive setting 3 12 3 4 4 CSEL setting 3 13 3 4 5 Power Up in Standby setting 3 14 CHAPTER 4 Theory of Device Operation 4 1 4 1 Outline 4 2 4 2 Subassemblies 4 2 4 2 1 Disk 4 2 4 2 2 Spindle 4 2 4 2 3 Actuator 4 2 4 2 4 Air filter 4 3 4 3 Circuit Configuration 4 3 4 4 Power on Sequence 4 6 4 5 Self calibration 4 7 4 5 1 Self calibration contents 4 7 4 5 2 Executio...

Page 15: ... 2 Logical Interface 5 6 5 2 1 I O registers 5 7 5 2 2 Command block registers 5 8 5 2 3 Control block registers 5 13 5 3 Host Commands 5 14 5 3 1 Command code and parameters 5 14 5 3 2 Command descriptions 5 18 5 3 3 Error posting 5 107 5 4 Command Protocol 5 109 5 4 1 PIO Data transferring commands from device to host 5 109 5 4 2 PIO Data transferring commands from host to device 5 111 5 4 3 Com...

Page 16: ... 132 5 6 3 1 Initiating an Ultra DMA data in burst 5 132 5 6 3 2 Ultra DMA data burst timing requirements 5 133 5 6 3 3 Sustained Ultra DMA data in burst 5 136 5 6 3 4 Host pausing an Ultra DMA data in burst 5 137 5 6 3 5 Device terminating an Ultra DMA data in burst 5 138 5 6 3 6 Host terminating an Ultra DMA data in burst 5 139 5 6 3 7 Initiating an Ultra DMA data out burst 5 140 5 6 3 8 Sustain...

Page 17: ...rocessing for defective sectors 6 10 6 4 Read ahead Cache 6 12 6 4 1 DATA buffer structure 6 12 6 4 2 Caching operation 6 13 6 4 3 Using the read segment buffer 6 15 6 4 3 1 Miss hit 6 15 6 4 3 2 Sequential Hit 6 16 6 4 3 3 Full hit 6 17 6 4 3 4 Partial hit 6 18 6 5 Write Cache 6 19 6 5 1 Cache operation 6 19 Glossary GL 1 Acronyms and Abbreviations AB 1 Index IN 1 ...

Page 18: ... connections 3 10 Figure 3 10 Power supply connector pins CN1 3 11 Figure 3 11 Jumper location 3 11 Figure 3 12 Factory default setting 3 12 Figure 3 13 Jumper setting of master or slave drive 3 12 Figure 3 14 CSEL setting 3 13 Figure 3 15 Example 1 of Cable Select 3 13 Figure 3 16 Example 2 of Cable Select 3 14 Figure 4 1 Power Supply Configuration 4 4 Figure 4 2 Circuit Configuration 4 5 Figure ...

Page 19: ... DMA data in burst 5 137 Figure 5 14 Device terminating an Ultra DMA data in burst 5 138 Figure 5 15 Host terminating an Ultra DMA data in burst 5 139 Figure 5 16 Initiating an Ultra DMA data out burst 5 140 Figure 5 17 Sustained Ultra DMA data out burst 5 141 Figure 5 18 Device pausing an Ultra DMA data out burst 5 142 Figure 5 19 Host terminating an Ultra DMA data out burst 5 143 Figure 5 20 Dev...

Page 20: ... Format of insurance failure threshold value data 5 72 Table 5 10 Log Directory Data Format 5 77 Table 5 11 Data format of SMART Summary Error Log 5 78 Table 5 11 1 Data format of SMART Comprehensive Error Log 5 79 Table 5 12 SMART self test log data format 5 80 Table 5 13 Selective self test log data structure 5 81 Table 5 14 Selective self test feature flags 5 82 Table 5 15 Contents of security ...

Page 21: ...on 1 7 Reliability 1 8 Error Rate 1 9 Media Defects 1 10 Load Unload Function 1 11 Advanced Power Management Overview and features are described in this chapter and specifications and power requirement are described The MHT Series are 2 5 inch hard disk drives with built in disk controllers These disk drives use the AT bus hard disk interface protocol and are compact and reliable ...

Page 22: ...rive supports an external data rate up to 100 MB s U DMA mode 5 4 Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed The average positioning time is 12 ms at read 1 1 2 Adaptability 1 Power save mode The power save mode feature for idle operation stand by and sleep modes makes The disk drives the MHT Series ideal for ...

Page 23: ...e read ahead data corresponds to the data requested by the next read command the data in the buffer can be transferred instead 4 Master slave The disk drives the MHT Series can be connected to ATA interface as daisy chain configuration Drive 0 is a master device drive 1 is a slave device 5 Error correction and retry by ECC If a recoverable error occurs the disk drives the MHT Series themselves att...

Page 24: ...05 120 39 070 080 Bytes per Sector 512 Recording Method 32 34 MEEPRML Rotational Speed 4 200 rpm 1 Average Latency 7 14 ms Positioning time read and seek Minimum Track Track Average Maximum Full 1 5 ms typ Read 12ms typ 22 ms typ Start time 3 5 sec typ Interface ATA 6 Max Cable length 18inches 0 46 m equipped with expansion function Data Transfer Rate To From Media To From Host 41 3 MB s Max 100 M...

Page 25: ...3 16 63 MHT2030AT 8 45 GB 16 383 16 63 MHT2020AT 8 45 GB 16 383 16 63 1 On using for the units of BIOS parameter 1 2 2 Model and product number Table 1 2 lists the model names and product numbers of the MHT Series Table 1 2 Model names and product numbers Model Name Capacity user area Mounting screw Order No MHT2080AT 80 GB M3 depth 3 CA06297 B048 MHT2060AT 60 GB M3 depth 3 CA06297 B046 MHT2040AT ...

Page 26: ...e voltage like the bottom figure isn t to occur at 5 V when power is turned off and a thing with no ringing Permissible level 0 2 V 5 0 100 200 300 400 500 600 700 800 Time ms 4 3 2 1 0 1 Figure 1 1 Negative voltage at 5 V when power is turned off ...

Page 27: ...MHT2080AT 0 011 W GB rank E MHT2060AT 0 011 W GB rank E MHT2040AT 0 022 W GB rank D MHT2030AT 0 022 W GB rank D MHT2020AT 1 Current at starting spindle motor 2 Current and power level when the operation command that accompanies a transfer of 63 sectors is executed 3 times in 100 ms 3 Power requirements reflect nominal values for 5 V power 4 Energy efficiency based on the Law concerning the Rationa...

Page 28: ...ed with the power on off sequence 1 4 Environmental Specifications Table 1 4 lists the environmental specifications Table 1 4 Environmental specifications Item Specification Temperature Operating Non operating Thermal Gradient 5 C to 55 C ambient 5 C to 60 C disk enclosure surface 40 C to 65 C 20 C h or less Humidity Operating Non operating Maximum Wet Bulb 8 to 90 RH Non condensing 5 to 95 RH Non...

Page 29: ...e 1 6 lists the shock and vibration specification Table 1 6 Shock and vibration specification Item Specification Vibration Swept sine 1 4 octave per minute Operating Non operating 5 to 500 Hz 9 8m s2 0 peak 1G 0 peak without non recovered errors 5 to 500 Hz 49m s2 0 peak 5G 0 peak no damage Shock half sine pulse Operating Non operating 2207 m s2 0 peak 225G 0 peak 2ms duration without non recovere...

Page 30: ...o repair MTTR is 30 minutes or less if repaired by a specialist maintenance staff member 3 Service life In situations where management and handling are correct the disk drive requires no overhaul for five years when the DE surface temperature is less than 48 C When the DE surface temperature exceeds 48 C the disk drives requires no overhaul for five years or 20 000 hours of operation whichever occ...

Page 31: ...tioning error Positioning seek errors that can be recovered by one retry shall occur no more than 10 times in 10 7 seek operations 1 9 Media Defects Defective sectors are replaced with alternates when the disk the MHT Series are formatted prior to shipment from the factory low level format Thus the hosts see a defect free devices Alternate sectors are automatically accessed by the disk drive The u...

Page 32: ...2 Head Unload Standby Immediate command execution 3 Wait Status Checking whether bit 7 of the status register was set to 0 wait to complete STANDBY IMMEDIATE command 4 HDD power supply cutting 1 11Advanced Power Management The disk drive shifts to the three kinds of APM modes automatically under the Idle condition The APM mode can be chosen with a Sector Count register of the SETFEATURES EF comman...

Page 33: ...2 1 2 sec 10 0 40 0 sec N A Mode 2 0 2 1 2 sec 10 0 40 0 sec 10 0 40 0 sec When the maximum time that the HDD is waiting for commands has been exceeded Mode 0 Mode shifts from Active condition to Active Idle in 0 2 1 2 and to Low Power Idle in 15 minutes Mode 1 Mode shifts from Active condition to Active Idle in 0 2 1 2 seconds and to Low power Idle in 10 0 40 0 seconds Mode 2 Mode shifts from Act...

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Page 35: ... 1 CHAPTER 2 Device Configuration 2 1 Device Configuration 2 2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate ...

Page 36: ... a direct drive Sensor less DC motor 4 Actuator The actuator uses a revolving voice coil motor VCM structure which consumes low power and generates very little heat The head assembly at the edge of the actuator arm is controlled and positioned by feedback of the servo information read by the read write head If the power is not on or if the spindle motor is stopped the head assembly stays on the ra...

Page 37: ...ility The high speed microprocessor unit MPU achieves a high performance AT controller 2 2 System Configuration 2 2 1 ATA interface Figures 2 2 and 2 3 show the ATA interface system configuration The drive has a 44pin PC AT interface connector and supports PIO mode 4 transfer at 16 6 MB s Multiword DMA mode 2 transfer at 16 6 MB s and also U DMA mode 5 100 MB s 2 2 2 1 drive connection MHC2032AT M...

Page 38: ... PIO mode 4 or DMA mode 2 U DMA mode 5 occurrence of ringing or crosstalk of the signal lines AT bus between the HA and the disk drive may be a great cause of the obstruction of system reliability Thus it is necessary that the capacitance of the signal lines including the HA and cable does not exceed the ATA 6 standard and the cable length between the HA and the disk drive should be as short as po...

Page 39: ...er Settings This chapter gives the external dimensions installation conditions surface temperature conditions cable connections and switch settings of the hard disk drives For information about handling this hard disk drive and the system installation procedure refer to the following Integration Guide C141 E144 ...

Page 40: ...Installation Conditions 3 2 C141 E192 01EN 3 1 Dimensions Figure 3 1 illustrates the dimensions of the disk drive and positions of the mounting screw holes All dimensions are in mm Figure 3 1 Dimensions ...

Page 41: ...g see the FUJITSU 2 5 INCH HDD INTEGRATION GUIDANCE C141 E144 1 Orientation Figure 3 2 illustrates the allowable orientations for the disk drive a Horizontal 1 b Horizontal 1 c Vertical 1 d Vertical 2 e Vertical 3 f Vertical 4 Figure 3 2 Orientation gravity gravity gravity ...

Page 42: ...5kgf cm When attaching the HDD to the system frame do not allow the system frame to touch parts cover and base other than parts to which the HDD is attached 3 Limitation of mounting Note These dimensions are recommended values if it is not possible to satisfy them contact us Figure 3 3 Mounting frame structure Screw Screw Details of B Details of A 3 0 or less 3 0 or less Frame of system cabinet Fr...

Page 43: ...cause of breather hole mounted to the HDD do not allow this to close during mounting Locating of breather hole is shown as Figure 3 4 For breather hole of Figure 3 4 at least do not allow its around φ 2 4 to block Figure 3 4 Location of breather ...

Page 44: ...ace temperature from exceeding 60 C Provide air circulation in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface temperatures of the DE Regardless of the ambient temperature this surface temperature must meet the standards listed in Table 3 1 Figure 3 5 shows the temperature measurement point Figure 3 5 Surface temperat...

Page 45: ...not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device disconnect the body ground 500 kΩ or greater Do not touch the printed circuit board but hold it by the edges 6 Handling cautions Please keep the following cautions and handle th...

Page 46: ...rque of the screw strictly M3 0 49N m 5 kgf cm Recommended equipments Contents Model Maker Wrist strap JX 1200 3056 8 SUMITOMO 3M ESD ESD mat SKY 8A Color Seiden Mat Achilles Shock Low shock driver SS 6500 HIOS Place the shock absorbing mat on the operation table and place ESD mat on it Use the Wrist strap Do not hit HDD each other Do not stack when carrying Do not place HDD vertically to avoid fa...

Page 47: ... Connections 3 3 1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices Figure 3 8 shows the locations of these connectors and terminals Figure 3 8 Connector locations Connector setting pins PCA ...

Page 48: ... 89361 144 FCI IMPORTANT For the host interface cable use a ribbon cable A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines This is because the interface is designed for ribbon cables and not for cables carrying differential signals 3 3 3 Device connection Figure 3 9 shows how to connect the devices Host system DC Power supply ...

Page 49: ... 3 10 shows the pin assignment of the power supply connector CN1 Figure 3 10 Power supply connector pins CN1 3 4 Jumper Settings 3 4 1 Location of setting jumpers Figure 3 11 shows the location of the jumpers to select drive configuration and functions Figure 3 11 Jumper location ...

Page 50: ...n at the factory Figure 3 12 Factory default setting 3 4 3 Master drive slave drive setting Master drive disk drive 0 or slave drive disk drive 1 is selected b Slave drive a Master drive Open Open Short Open A 1 C B D 2 B D 2 A C 1 Figure 3 13 Jumper setting of master or slave drive Note Pins A and C should be open Open ...

Page 51: ...ion using unique interface cables By connecting the CSEL of the master drive to the CSEL Line conducer of the cable and connecting it to ground further the CSEL is set to low level The drive is identified as a master drive At this time the CSEL of the slave drive does not have a conductor Thus since the slave drive is not connected to the CSEL conductor the CSEL is set to high level The drive is i...

Page 52: ...Installation Conditions 3 14 C141 E192 01EN Figure 3 16 Example 2 of Cable Select 3 4 5 Power Up in Standby setting When pin C is grounded the drive does not spin up at power on drive drive ...

Page 53: ...4 3 Circuit Configuration 4 4 Power on Sequence 4 5 Self calibration 4 6 Read write Circuit 4 7 Servo Control This chapter explains basic design concepts of the disk drive Also this chapter explains subassemblies of the disk drive each sequence servo control and electrical circuit blocks ...

Page 54: ...ins disks with an outer diameter of 65 mm and an inner diameter of 20 mm Servo data is recorded on each cylinder total 150 Servo data written at factory is read out by the read head For servo data see Section 4 7 4 2 2 Spindle The spindle consists of a disk stack assembly and spindle motor The disk stack assembly is activated by the direct drive sensor less DC spindle motor which has a speed of 4 ...

Page 55: ...annel RDC The PreAMP consists of the write current switch circuit that flows the write current to the head coil and the voltage amplifier circuit that amplitudes the read output from the head The RDC is the read demodulation circuit using the Modified Extended Partial Response MEEPR and contains the Viterbi detector programmable filter adaptable transversal filter times base generator data separat...

Page 56: ...4 Controller circuit Major functions are listed below Data buffer management ATA interface control and data transfer control Sector format control Defect management ECC control Error recovery and self diagnosis Figure 4 1 Power Supply Configuration ...

Page 57: ...4 5 MCU HDC RDC Anchor 88i553x Marvell HDC MCU RDC Data Buffer SDRAM Flash ROM FROM SVC TLS2255 Resonator 20MHz R W Pre Amp TLS26B624 Thermistor VCM HEAD SP Motor Media DE PCA ATA Interface Shock Sensor Console Figure 4 2 Circuit Configuration ...

Page 58: ... the spindle motor b The disk drive executes self diagnosis data buffer read write test after enabling response to the ATA bus c After confirming that the spindle motor has reached rated speed the head assembly is loaded on the disk d The disk drive positions the heads onto the SA area and reads out the system information e The disk drive sets up a requirement for execution of self seek calibratio...

Page 59: ... the cylinder where the head is positioned To execute stable fast seek operations external forces are occasionally sensed The firmware of the drive measures and stores the force value of the actuator motor drive current that balances the torque for stopping head stably This includes the current offset in the power amplifier circuit and DAC system Start Self diagnosis 1 MPU bus test Internal regist...

Page 60: ... firmware calculates the loop gain from the position signal and stores the compensation value against to the target gain as ratio For compensating the direction current value to the power amplifier is multiplied by the compensation value By this compensation loop gain becomes constant value and the stable servo control is realized To compensate torque constant value change depending on cylinder wh...

Page 61: ...write circuit consists of the read write preamplifier PreAMP the write circuit the read circuit and the time base generator in the read channel RDC Figure 4 4 is a block diagram of the read write circuit 4 6 1 Read write preamplifier PreAMP PreAMP equips a read preamplifier and a write current switch that sets the bias current to the MR device and the current in writing Each channel is connected t...

Page 62: ...Theory of Device Operation 4 10 C141 E192 01EN Figure 4 4 Read write circuit block diagram ...

Page 63: ... AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer inner head positions 2 Programmable filter circuit The programmable filter circuit has a low pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost up function that equalizes the waveform of the read signal Cut off...

Page 64: ...o the survivor path sequence 6 ENDEC This circuit converts the 34 bit read data into the 32 bit NRZ data 4 6 4 Digital PLL circuit The drive uses constant density recording to increase total capacity This is different from the conventional method of recording data with a fixed data transfer rate at all data area In the constant density recording method data area is divided into zones by radius and...

Page 65: ...vo control circuit Figure 4 6 is the block diagram of the servo control circuit The following describes the functions of the blocks Figure 4 6 Block diagram of servo control circuit 1 Microprocessor unit MPU The MPU executes startup of the spindle motor movement to the reference cylinder seek to the specified cylinder and calibration operations Main internal operation of the MPU are shown below He...

Page 66: ... head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area The logical initial cylinder is at the outermost circumference cylinder 0 c Seek to specified cylinder Drives the VCM to position the head to the specified cylinder d Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator and stores the calibration ...

Page 67: ... processed 3 D A converter DAC The control program calculates the specified data value digital value of the VCM drive current and the value is converted from digital to analog so that an analog output voltage is sent to the power amplifier 4 Power amplifier The power amplifier feeds currents corresponding to the DAC output signal voltage to the VCM 5 Spindle motor control circuit The spindle motor...

Page 68: ...ibed below 1 Inner guard band This area is located inside the user area and the rotational speed of the VCM can be controlled on this cylinder area for head moving 2 Data area This area is used as the user data area SA area 3 Outer guard band This area is located at outer position of the user data area and the rotational speed of the spindle can be controlled on this cylinder area for head moving ...

Page 69: ... W R Recovery Servo Mark Gray Code W R Recovery Servo Mark Gray Code Erase Servo A Erase Servo A Servo B Erase Servo B Erase Servo C Erase Servo C Erase Servo D Erase PAD CYLn 1 CYLn CYLn 1 n even number Diameter direction Circumference Direction Erase DC erase area OGB Data area IGB expand Servo frame 150 servo frames per revolution ...

Page 70: ...rated from the gray code and servo A to D This servo information is used for positioning operation of radius direction and position detection of circumstance direction The servo frame consists of 6 blocks write read recovery servo mark gray code servo A to D and PAD Figure 4 8 shows the servo frame format Figure 4 8 Servo frame format ...

Page 71: ...fetches the position sense data on the servo frame at a constant interval of sampling time executes calculation and updates the VCM drive current The servo control of the actuator includes the operation to move the head to the reference cylinder the seek operation to move the head to the target cylinder to read or write data and the track following operation to position the head onto the target tr...

Page 72: ...tally controlled by the firmware 4 7 5 Spindle motor control Hall less three phase twelve pole motor is used for the spindle motor and the 3 phase full half wave analog current control circuit is used as the spindle motor driver called SVC hereafter The firmware operates on the MPU manufactured by Fujitsu The spindle motor is controlled by sending several signals from the MPU to the SVC There are ...

Page 73: ...SVC enters the stable rotation mode 3 Stable rotation mode The SVC calculates a time for one revolution of the spindle motor based on the PHASE signal The MPU takes a difference between the current time and a time for one revolution at 4 200 rpm that the MPU already recognized Then the MPU keeps the rotational speed to 4 200 rpm by charging or discharging the charge pump for the different time For...

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Page 75: ...PTER 5 Interface 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Ultra DMA Feature Set 5 6 Timing This chapter gives details about the interface and the interface commands and timings ...

Page 76: ... DMA REQUEST INTRO INTERRUPT REQUEST DIOW I O WRITE STOP STOP DURING ULTRA DMA DATA BURSTS DA 0 2 DEVICE ADDRESS CS0 CHIP SELECT 0 CS1 CHIP SELECT 1 RESET RESET CSEL CABLE SELECT MSTR Master ENCSEL ENABLE CSEL GND GROUND DIOR I O READ HDMARDY DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE DATA STROBE DURING ULTRA DMA DATA OUT BURST 5V DC 5 volt Host IORDY I O READY DDMARDY DMA READY DURING ULTR...

Page 77: ...9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 MSTR PUS KEY RESET DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND DMARQ DIOW STOP DIOR HDMRDY HSTROBE IORDY DDMARDY DSTROBE DMACK INTRQ DA1 DA0 CS0 DASP 5 VDC GND B D F 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 MSTR ENCSEL ENCSEL KEY GND DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 KEY GND GND GND CSEL GND reser...

Page 78: ...ertion of the STOP signal asserted by the host later indicates that the transfer has been suspended DIOR I Read strobe signal from the host to read the device register or data port HDMARDY I Flow control signal for Ultra DMA data In transfer READ DMA command This signal is asserted by the host to inform the device that the host is ready to receive the Ultra DMA data In transfer The host can negate...

Page 79: ...nd a slave device is present This signal is pulled up to 5 V through 10 kΩ resistor at each device IORDY O This signal requests the host system to delay the transfer cycle when the device is not ready to respond to a data transfer request from the host system DDMARDY O Flow control signal for Ultra DMA data Out transfer WRITE DMA command This signal is asserted by the device to inform the host tha...

Page 80: ...nal from the host to the device O indicates output signal from the device to the host I O indicates common output or bi directional signal between the host and the device 5 2 Logical Interface The device can operate for command execution in either address specified mode cylinder head sector CHS or Logical block address LBA mode The IDENTIFY DEVICE information indicates whether the device supports ...

Page 81: ...gh X 1F5 L H H H L Device Head Device Head X 1F6 L H H H H Status Command X 1F7 L L X X X Invalid Invalid Control block registers H L H H L Alternate Status Device Control X 3F6 H L H H H X 3F7 Notes 1 The Data register for read or write operation can be accessed by 16 bit data bus DATA0 to DATA15 2 The registers for read or write operation other than the Data registers can be accessed by 8 bit da...

Page 82: ...tes the status of the command executed by the device The contents of this register are valid when the ERR bit of the Status register is 1 This register contains a diagnostic code after power is turned on a reset or the EXECUTIVE DEVICE DIAGNOSTIC command is executed Status at the completion of command execution other than diagnostic command Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICRC UNC ...

Page 83: ... feature to a command For instance it is used with SET FEATURES command to enable or disable caching 4 Sector Count register X 1F2 The Sector Count register indicates the number of sectors of data to be transferred in a read or write operation between the host system and the device When the value in this register is X 00 the sector count is 256 With the EXT system command the sector count is 65536...

Page 84: ...ss At the end of a command the contents of this register are updated to the current cylinder number Under the LBA mode this register indicates LBA bits 15 to 8 Under the LBA mode of the EXT system command LBA bits 39 to 32 are set in the first setting and LBA bits 15 to 8 are set in the second setting 7 Cylinder High register X 1F5 The contents of this register indicates high order 8 bits of the d...

Page 85: ...ode of the EXT command Bit 1 HS1 CHS mode head address 1 2 1 bit 25 for LBA mode Unused under the LBA mode of the EXT command Bit 0 HS0 CHS mode head address 0 2 0 bit 24 for LBA mode Unused under the LBA mode of the EXT command 9 Status register X 1F7 The contents of this register indicate the status of the device The contents of this register are updated at the completion of each command When th...

Page 86: ...WRITE SECTOR S or WRITE BUFFER command Within 5 µs following transfer of 512 bytes of data and the appropriate number of ECC bytes during execution of READ LONG or WRITE LONG command Bit 6 Device Ready DRDY bit This bit indicates that the device is capable to respond to a command The IDD checks its status when it receives a command If an error is detected not ready state the IDD clears this bit to...

Page 87: ...mediately Table 5 3 lists the executable commands and their command codes This table also lists the necessary parameters for each command which are written to certain registers before the Command register is written 5 2 3 Control block registers 1 Alternate Status register X 3F6 The Alternate Status register contains the same information as the Status register of the command block register The onl...

Page 88: ...he DASP handshake Bit 1 nIEN bit enables an interrupt INTRQ signal from the device to the host When this bit is 0 and the device is selected an interruption INTRQ signal can be enabled through a tri state buffer When this bit is 1 or the device is not selected the INTRQ signal is in the high impedance state 5 3 Host Commands The host system issues a command to the device by writing necessary param...

Page 89: ... 0 0 1 1 0 0 0 R N Y Y Y Y RECALIBRATE 0 0 0 1 X X X X N N N N D SEEK 0 1 1 1 X X X X N N Y Y Y INITIALIZE DEVICE PARAMETERS 1 0 0 1 0 0 0 1 N Y N N Y IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D IDENTIFY DEVICE DMA 1 1 1 0 1 1 0 0 N N N N D SET FEATURES 1 1 1 0 1 1 1 1 Y N N N D SET MULTIPLE MODE 1 1 0 0 0 1 1 0 N Y N N D SET MAX 1 1 1 1 1 0 0 1 N Y Y Y Y READ NATIVE MAX ADDRESS 1 1 1 1 1 0 0 0 N N ...

Page 90: ... PREPARE 1 1 1 1 0 0 1 1 N N N N D SECURITY ERASE UNIT 1 1 1 1 0 1 0 0 N N N N D SECURITY FREEZE LOCK 1 1 1 1 0 1 0 1 N N N N D SECURITY SET PASSWORD 1 1 1 1 0 0 0 1 N N N N D SECURITY UNLOCK 1 1 1 1 0 0 1 0 N N N N D FLUSH CACHE 1 1 1 0 0 1 1 1 N N N N D DEVICE CONFIGURATION 1 0 1 1 0 0 0 1 N N N N D SET MAX ADDRESS 1 1 1 1 1 0 0 1 N Y Y Y Y SET MAX SET PASSWORD 1 1 1 1 1 0 0 1 Y N N N Y SET MAX ...

Page 91: ... 1 1 0 1 0 1 N Y Y Y D READ DMA EXT O 0 0 1 0 0 1 0 1 N Y Y Y D WRITE MULTIPLE EXT O 0 0 1 1 1 0 0 1 N Y Y Y D READ MULTIPLE EXT O 0 0 1 0 1 0 0 1 N Y Y Y D WRITE SECTOR S EXT O 0 0 1 1 0 1 0 0 N Y Y Y D READ SECTOR S EXT O 0 0 1 0 0 1 0 0 N Y Y Y D DOWNLOAD MICRO CODE 1 0 0 1 0 0 1 0 Y Y Y N D Notes FR Features Register CY Cylinder Registers SC Sector Count Register DH Drive Head Register SN Sect...

Page 92: ...own as following in this subsection Example READ SECTOR S At command issuance I O registers setting contents Bit 7 6 5 4 3 2 1 0 1F7H CM 0 0 1 0 0 0 0 0 1F6H DH x L x DV Head No LBA MSB 1F5H CH Start cylinder address MSB LBA 1F4H CL Start cylinder address LSB LBA 1F3H SN Start sector No LBA LSB 1F2H SC Transfer sector count 1F1H FR xx At command completion I O registers contents to be read Bit 7 6...

Page 93: ...r Number registers Number of sectors can be specified from 1 to 256 sectors To specify 256 sectors reading 00 is specified For the DRQ INTRQ and BSY protocols related to data transfer see Subsection 5 4 1 If the head is not on the track specified by the host the device performs an implied seek After the head reaches to the specified track the device reads the target sector If an error occurs retry...

Page 94: ...tors of which data was not transferred is set in this register 2 READ MULTIPLE X C4 The READ MULTIPLE Command performs the same as the READ SECTOR S Command except that when the device is ready to transfer data for a block of sectors and enters the interrupt pending state only before the data transfer for the first sector of the block sectors In the READ MULTIPLE command operation the DRQ bit of t...

Page 95: ... an ABORTED COMMAND error Figure 5 2 shows an example of the execution of the READ MULTIPLE command Block count specified by SET MULTIPLE MODE command 4 number of sectors in a block READ MULTIPLE command specifies Number of requested sectors 9 Sector Count register 9 Figure 5 2 Execution example of READ MULTIPLE command At command issuance I O registers setting contents 1F7H CM 1 1 0 0 0 1 0 0 1F6...

Page 96: ... status as the result of command execution only once at completion of the data transfer When an error such as an unrecoverable medium error that the command execution cannot be continued is detected the data transfer is stopped without transferring data of sectors after the erred sector The device generates an interrupt using the INTRQ signal and posts a status to the host system The format of the...

Page 97: ...s not transferred is set in this register 4 READ VERIFY SECTOR S X 40 or X 41 This command operates similarly to the READ SECTOR S command except that the data is not transferred to the host system After all requested sectors are verified the device clears the BSY bit of the Status register and generates an interrupt Upon the completion of the command execution the command block registers contain ...

Page 98: ...address specified in the Device Head Cylinder High Cylinder Low and Sector Number registers to the address specified in the Sector Count register Number of sectors can be specified from 1 to 256 sectors A sector count of 0 requests 256 sectors Data transfer begins at the sector specified in the Sector Number register For the DRQ INTRQ and BSY protocols related to data transfer see Subsection 5 4 2...

Page 99: ...nts 1F7H CM 0 0 1 1 0 0 0 R 1F6H DH x L x DV StartheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x L x DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder...

Page 100: ...f sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the WRITE MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when WRITE MULTIPLE command is disabled the device rejects the WRITE MULTIPLE command with an ABORTED COMMAND error Disk errors encountered during execution of the WRITE MULTIPLE command are posted after...

Page 101: ... SECTOR S command except for following events The data transfer starts at the timing of DMARQ signal assertion The device controls the assertion or negation timing of the DMARQ signal The device posts a status as the result of command execution only once at completion of the data transfer or completion of processing in the device The device posts a status as the result of command execution only on...

Page 102: ...rmation 1F6H DH x L x DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 8 WRITE VERIFY X 3C This command operates similarly to the WRITE SECTOR S command excep...

Page 103: ...B 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 9 RECALIBRATE X 10 to X 1F This command performs the calibration Upon receipt of this command the device sets BSY bit of the Sta...

Page 104: ... CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information Note Also executable in LBA mode 10 SEEK X 70 to X 7F This command performs a seek operation to the track and selects the head specified in the command block registers After completing the seek operation the device clears the BSY bit in the Status register and generates an interrupt In the LBA mode this command performs the seek operation t...

Page 105: ...X 91 The host system can set the number of sectors per track and the maximum head number maximum head number is number of heads minus 1 per cylinder with this command Upon receipt of this command the device sets the BSY bit of Status register and saves the parameters Then the device clears the BSY bit and generates an interrupt When the SC register is specified to X 00 an ABORTED COMMAND error is ...

Page 106: ...VICE X EC The host system issues the IDENTIFY DEVICE command to read parameter information from the device Upon receipt of this command the drive sets the BSY bit to one prepares to transfer the 256 words of device identification data to the host sets the DRQ bit to one clears the BSY bit to zero and generates an interrupt After that the host system reads the information out of the sector buffer T...

Page 107: ...ommand is not used to transfer data to the host in DMA mode this command functions in the same way as the Identify Device command At command issuance I O registers setting contents 1F7H CM 1 1 1 0 1 1 1 0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1...

Page 108: ...ters left 27 46 Set by a device Model name ASCII code 40 characters left 47 X 8010 Maximum number of sectors per interrupt on READ WRITE MULTIPLE command 48 X 0000 Reserved 49 X 2B00 Capabilities 4 50 X 400x Capabilities 5 51 X 0200 PIO data transfer mode 6 52 X 0200 Reserved 53 X 0007 Enable disable setting of words 54 58 and 64 70 88 7 54 Variable Number of current Cylinders 55 Variable Number o...

Page 109: ...f command sets function 16 87 17 Default of command sets function 17 88 X xx3F Ultra DMA transfer mode 18 89 Set by a device Security Erase Unit execution time 1 LSB 2 min 19 90 X 0000 Enhanced Security Erase Unit execution time 1 LSB 2 min 91 Variable Advance power management level 92 Variable Master password revision 93 20 Hardware configuration 20 94 Variable Acoustic Management level 21 95 99 ...

Page 110: ...he power on sequence in order to spin up The Identify information is incomplete 738Ch The device requires the SET FEATURES sub command after the power on sequence in order to spin up The Identify information is incomplete 8C73h The device requires the SET FEATURES sub command after the power on sequence in order to spin up The Identify information is incomplete C837h The device requires the SET FE...

Page 111: ... Word 59 Transfer sector count currently set by READ WRITE MULTIPLE command Bit 15 9 Reserved Bit 8 1 Enable the multiple sector transfer Bit 7 0 Transfer sector count currently set by READ WRITE MULTIPLE command without interrupt supports 2 4 8 and 16 sectors 9 Word 63 Multiword DMA transfer mode Bit 15 11 Reserved Bit 10 1 multiword DMA mode 2 is selected Bit 9 1 multiword DMA mode 1 is selected...

Page 112: ...AD BUFFER command Bit 12 1 Supports the WRITE BUFFER command Bit 11 Undefined Bit 10 1 Supports the Host Protected Area feature set Bit 9 1 Supports the DEVICE RESET command Bit 8 1 Supports the SERVICE interrupt Bit 7 1 Supports the release interrupt Bit 6 1 Supports the read cache function Bit 5 1 Supports the write cache function Bit 4 1 Supports the PACKET command feature set Bit 3 1 Supports ...

Page 113: ...and Bit 5 1 Supports the Power Up In Standby set Bit 4 1 Supports the Removable Media Status Notification feature set Bit 3 1 Supports the Advanced Power Management feature set Bit 2 1 Supports the CFA Compact Flash Association feature set Bit 1 1 Supports the READ WRITE DMA QUEUED command Bit 0 1 Supports the DOWNLOAD MICROCODE command Option customizing 14 WORD 84 Bit 15 0 Bit 14 1 Bit 13 2 Rese...

Page 114: ... 2 1 Supports the Removable Media function Bit 1 1 From the SECURITY SET PASSWORD command Bit 0 1 From the SMART ENABLE OPERATION command 16 WORD 86 Bits 15 Reserved Bit 13 10 Same definition as WORD 83 Bit 9 1 Enables the Automatic Acoustic Management function From the SET FEATURES command Bit 8 1 From the SET MAX SET PASSWORD command Bits 7 6 Same definition as WORD 83 Bit 5 1 Enables the Power ...

Page 115: ...Bit 3 1 Supports the Mode 3 Bit 2 1 Supports the Mode 2 Bit 1 1 Supports the Mode 1 Bit 0 1 Supports the Mode 0 19 WORD 89 MHT2080AT X 30 96 minutes MHT2060AT X 24 72 minutes MHT2040AT X 18 48 minutes MHT2030AT X 12 36 minutes MHT2020AT X 0C 24 minutes 20 WORD 93 Bits 15 0 Bit 14 1 Bit 13 1 CBLID is a higher level than VIH 80 conductor cable 0 CBLID is a lower level than VIL 40 conductor cable Bit...

Page 116: ...as not detected in the self diagnosis Bit 2 1 Method for deciding the device No of Device 0 00 Reserved 01 Using a jumper 10 Using the CSEL signal 11 Other method Bit 0 1 In the case of device 0 21 WORD 94 Bit 15 8 X FE Recommended acoustic management value Bit 7 0 X XX Current set value FE C0 Performance mode BF 80 Acoustic mode 00 Acoustic management is unused it It is same as FE CO 22 WORD 100 ...

Page 117: ...ers in the Features register for the purpose of changing the device features to be executed Upon receipt of this command the device sets the BSY bit of the Status register and saves the parameters in the Features register Then the device clears the BSY bit and generates an interrupt If the value in the Features register is not supported or it is invalid the device posts an ABORTED COMMAND error Ta...

Page 118: ...nction X 85 Set the advanced power management mode to the default mode X AA Enables the read cache function X BB Specifies the transfer of 4 byte ECC for READ LONG and WRITE LONG commands 1 X C2 Disables the Acoustic management function X CC Enables the reverting to power on default settings after software reset 1 1 Although there is a response to the command nothing is done At power on or after h...

Page 119: ...de The host sets X 03 to the Features register By issuing this command with setting a value to the Sector Count register the transfer mode can be selected Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value The IDD supports following values in the Sector Count register value If other value than below is specified an ABORTED COMMAND e...

Page 120: ...e up to the specified APM level when the drive does not receive any commands for a specific time The sequence in which the power management level shifts is from Active Idle to Low Power Idle to Standby The Mode 2 level requires the longest shifting time depending on the APM level settings The settings of the APM level revert to their default values when power on or a hardware or software reset occ...

Page 121: ... WRITE MULTIPLE commands The block count number of sectors in a block for these commands are also specified by the SET MULTIPLE MODE command The number of sectors per block is written into the Sector Count register The IDD supports 2 4 8 16 and 32 sectors as the block counts Upon receipt of this command the device sets the BSY bit of the Status register and checks the contents of the Sector Count ...

Page 122: ...d WRITE MULTIPLE command operation are disabled as the default mode At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx Sector count block Error information 16 SET MAX F9 SET MAX Features Register Values Value Command 00h Obsolete 01h SET MAX SET PASSWORD 02h SET MAX LOCK 03h SET MAX UNLOCK 04h SET ...

Page 123: ...s 0 the value set by this command becomes invalid when the power is turned on or a hard reset occurs and the maximum address returns to the value most lately set when VV bit 1 The value by VV bit 0 is held in case that this command with VV bit 1 has not been issued or had set the default value and hard reset occurs After power on and the occurrence of a hard reset the host can issue this command o...

Page 124: ...mand requests a transfer of 1 sector of data from the host and defines the contents of SET MAX password The password is retained by the device until the next power cycle The READ NATIVE MAX ADDRESS command is not executed just before this command The command is the SET MAX ADDRESS command if it is the command just after the READ NATIVE MAX ADDRESS command is executed At command issuance I O regist...

Page 125: ...d sets the device into SET_MAX_LOCK state After this command is completed any other SET MAX commands except SET MAX UNLOCK and SET MAX FREEZE LOCK commands are rejected And the device returns command aborted The device remains in the SET MAX LOCK state until a power cycle or the acceptance of SET MAX UNLOCK or SET MAX FREEZE LOCK command The READ NATIVE MAX ADDRESS command is not executed just bef...

Page 126: ... data transferred shall be compared with the stored password If the password compare fails the device returns command aborted and decrements the Unlock counter and remains in the Set Max Lock state On the acceptance of the SET MAX LOCK command the Unlock counter is set to a value of five When this counter reaches zero then SET MAX UNLOCK command returns command aborted until a power cycle If the p...

Page 127: ...EZE LOCK command sets the device to SET_MAX_Frozen state After the device made a transition to the Set Max Freeze Lock state the following SET MAX commands are rejected then the device returns command aborted SET MAX ADDRESS SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK If the Device is in the SET_MAX_UNLOCK state with the SET MAX FREEZE LOCK command then the device returns command aborted The ...

Page 128: ...C xx xx xx xx xx 1F1H ER Error information 17 READ NATIVE MAX ADDRESS F8 This command posts the maximum address intrinsic to the device which can be set by the SET MAX ADDRESS command Upon receipt of this command the device sets the BSY bit and indicates the maximum address in the DH CH CL and SN registers Then it clears BSY and generates an interrupt At command issuance I O registers setting cont...

Page 129: ...evice 1 asserts the PDIAG signal If the device 1 does not assert the PDIAG signal but indicates an error the device 0 shall append X 80 to its own diagnostic status The device 0 clears the BSY bit of the Status register and generates an interrupt The device 1 does not generate an interrupt A diagnostic status of the device 0 is read by the host system When a diagnostic failure of the device 1 is d...

Page 130: ...rmal Failure of device 1 attention The device responds to this command with the result of power on diagnostic test At command issuance I O registers setting contents 1F7H CM 1 0 0 1 0 0 0 0 1F6H DH x x x DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV Head No LBA MSB 1F5H C...

Page 131: ...upports only single sector operation Number of ECC bytes to be transferred is fixed to 4 bytes and cannot be changed by the SET FEATURES command At command issuance I O registers setting contents 1F7H CM 0 0 1 0 0 0 1 R 1F6H DH x L x DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Cylinder No MSB LBA Cylinder No LSB LBA Sector No LBA LSB 01 xx R Retry At command completion I O registers...

Page 132: ...conditions READ LONG issued WRITE LONG Same address issues sequence After READ LONG is issued WRITE LONG can be issued consecutively If above condition is not satisfied the WRITE LONG Data becomes the Uncorrectable error for subsequence READ command At command issuance I O registers setting contents 1F7H CM 0 0 1 1 0 0 1 R 1F6H DH x L x DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Cy...

Page 133: ...ice sets the DRQ bit of Status register clears the BSY bit and generates an interrupt After that the host system can read up to 512 bytes of data from the buffer At command issuance I O registers setting contents 1F7H CM 1 1 1 1 0 1 0 0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H ...

Page 134: ...clears the BSY bit when the device is ready to receive the data After that 512 bytes of data is transferred from the host and the device writes the data to the buffer then generates an interrupt At command issuance I O registers setting contents 1F7H CM 1 1 1 1 1 0 0 0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read...

Page 135: ... timer allows the device to change to the standby mode automatically after specified period When the device enters the idle mode the timer starts countdown If any command is not issued while the timer is counting down the device automatically enters the standby mode If any command is issued while the timer is counting down the timer is initialized and the command is executed The timer restarts cou...

Page 136: ... bit of the Status register and enters the idle mode Then the device clears the BSY bit and generates an interrupt This command does not support the APS timer function At command issuance I O registers setting contents 1F7H CM X 95 or X E1 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F...

Page 137: ...le mode If the device has not received any command during specified period then the device enters standby mode automatically Under the standby mode the spindle motor is stopped Thus when the command involving a seek such as READ SECTOR s command is received the device processes the command after driving the spindle motor At command issuance I O registers setting contents 1F7H CM X 96 or X E2 1F6H ...

Page 138: ... bit and generates an interrupt This command does not support the APS timer function At command issuance I O registers setting contents 1F7H CM X 94 or X E0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error informa...

Page 139: ...d the sleep mode In the sleep mode the spindle motor is stopped and the ATA interface section is inactive All I O register outputs are in high impedance state The only way to release the device from sleep mode is to execute a software or hardware reset At command issuance I O registers setting contents 1F7H CM X 99 or X E6 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx ...

Page 140: ...hat the device clears the BSY bit and generates an interrupt Power save mode Sector Count register During moving to standby mode Standby mode X 00 Idle mode X FF Active mode X FF At command issuance I O registers setting contents 1F7H CM X 98 or X E5 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status inf...

Page 141: ...rs 4Fh in the CL register and C2h in the CH register If the key values are incorrect the Aborted Command error is issued If the failure prediction function is disabled the device returns the Aborted Command error to subcommands other than those of the SMART Enable Operations with the FR register set to D8h If the failure prediction function is enabled the device collects and updates data on specif...

Page 142: ...e than 15 minutes has elapsed since the last time that attributes were saved then the attributes are saved However if the automatic attribute save function is disabled the attributes are not saved Upon receiving this subcommand a device asserts BSY enables or disables the automatic attribute save function and clears BSY X D3 SMART Save Attribute Values When the device receives this subcommand it a...

Page 143: ...ector A device which receives this sub command asserts the BSY bit and when it has prepared to receive data from the host computer it sets DRQ and clears the BSY bit Next it receives data from the host computer and writes the specified log sector in the SN register SN SC Log sector 09h 01h SMART selective self test log 80h 9Fh 01h 10h Host vendor log The host can write any desired data in the host...

Page 144: ...ssed since the power was switched on or since the last time that off line data were collected off line data collection is performed without relation to any command from the host computer The host must regularly issue the SMART Read Attribute Values subcommand FR register D0h SMART Save Attribute Values subcommand FR register D3h or SMART Return Status subcommand FR register DAh to save the device ...

Page 145: ...4Fh F4h xx xx Error information The attribute value information is 512 byte data the format of this data is shown the following Table 5 8 The host can access this data using the SMART Read Attribute Values subcommand FR register D0h The insurance failure threshold value data is 512 byte data the format of this data is shown the following Table 5 9 The host can access this data using the SMART Read...

Page 146: ...d 16F Off line data collection capability 170 171 Trouble prediction capability flag 172 Error logging capability 173 Self test error detection point 174 Simple self test Quick Test execution time min 175 Comprehensive self test Comprehensive Test execution time min 176 Conveyance self test execution time min 177 to 181 Reserved 182 to 1FE Vendor unique 1FF Check sum Table 5 9 Format of insurance ...

Page 147: ...te ID The attribute ID is defined as follows Attribute ID Attribute name 0 Indicates unused attribute data 1 Read Error Rate 2 Throughput Performance 3 Spin Up Time 4 Start Stop Count 5 Reallocated Sector Count 7 Seek Error Rate 8 Seek Time Performance 9 Power On Hours Count 10 Spin Retry Count 12 Drive Power Cycle Count 192 Emergency Retract Cycle Count 193 Load Unload Cycle Count 194 HDA Tempera...

Page 148: ...aved even if the drive fault prediction function is disabled 6 to 15 Reserve bit Current attribute value It indicates the normalized value of the original attribute value The value deviates in a range of 01h to 64h range of 01h to C8h for the ultra ATA CRC error rate It indicates that the closer the value is to 01h the higher the possibility of a failure The host compares the attribute value with ...

Page 149: ...xecution status Bit Meaning 0 to 3 Remainder of the self test is indicated as a percentage in a range of 0h to 9h corresponding to 0 to 90 4 to 7 Self test execution status 0h Self test has ended successfully or self test has not been executed 1h Self test is suspended by the host 2h Self test is interrupted by a soft hard reset from the host 3h Self test cannot be executed 4h Self test has ended ...

Page 150: ...his bit is 1 it indicates that the SMART Self test function is supported 5 If this bit is 1 it indicates that the SMART Conveyance Self test is supported 6 If this bit is 1 it indicates that the SMART Selective Self test is supported 7 Reserved bits Failure prediction capability flag Bit Meaning 0 If this bit is 1 it indicates that the attribute value is saved on media before the drive enters the ...

Page 151: ...0h Reserved 102 13F Address 81h Address 9Fh 102 and 13F are both the same format as 100 101 140 1FF Reserved SMART error logging If the device detects an unrecoverable error during execution of a command received from the host the device registers the error information in the SMART Summary Error Log see Table 5 11 and the SMART Comprehensive Error Log see Table 5 11 1 and saves the information on ...

Page 152: ...to 3D Command data structure Elapsed time after the power on sequence unit ms 3E Reserved 3F Error register value 40 Sector Count register value 41 Sector Number register value 42 Cylinder Low register value 43 Cylinder High register value 44 Drive Head register value 45 Status register value 46 to 58 Vendor unique 59 State 5A 5B Error log data structure Error data structure Power on time unit h 5...

Page 153: ...ng table Bits 4 to 7 Vendor unique Status Meaning 0 Unclear status 1 Sleep status 2 Standby status 3 Active status BSY bit 0 4 Off line data collection being executed 5 to F Reserved Table 5 11 1 Data format of SMART Comprehensive Error Log Byte First sector Next sector 00h SMART Error Logging 01h Reserved 01h Index Pointer Latest Error Data Structure Reserved 02h 5Bh 1 st Error Log Data Structure...

Page 154: ... Self test log 1 Self test number SN Register Value 03 Self test execution status 04 05 Life time Total power on time hours 06 Self test error No 07 to 0A Error LBA 0B to 19 Vendor unique 1A to 1F9 Self test log 2 to 21 Each log data format is the same as that in byte 02 to 19 1FA 1FB Vendor unique 1FC Self test index 1FD 1FE Reserved 1FF Check sum Self test number Indicates the type of self test ...

Page 155: ...rrent LBA under test 00h 00h 1F4h 1F5h Current Span under test 00h 00h 1F6h 1F7h Feature Flags 00h 00h 1F8h Offline Execution Flag 00h 1F9h Selective Offline Scan Number 00h 1FAh 1FBh Vender Unique Reserved 00h 00h 1FCh 1FDh Selective Self test pending time min 00h 00h 1FEh 1FFh Checksum 00h FFh Test Span Selective self test log provides for the definition of up to five test spans If the starting ...

Page 156: ...ing bit is set 30 SECURITY DISABLE PASSWORD F6h This command invalidates the user password already set and releases the lock function The host transfers the 512 byte data shown in Table 5 15 to the device The device compares the user password or master password in the transferred data with the user password or master password already set and releases the lock function if the passwords are the same...

Page 157: ...passwords Bits 1 to 15 Reserved 1 to 16 Password 32 bytes 17 to 255 Reserved At command issuance I O register contents 1F7h CM 1 1 1 1 0 1 1 0 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h FR xx xx xx xx xx At command completion I O register contents 1F7h ST Status information 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information ...

Page 158: ...5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h FR xx xx xx xx xx At command completion I O register contents 1F7h ST Status information 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information 32 SECURITY ERASE UNIT F4h This command erases all user data This command also invalidates the user password and releases the lock function The host transfers the 512 byte data shown in ...

Page 159: ...e Aborted Command error At command issuance I O register contents 1F7h CM 1 1 1 1 0 1 0 0 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h FR xx xx xx xx xx At command completion I O register contents 1F7h ST Status information 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information 33 SECURITY FREEZE LOCK F5h This command puts the device into FROZEN MODE ...

Page 160: ...r The following medium access commands return the Aborted Command error when the device is in LOCKED MODE READ DMA EXT READ LONG READ MULTIPLE EXT READ SECTORS READ VERIFY SECTORS WRITE DMA EXT WRITE LONG WRITE MULTIPLE EXT WRITE SECTORS EXT WRITE VERIFY SECURITY DISABLE PASSWORD SECURITY FREEZE LOCK SECURITY SET PASSWORD SET MAX ADDRESS EXT FLUSH CACHE EXT DCO RESTORE DCO SET SET MAX ADDRESS EXT ...

Page 161: ...e 5 16 to the device The device determines the operation of the lock function according to the specifications of the Identifier bit and Security level bit in the transferred data Table 5 17 Issuing this command in LOCKED MODE or FROZEN MODE returns the Aborted Command error Table 5 16 Contents of SECURITY SET PASSWORD data Word Contents 0 Control word Bit 0 Identifier 0 Sets a user password 1 Sets...

Page 162: ...ion is not enabled User Maximum The specified password is saved as a new user password The lock function is enabled after the device is turned off and then on LOCKED MODE can be canceled using the user password only The master password already set cannot cancel LOCKED MODE Master Maximum The specified password is saved as a new master password The lock function is not enabled At command issuance I...

Page 163: ...user password is selected The password is compared with the user password already set If the passwords are the same LOCKED MODE is canceled Otherwise the Aborted Command error is returned If the password comparison fails the device decrements the UNLOCK counter The UNLOCK counter initially has a value of five When the value of the UNLOCK counter reaches zero this command or the SECURITY ERASE UNIT...

Page 164: ...error recovery so that the data are read correctly When executing this command the reading of the data may take several seconds if much data are to be read In case a non recoverable error has occurred while the data is being read the error generation address is put into the command block register before ending the command This error sector is deleted from the write cache data and the remaining cac...

Page 165: ...y the value placed in the Features register The following table shows these Features register values If this command sets with the reserved value of Features register an aborted error is posted FR values Command C0h DEVICE CONFIGURATION RESTORE C1h DEVICE CONFIGURATION FREEZE C2h DEVICE CONFIGURATION IDENTIFY C3h DEVICE CONFIGURATION SET 00h BFh C4h FFh Reserved At command issuance I O register co...

Page 166: ...power down or reset If a Host Protected Area has been set by a SET MAX ADDRESS EXT command or if DEVICE CONFIGURATION FREEZE LOCK is set an aborted error is posted DEVICE CONFIGURATION FREEZE LOCK FR C1h The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the Device Configuration Overlay settings After successful execution of a DEVICE CONFIGURATION FREEZE LOCK command ...

Page 167: ...the limitation of the function by the DEVICE CONFIGURATION SET command is reflected in IDENTIFY information When the bits in these words are cleared the device no longer supports the indicated command mode or feature set If a bit is set in the overlay transmitted by the device that is not set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit After...

Page 168: ...0 1 Ultra DMA mode 0 is supported 3 6 Maximum LBA address Reflected in IDENTIFY information WORD60 61 WORD100 103 7 X 00CF X 01CF Command set feature set supported Reflected in IDENTIFY information WORD82 87 Bit 15 9 Reserved Bit 8 1 48 bit Addressing feature set supported Bit 7 1 Host Protected Area feature set supported Bit 6 1 Automatic acoustic management supported Bit 5 1 READ WRITE DMA QUEUE...

Page 169: ...issuance I O registers setting contents 1F7h CM 0 0 0 1 0 1 1 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C xx xx xx xx xx xx xx xx xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1F5h CH 1 1F5h CH 0 1F4h CL 1 1F4h CL 0 1F3h SN 1 1F3h SN 0 1F...

Page 170: ...the VV bit is 1 the highest address value is defined as the last value specified If the VV bit is not set to 1 the highest address is the default value After a power on reset is performed a host can issue the SET MAX ADDRESS EXT command only once if the VV bit is 1 If the SET MAX ADDRESS EXT command is issued twice or more an ID Not Found error occurs When the SET MAX ADDRESS EXT command is execut...

Page 171: ...At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1F5h CH 1 1F5h CH 0 1F4h CL 1 1F4h CL 0 1F3h SN 1 1F3h SN 0 1F2h SC 1 1F2h SC 0 1F1h ER SET MAX LBA 47 40 SET MAX LBA 23 16 SET MAX LBA 39 32 SET MAX LBA 15 8 SET MAX LBA 31 24 SET MAX LBA 7 0 xx xx Error information 0 HOB 0 1 HOB 1 40 FLUSH CACHE EXT EAH Option customizing Description This comma...

Page 172: ...L C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C xx xx xx xx xx xx xx xx xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1 DV xx 1F5h CH 1 1F5h CH 0 1F4h CL 1 1F4h CL 0 1F3h SN 1 1F3h SN 0 1F2h SC 1 1F2h SC 0 1F1h ER xx xx xx xx xx xx xx xx Error information 0 HOB 0 1 HOB 1 ...

Page 173: ...mmand issuance I O registers setting contents 1F7h CM 0 0 1 1 0 1 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH ...

Page 174: ... issuance I O registers setting contents 1F7h CM 0 0 1 0 0 1 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h DH 1 L 1...

Page 175: ...nd At command issuance I O registers setting contents 1F7h CM 0 0 1 1 1 0 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information ...

Page 176: ... command issuance I O registers setting contents 1F7h CM 0 0 1 1 1 0 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h ...

Page 177: ...nd At command issuance I O registers setting contents 1F7h CM 0 0 1 1 1 0 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information ...

Page 178: ... command issuance I O registers setting contents 1F7h CM 0 0 1 0 0 1 0 1 1F6h DH 1 L 1 DV xx 1F5h CH P 1F5h CH C 1F4h CL P 1F4h CL C 1F3h SN P 1F3h SN C 1F2h SC P 1F2h SC C 1F1h FR P 1F1h FR C LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx C Current P Previous At command completion I O registers contents to be read 1F7h ST Status information 1F6h ...

Page 179: ...XX 1F2h SC XX 1F1h ER Error information This command rewrites the microcode of the device firmware When this command is accepted the device does beginning the data transfer of the microcode or the microcode rewriting according to Subcommand code Rewriting is also possible simultaneously with the data transfer Refer to Table 5 19 In the data transfer of Subcommand code 01h transfer by which data is...

Page 180: ...of microcode Transfer example 1 1 CMD 92h SN SC 0100h FR 0lh 2 CMD 92h SN SC 0100h FR 0lh 3 CMD 92h SN SC 0100h FR 0lh 4 CMD 92h SN SC 0000h FR 07h Transfer of 127 KB from the first Transfer from 128 to 255 KB Transfer from 256 to 383 KB Firmware rewriting execution Transfer example 2 1 CMD 92h SN SC 0300h FR 0lh 2 CMD 92h SN SC 0000h FR 07h Transfer of 384 KB Firmware rewriting execution Transfer...

Page 181: ...ITE DMA V 2 V V V V V WRITE VERIFY V V V V V V READ VERIFY SECTOR S V V V V V V RECALIBRATE V V V V V SEEK V V V V V INITIALIZE DEVICE PARAMETERS V V V V IDENTIFY DEVICE V V V V IDENTIFY DEVICE DMA V V V V SET FEATURES V V V V SET MULTIPLE MODE V V V V SET MAX ADDRESS V V V V V READ NATIVE MAX ADDRESS V V V V EXECUTE DEVICE DIAGNOSTIC 1 1 1 1 1 V READ LONG V V V V V WRITE LONG V V V V V READ BUFFE...

Page 182: ...ECURITY SET PASSWORD V V V V SECURITY UNLOCK V V V V FLUSH CACHE V V V V V DEVICE CONFIGURATION V V V V READ NATIVE MAX ADDRESS EXT O V V V V SET MAX ADDRESS EXT O V V V V V FLUSH CACHE EXT O V V V V V WRITE DMA EXT O V 2 V V V V V READ DMA EXT O V 2 V V V V V V WRITE MULTIPLE EXT O V V V V V READ MULTIPLE EXT O V V V V V V WRITE SECTOR S EXT O V V V V V READ SECTOR S EXT O V V V V V V DOWNLOAD MI...

Page 183: ...In the READ LONG command 516 bytes are transferred Following shows the protocol outline a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head registers b The host writes a command code to the Command register c The device sets the BSY bit of the Status register and prepares for data transfer d When one sector of data is available for transfer...

Page 184: ...ure 5 3 shows an example of READ SECTOR S command protocol and Figure 5 4 shows an example protocol for command abort Figure 5 3 Read Sector s command protocol IMPORTANT For transfer of a sector of data the host needs to read Status register X 1F7 in order to clear INTRQ interrupt signal The Status register should be read within a period from the DRQ setting by the ...

Page 185: ...nsfer operation is not guaranteed When the host new command even if the device requests the data transfer setting in DRQ bit the correct device operation is not guaranteed Figure 5 4 Protocol for command abort 5 4 2 PIO Data transferring commands from host to device The execution of the following commands involves Data transfer from the host to the drive WRITE SECTOR S EXT WRITE LONG WRITE BUFFER ...

Page 186: ...he device is ready to receive the data of the first sector the device sets DRQ bit and clears BSY bit d The host writes one sector of data through the Data register e The device clears the DRQ bit and sets the BSY bit f When the drive completes transferring the data of the sector the device clears BSY bit and asserts INTRQ signal If transfer of another sector is requested the drive sets the DRQ bi...

Page 187: ... the host does not need to read the Status register for the first and the last sector to be transferred If the timing to read the Status register does not meet above condition normal data transfer operation is not assured guaranteed When the host issues the command even if the drive requests the data transfer DRQ bit is set or when the host executes resetting the device correct operation is not gu...

Page 188: ...LE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE CHECK POWER MODE SMART DISABLE OPERATION SMART ENABLE DISABLE AUTOSAVE SMART ENABLE OPERATION SMART EXECUTE OFFLINE IMMEDIATE SMART RETURN STATUS SECURITY ERASE PREPARE SECURITY FREEZE LOCK FLUSH CACHE EXT Figure 5 6 shows the protocol for the command execution without data transfer Figure 5 6 Protocol for the command execution without data transfer ...

Page 189: ...AD DMA EXT WRITE DMA EXT Starting the DMA transfer command is the same as the READ SECTOR S or WRITE SECTOR S command except the point that the host initializes the DMA channel preceding the command issuance Interruption processing for DMA transfer does not issue interruptions in any intermediate sector when a multisector command is executed The following outlines the protocol ...

Page 190: ... channel c The host writes a command code in the Command register d The device sets the BSY bit of the Status register e The device asserts the DMARQ signal after completing the preparation of data transfer The device asserts either the BSY bit or DRQ bit during DMA data transfer f When the command execution is completed the device clears both BSY and DRQ bits and asserts the INTRQ signal Then the...

Page 191: ...5 4 Command Protocol C141 E192 01EN 5 117 g d f f d e Figure 5 7 Normal DMA data transfer ...

Page 192: ...tra DMA data out burst During an Ultra DMA burst a sender shall always drive data onto the bus and after a sufficient time to allow for propagation delay cable settling and setup time the sender shall generate a STROBE edge to latch the data Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data Words in the IDENTIFY DEVICE dat...

Page 193: ...eneral Ultra DMA rules a An Ultra DMA burst is defined as the period from an assertion of DMACK by the host to the subsequent negation of DMACK b A recipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra DMA burst 5 5 3 Ultra DMA data in commands 5 5 3 1 Initiating an Ultra DMA data in burst The following steps shall occur in the order they are listed ...

Page 194: ... in transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 3 and 5 6 3 2 for specific timing requirements 1 The device shall drive a data word onto DD 15 0 2 The device shall generate a DSTROBE edge to latch the new word no sooner than tDVS after changing the state of DD 15 0 The device shall generate a DSTROBE edge no more frequently ...

Page 195: ...ost shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and tRFS timing for the device 5 The host shall resume an Ultra DMA burst by asserting HDMARDY 5 5 3 4 Terminating an Ultra DMA data in burst a Device terminating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherw...

Page 196: ...th the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 12 The device shall release DSTROBE within tIORDYZ after the host negates DMACK 13 The host shall not negate STOP no assert HDMARDY until at least tACK after negating DMACK 14 The hos...

Page 197: ...egated DMARQ For this step the host may first drive DD 15 0 with the result of its CRC calculation see 5 5 5 10 If the host has not placed the result of its CRC calculation on DD 15 0 since first driving DD 15 0 during 9 the host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 11 The host shall negate DMACK no sooner than tMLI after the device has asserted DSTROBE and negated DM...

Page 198: ... asserted DMACK Once the device has negated DDMARDY the device shall not release DDMARDY until after the host has negated DMACK at the end of an Ultra DMA burst 8 The host shall negate STOP within tENV after asserting DMACK The host shall not assert STOP until after the first negation of HSTROBE 9 The device shall assert DDMARDY within tLI after the host has negated STOP After asserting DMARQ and ...

Page 199: ...n Ultra DMA burst by not generating an HSTROBE edge Note The device shall not immediately negate DMARQ to initiate Ultra DMA burst termination when the host stops generating HSTROBE edges If the host does not assert STOP in order to initiate Ultra DMA burst termination the device shall negate DDMARDY and wait tRP before negating DMARQ 3 The host shall resume an Ultra DMA burst by generating an HST...

Page 200: ...e device has negated DMARQ No data shall be transferred during this assertion The device shall ignore this transition on HSTROBE HSTROBE shall remain asserted until the Ultra DMA burst is terminated 6 The host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 7 The host shall negate DMACK no sooner than tMLI after the host has asserted HSTROBE and STOP and the device has negated D...

Page 201: ...he device shall not assert DMARQ again until after the Ultra DMA burst is terminated 6 The host shall assert STOP with tLI after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated 7 If HSTROBE is negated the host shall assert HSTROBE with tLI after the device has negated DMARQ No data shall be transferred during this assertion The device...

Page 202: ...d the results of its CRC calculation function to the device on DD 15 0 with the negation of DMACK f The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function If the two values do not match the device shall save the error and report it at the end of the command A subsequent Ultra DMA burst for the same command that does not have a CRC err...

Page 203: ...es The following table describes recommended values for series termination at the host and the device Table 5 22 Recommended series termination for Ultra DMA Signal Host Termination Device Termination DIOR HDMARDY HSTROBE 22 ohm 82 ohm DIOW STOP 22 ohm 82 ohm CS0 CS1 33 ohm 82 ohm DA0 DA1 DA2 33 ohm 82 ohm DMACK 22 ohm 82 ohm DD15 through DD0 33 ohm 22 ohm DMARQ 82 ohm 22 ohm INTRQ 82 ohm 22 ohm I...

Page 204: ...register selection setup time for DIOR DIOW 25 ns t2 Pulse width of DIOR DIOW 70 ns t2i Recovery time of DIOR DIOW 25 ns t3 Data setup time for DIOW 20 ns t4 Data hold time for DIOW 10 ns t5 Time from DIOR assertion to read data available 50 ns t6 Data hold time for DIOR 5 ns t9 Data register selection hold time for DIOR DIOW 10 ns t10 Time from DIOR DIOW assertion to IORDY low level 35 ns t11 Tim...

Page 205: ...IOW tI Symbol Timing parameter Min Max Unit t0 Cycle time 120 ns tD Pulse width of DIOR DIOW 70 ns tE Data Access time for DIOR 50 ns tF Data hold time for DIOR 5 ns tG Data setup time for DIOR DIOW 20 ns tH Data hold time for DIOW 10 ns tI DMACK setup time for DIOR DIOW 0 ns t CS 1 0 Available time for DIOR DIOW 25 ns Figure 5 10 Multiword DMA data transfer timing mode 2 ...

Page 206: ...ting an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 11 Initiating an Ultra DMA data in burst DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DA0 DA1 DA2 CS0 CS1 tUI tENV tFS tENV tZAD tFS tZAD ...

Page 207: ... 4 6 Data hold time at recipient from STROBE edge until data may become invalid 2 5 tDVS 70 48 31 20 6 7 4 8 Data valid setup time at sender from data valid until STROBE edge 3 tDVH 6 2 6 2 6 2 6 2 6 2 4 8 Data valid hold time at sender from STROBE edge until data may become invalid 3 tCS 15 10 7 7 5 5 CRC word setup time at device 2 tCH 5 5 5 5 5 5 CRC word hold time device 2 tCVS 70 48 31 20 6 7...

Page 208: ...gation tSS 50 50 50 50 50 50 Time from STROBE edge to negation of DMARQ or assertion of STOP when sender terminates a burst 1 Except for some instances of tMLI that apply to host signals only the parameters tUI tMLI and tLI indicate sender to recipient or recipient to sender interlocks i e one agent either sender or recipient is waiting for the other agent to respond with a signal before proceedin...

Page 209: ...2 tDVHIC 9 9 9 9 9 6 Sender IC data valid hold time from STROBE edge until data may become invalid 2 1 The correct data value shall be captured by the recipient given input data with a slew rate of 0 4 V ns rising and falling and the input STROBE with a slew rate of 0 4 V ns rising and falling at tDSIC and tDHIC timing as measured through 1 5V 2 The parameters tDVSIC and tDVHIC shall be met for lu...

Page 210: ...hasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Figure 5 12 Sustained Ultra DMA data in burst DSTROBE at device DD 15 0 at device DSTROBE at host DD 15 0 at host t2CYC tCYC tDVS tDVSIC tDVH tDVHIC tDS tDSIC tDH tDHIC t2CYC tCYC tDVS tDVSIC tDVH tDVHIC tDH tDHIC...

Page 211: ...otes 1 The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY is negated 2 After negating HDMARDY the host may receive zero one two or three more data words from the device Figure 5 13 Host pausing an Ultra DMA data in burst tRP tRFS DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 device ...

Page 212: ...a DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 14 Device terminating an Ultra DMA data in burst DMARQ device DMACK host DD 15 0 HDMARDY host DSTROBE device STOP host DA0 DA1 DA2 CS0 CS1 tMLI tLI tLI tLI tACK tACK tIORDYZ tSS tZAH tAZ tCVS tCVH CRC tACK ...

Page 213: ...MA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 15 Host terminating an Ultra DMA data in burst DMARQ device tLI tMLI tRP tZAH tAZ tRFS tLI tMLI tCVS tCVH tACK tACK tACK tIORDYZ CRC DA0 DA1 DA2 CS0 CS1 DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 ...

Page 214: ... Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 16 Initiating an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tUI tACK tENV tZIORDY tUI tLI tACK tACK tDVH tDVS tDZFS ...

Page 215: ...hasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Figure 5 17 Sustained Ultra DMA data out burst HSTROBE at host HSTROBE at device DD 15 0 at host DD 15 0 at device t2CYC tCYC tCYC t2CYC tDVH tDVHIC tDVS tDVSIC tDVS tDVSIC tDVH tDVHIC tDH tDHIC tDS tDSIC tDH tDHI...

Page 216: ...tes 1 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY is negated 2 After negating DDMARDY the device may receive zero one two or three more data words from the host Figure 5 18 Device pausing an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host tRP tRFS ...

Page 217: ...ltra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 19 Host terminating an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host tLI tLI tSS tLI tMLI tACK tIORDYZ tACK tACK tCVH tCVS CRC DA0 DA1 DA2 CS0 CS1 ...

Page 218: ... DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 20 Device terminating an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tLI tLI tRP tRFS tMLI tMLI tCVS tCVH tIORDYZ tACK tACK tACK CRC ...

Page 219: ...re reset 2 Master and slave devices are present 2 drives configuration tP Clear Reset Slave device Master device tN DASP PDIAG BSY BSY DASP tQ tR tS Symbol Timing parameter Min Max Unit tM Pulse width of RESET 25 µs tN Time from RESET negation to BSY set 400 ns tP Time from RESET negation to DASP or DIAG negation 1 ms tQ Self diagnostics execution time 30 s tR Time from RESET negation to DASP asse...

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Page 221: ...C141 E192 01EN 6 1 CHAPTER 6 Operations 6 1 Device Response to the Reset 6 2 Power Save 6 3 Defect Processing 6 4 Read Ahead Cache 6 5 Write Cache ...

Page 222: ...firms assertion of the DASP signal Then the master device checks a PDIAG signal to see if the slave device has successfully completed the power on diagnostics If the master device cannot confirm assertion of the DASP signal within 500 ms the master device recognizes that no slave device is connected After the slave device device 1 releases its own power on reset state the slave device shall report...

Page 223: ...ore the device power is turned on 6 1 2 Response to hardware reset Response to RESET hardware reset through the interface is similar to the power on reset Upon receipt of hardware reset the master device checks a DASP signal for up to 500 ms to confirm presence of a slave device The master device recognizes the presence of the slave device when it confirms assertion of the DASP signal Then the mas...

Page 224: ...ted within 30 seconds The asserted PDIAG signal is negated 30 seconds after it is asserted if the command is not received Max 31 sec Max 450 ms Max 30 sec Max 1 ms If presence of a slave device is confirmed PDIAG is checked for up to 31 seconds Checks DASP for up to 500 ms DASP PDIAG BSY bit Reset Status Reg BSY bit Slave device Master device Figure 6 2 Response to hardware reset Note Master Devic...

Page 225: ... report its presence and the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 30 seconds The asserted PDIAG signal is negated 30 seconds after it is asserted if the command is not received When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal Max 31 sec Max 30 sec Max 1 ms If t...

Page 226: ...he self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 5 seconds The asserted PDIAG signal is negated 5 seconds after it is asserted if the command is not received If the command is received the PDIAG signal is negated according to timing at which the command is received When the IDD is set to a slave device the IDD asserts the DASP signal ...

Page 227: ...1 Active mode In this mode all the electric circuit in the device are active or the device is under seek read or write operation A device enters the active mode under the following conditions The media access system is received 2 Active idle mode In this mode circuits on the device is set to power save mode The device enters the Active idle mode under the following conditions After completion of t...

Page 228: ...as elapsed in the low power idle state APM Mode 2 The time specified by the STANDBY or IDLE command has elapsed after completion of the command A reset is issued in the sleep mode When one of following commands is issued the command is executed normally and the device is still stayed in the standby mode Reset hardware or software STANDBY command STANDBY IMMEDIATE command INITIALIZE DEVICE PARAMETE...

Page 229: ...ve sector is alternated with the spare area depending on media defect location information The media defect location information is registered in the system space specified for the user area according to the format at shipment of the media from the plant 6 3 1 Spare area The following type of area is prepared as the spare area in user areas 1 Spare cylinder for alternate assignment This cylinder i...

Page 230: ...r defective sectors Figure 6 5 shows an example where sector physical 5 with cylinder 0 and head 0 is defective Sector physical Cylinder 0 Head 0 Defec tive sector Not used 778 779 780 777 778 779 Note When an access request for sector 5 is issued physical sector 6 must be accessed instead of physical sector 5 Figure 6 5 Sector slip processing 2 Track slip processing In this method defective track...

Page 231: ...ating processing is not performed If error recovery is not successful even if a write fault error retry is executed automatic alternating processing is performed Figure 6 6 shows an example where automatic alternating processing is applied to sector physical 5 with cylinder 0 and head 0 Sector physical Cylinder 0 Head 0 Defec tive sector Not used Alternate cylinder 0 Head 0 This is assigned to an ...

Page 232: ...ter data access becomes possible for the host 6 4 1 DATA buffer structure This device contains a data buffer 2 MB This buffer is divided into two areas one area is used for MPU work and the other is used as a read cache for another command See Figures 6 7 and 6 8 For MPU work For R W command For MPU work 2048 KB 2097152 bytes 391 KB 400384 bytes 1657 KB 1696768 bytes 16 KB 16384 bytes Figure 6 7 D...

Page 233: ...Data that is a target of caching The data that is a target of caching are as follows 1 Read ahead data that is read from disk media and saved to the data buffer upon completion of execution of a command that is a target of caching 2 Pre read data that is read from disk media and saved to the data buffer before execution of a command that is a target of caching 3 Data required by a command that is ...

Page 234: ...When data in the buffer or on media is overwritten the overwritten data is invalidated READ DMA READ MULTIPLE READ SECTOR s READ DMA EXT READ MULTIPLE EXT READ SECTOR s EXT WRITE DMA WRITE MULTIPLE WRITE SECTOR s WRITE DMA EXT WRITE MULTIPLE EXT WRITE SECTOR s EXT READ DMA QUEUED READ DMA QUEUED EXT WRITE DMA QUEUED WRITE DMA QUEUED EXT READ STREAM PIO READ STREAM DMA WRITE STREAM PIO WRITE STREAM...

Page 235: ...ad of the segment allocated from Buffer If pre read is executed HAP is set at the requested data reading position Read segment HAP host address pointer DAP disk address pointer 2 During reading of read requested data the request data that has already been read is sent to the host system Read requested data Free space HAP DAP Read requested data is stored until this point 3 When reading of read req...

Page 236: ...e last read command and DAP is set at a present read position as it is Read ahead data Cache valid data Free space Read requested data DAP disk address pointer HAP host address pointer 2 During reading of read requested data the request data that has already been read is sent to the host system Cache valid data Free space Read requested data DAP disk address pointer HAP host address pointer 3 When...

Page 237: ...a new read ahead operation is not performed If the full hit command is received during the read ahead operation a transfer of the read requested data starts while the read ahead operation is in progress 1 An example is the state shown below where the previous read command is executing sequential reading First HAP is set at the location where hit data is stored HAP It is reset to the hit data locat...

Page 238: ...id data START LBA LAST LBA 1 HAP is set at the address where partial hit data is stored and Transfer is started Cache valid data Partial hit data HAP host address pointer 2 DAP and HAP are set at the head of Buffer newly allocated and insufficient data is read Read segment HAP host address pointer DAP disk address pointer 3 When reading the read requested data ends and the transmission of the read...

Page 239: ...DMA QUEUED WRITE DMA QUEUED EXT WRITE STREAM PIO WRITE STREAM DMA However the caching operation is not performed when the caching function is prohibited by the SET FEATURES command 2 Invalidation of cached data If an error occurs during writing onto media write processing is repeated up to as many times as specified for retry processing If retry fails for a sector because the retry limit is reache...

Page 240: ...sabling of the Write Cache function can be set only with the SET FEATURES command The setting does not changed even when the error status is reported The initial setting is stored in the system area of media System area information is loaded whenever the power is turned on 5 Reset response When a reset is received while cached data is stored on the data buffer data of the data buffer is written on...

Page 241: ... the host if automatic alternating processing for the error is performed normally Therefore the host cannot execute a retry for the unrecoverable error while Write Cache is enabled Be very careful on this point when using this function If a write error occurs an abort response is sent to all subsequent commands ...

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Page 243: ... The physical specifications of the drive do not always correspond to these parameters The BIOS of a PC AT cannot make full use of the physical specifications of these drivers To make the best use of these drives a BIOS that can handle the standard parameters of these drives is required Command Commands are instructions to input data to and output data from a drive Commands are written in command ...

Page 244: ...e spindle motor is stopped and circuits other than the interface control circuit are sleeping The drive enters sleep mode when the host issues the SLEEP command Reserved Reserved bits bytes and fields are set to zero and unusable because they are reserved for future standards Rotational delay Time delay due to disk rotation The mean delay is the time required for half a disk rotation The mean dela...

Page 245: ...rmation posted from the drive to the host when command execution is ended The status indicates the command termination state VCM Voice coil motor The voice coil motor is excited by one or more magnets In this drive the VCM is used to position the heads accurately and quickly ...

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Page 247: ...ter DRDY Drive ready DRQ Ddata request bit DSC Drive seek complete DWF Drive write fault E ECC Error checking and correction ER Error register ERR Error F FR Feature register H HA Host adapter HDD Hard disk drive I IDNF ID not found IRQ14 Interrupt request 14 L LED Light emitting diode M MB Mega byte MB S Mega byte per seconds MPU Micro processor unit P PCA Printed circuit assembly PIO Programmed ...

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Page 249: ...ata in burst 5 138 5 144 out burst 5 144 E enabling and disabling 6 20 F fluctuation current 1 7 full hit 6 17 H hit full 6 17 hit partial 6 18 hit sequential 6 16 host pausing Ultra DMA data in burst 5 137 host terminating Ultra DMA data in burst 5 139 out burst 5 143 I initiating Ultra DMA data in burst 5 132 out burst 5 140 initiating Ultra DMA data in burst 5 132 out burst 5 140 invalidating c...

Page 250: ...lip processing 6 10 sequential command 6 16 sequential hit 6 16 sleep mode 6 8 spare area 6 9 standby mode 6 8 status report in event of error 6 20 sustain Ultra DMA data in burst 5 136 out burst 5 141 sustained Ultra DMA data in burst 5 136 out burst 5 141 T terminating device Ultra DMA data out burst 5 138 5 144 terminating host Ultra DMA data in burst 5 139 out burst 5 143 timing multiword DMA ...

Page 251: ...G Good F Fair P Poor General appearance Technical level Organization Clarity Accuracy Illustration Glossary Acronyms Abbreviations Index Comments Suggestions List any errors or suggestions for improvement Page Line Contents Please send this form to the address below We will use your comments in planning future editions Address Fujitsu Learning Media Limited 37 10 Nishikamata 7 chome Oota ku Tokyo ...

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Page 253: ...MHT2080AT MHT2060AT MHT2040AT MHT2030AT MHT2020AT DISK DRIVES PRODUCT MANUAL C141 E192 01EN MHT2080AT MHT2060AT MHT2040AT MHT2030AT MHT2020AT DISK DRIVES PRODUCT MANUAL C141 E192 01EN ...

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