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Interface

5-52

C141-E050-02EN

At command issuance (I/O registers setting contents)

1F7

(CM)

X’99’ or X’E6’

1F6

(DH)

1F5

(CH)

1F4

(CL)

1F3

(SN)

1F2

(SC)

1F1

(FR)

At command completion (I/O registers contents to be read)

1F7

(ST)

Status information

1F6

(DH)

1F5

(CH)

1F4

(CL)

1F3

(SN)

1F2

(SC)

1F1

(ER)

Error information

(26) CHECK POWER MODE (X’98’ or X’E5’)

The host checks the power mode of the device with this command.

The host system can confirm the power save mode of the device by analyzing the
contents of the Sector Count and Sector registers.

The device sets the BSY bit and sets the following register value. After that, the
device clears the BSY bit and generates an interrupt.

Power save mode

Sector Count register

• During moving to standby mode

• Standby mode

• During returning from the standby mode

X’00’

• Idle mode

X’FF’

• Active mode

X’FF’

Summary of Contents for MHC2032AT

Page 1: ...C141 E050 02EN MHC2032AT MHC2040AT MHD2032AT MHD2021AT DISK DRIVES PRODUCT MANUAL ...

Page 2: ...mes no liability to any party for any damage caused by any error or omission contained in this manual its updates or supplements whether such errors or omissions result from negligence accident or any other cause In addition FUJITSU assumes no liability with respect to the application or use of any product or system in accordance with the descriptions or instructions contained herein including any...

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Page 4: ...C141 E050 02EN Revision History 1 1 Edition Date Revised section 1 Added Deleted Altered Details 01 1998 02 15 02 1998 0 1 Section s with asterisk refer to the previous edition when those were deleted ...

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Page 6: ...MHC Series and MHD Series and describes their features CHAPTER 2 Drive Configuration This chapter describes the internal configurations of the MHC Series and MHD Series and the configuration of the systems in which they operate CHAPTER 3 Conditions Installation This chapter describes the external dimensions installation conditions and switch settings of the MHC Series and MHD Series CHAPTER 4 Theo...

Page 7: ...signal is centered followed below by the indented message A wider line space precedes and follows the alert message to show where the alert message begins and ends The following is an example Example Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields The main alert messages in the t...

Page 8: ...nvolve adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system or other causes outside the disk drive ...

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Page 10: ...personal injury if the user does not perform the procedure correctly Also damage to the predate or other property may occur if the user does not perform the procedure correctly Task Alert message Page Normal Operation Data corruption Avoid mounting the disk near strong magnetic soures such as loud speakers Ensure that the disk drive is not affected by extrnal magnetic fields 3 6 ...

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Page 12: ...ns summary 1 4 1 2 2 Model and product number 1 6 1 3 Power Requirements 1 6 1 4 Environmental Specifications 1 8 1 5 Acoustic Noise 1 8 1 6 Shock and Vibration 1 9 1 7 Reliability 1 9 1 8 Error Rate 1 10 1 9 Media Defects 1 10 CHAPTER 2 Device Configuration 2 1 2 1 Device Configuration 2 2 2 2 System Configuration 2 4 2 2 1 ATA interface 2 4 2 2 2 1 drive connection 2 4 2 2 3 2 drives connection ...

Page 13: ...rs 3 10 3 4 2 Factory default setting 3 11 3 4 3 Master drive slave drive setting 3 11 3 4 4 CSEL setting 3 12 CHAPTER 4 Theory of Device Operation 4 1 4 1 Outline 4 2 4 2 Subassemblies 4 2 4 2 1 Disk 4 2 4 2 2 Head 4 2 4 2 3 Spindle 4 3 4 2 4 Actuator 4 3 4 2 5 Air filter 4 3 4 3 Circuit Configuration 4 4 4 4 Power on Sequence 4 6 4 5 Self calibration 4 7 4 5 1 Self calibration contents 4 7 4 5 2...

Page 14: ...erface signals 5 2 5 1 2 Signal assignment on the connector 5 3 5 2 Logical Interface 5 6 5 2 1 I O registers 5 7 5 2 2 Command block registers 5 8 5 2 3 Control block registers 5 13 5 3 Host Commands 5 13 5 3 1 Command code and parameters 5 14 5 3 2 Command descriptions 5 16 5 3 3 Error posting 5 68 5 4 Command Protocol 5 70 5 4 1 Data transferring commands from device to host 5 70 5 4 2 Data tra...

Page 15: ...les 5 89 5 5 6 Series termination required for Ultra DMA 5 91 5 6 Timing 5 92 5 6 1 PIO data transfer 5 92 5 6 2 Single word DMA data transfer 5 94 5 6 3 Multiword DMA data transfer 5 95 5 6 4 Transfer of Ultra DMA data 5 96 5 6 4 1 Starting of Ultra DMA data In Burst 5 96 5 6 4 2 Ultra DMA data burst timing requirements 5 97 5 6 4 3 Sustained Ultra DMA data in burst 5 99 5 6 4 4 Host pausing an U...

Page 16: ... Logical address 6 8 6 3 Power Save 6 9 6 3 1 Power save mode 6 9 6 3 2 Power commands 6 11 6 4 Defect Management 6 11 6 4 1 Spare area 6 12 6 4 2 Alternating defective sectors 6 12 6 5 Read Ahead Cache 6 14 6 5 1 Data buffer configuration 6 14 6 5 2 Caching operation 6 14 6 5 3 Usage of read segment 6 16 6 5 3 1 Mis hit no hit 6 16 6 5 3 2 Sequential read 6 17 6 5 3 3 Full hit hit all 6 20 6 5 3 ...

Page 17: ... 3 8 Power supply connector pins CN1 3 10 Figure 3 9 Jumper location 3 10 Figure 3 10 Factory default setting 3 11 Figure 3 11 Jumper setting of master or slave device 3 11 Figure 3 12 CSEL setting 3 12 Figure 3 13 Example 1 of Cable Select 3 12 Figure 3 14 Example 2 of Cable Select 3 13 Figure 4 1 Head structure 4 3 Figure 4 2 Circuit Configuration 4 5 Figure 4 3 Power on operation sequence 4 7 F...

Page 18: ...5 103 Figure 5 19 Sustained Ultra DMA data out burst 5 104 Figure 5 20 Device pausing an Ultra DMA data out burst 5 105 Figure 5 21 Host terminating an Ultra DMA data out burst 5 106 Figure 5 22 Device terminating an Ultra DMA data out burst 5 107 Figure 5 23 Power on Reset Timing 5 108 Figure 6 1 Response to power on 6 3 Figure 6 2 Response to hardware reset 6 4 Figure 6 3 Response to software re...

Page 19: ...5 38 Table 5 6 Diagnostic code 5 43 Table 5 7 Features Register values subcommands and functions 5 54 Table 5 8 Format of device attribute value data 5 56 Table 5 9 Format of insurance failure threshold value data 5 57 Table 5 10 Contents of security password 5 61 Table 5 11 Contents of SECURITY SET PASSWORD data 5 65 Table 5 12 Relationship between combination of Identifier and Security level and...

Page 20: ...1 6 Shock and Vibration 1 7 Reliability 1 8 Error Rate 1 9 Media Defects Overview and features are described in this chapter and specifications and power requirement are described The MHC Series and MHD Series are 2 5 inch hard disk drives with built in disk controllers These disk drives use the AT bus hard disk interface protocol and are compact and reliable ...

Page 21: ...sfer rate The disk drives the MHC Series and MHD Series have an internal data rate up to 10 6 MB s MHC D2032AT The disk drive supports an external data rate up to 33 3 MB s U DMA mode 2 4 Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed The average positioning time is 13 ms at read 1 1 2 Adaptability 1 Power save mo...

Page 22: ...sk access But if the read ahead data corresponds to the data requested by the next read command the data in the buffer can be transferred instead 4 Master slave The disk drives the MHC Series and MHD Series can be connected to ATA interface as daisy chain configuration Drive 0 is a master device drive 1 is a slave device 5 Error correction and retry by ECC If a recoverable error occurs the disk dr...

Page 23: ...t Density 178 000 BPI Rotational Speed 4 000 rpm 1 Average Latency 7 5 ms Positioning time read and seek Minimum Track to Track Average Maximum Full 2 5 ms typ Read 13 ms typ 23 ms typ Start Stop time Start 0 rpm to Drive Read Stop at Power Down Typ 5 sec Max 10 sec Typ 5 sec Max 15 sec when the command is stopped when the power is off Interface ATA 3 Max Cable length 0 46 m Data Transfer Rate To ...

Page 24: ...k Minimum Track to Track Average Maximum Full 2 5 ms typ Read 13 ms typ 23 ms typ Start Stop time Start 0 rpm to Drive Read Stop at Power Down Typ 5 sec Max 10 sec Typ 5 sec Max 15 sec when the command is stopped when the power is off Interface ATA 3 Max Cable length 0 46 m Data Transfer Rate To From Media 5 9 to 10 0 MB s 6 3 to 10 6 MB s To From Host 33 3 MB s Max U DMA mode 2 Data Buffer Size 5...

Page 25: ...number Table 1 3 lists the model names and product numbers of the MHC Series and MHD Series Table 1 3 Model names and product numbers Model Name Capacity user area Mounting screw Order No MHC2032AT 3 25 GB M3 depth 3 CA01677 B040 MHC2040AT 4 09 GB M3 depth 3 CA01677 B060 MHD2021AT 2 16 GB M3 depth 3 CA01678 B030 MHD2032AT 3 25 GB M3 depth 3 CA01678 B040 1 3 Power Requirements 1 Input Voltage 5 V 5...

Page 26: ... Spin up 1 0 9 A 0 9 A 4 5 W 4 5 W Idle 190 mA 190 mA 0 95 W 0 95 W R W 2 420 mA 430 mA 2 1 W 2 15 W Standby 70 mA 70 mA 0 35 W 0 35 W Sleep 26 mA 26 mA 0 13 W 0 13 W Energy Consumption Efficiency 0 0002 W MB 0 0003 W MB 1 Current at starting spindle motor 2 Power requirements reflect nominal values for 5V power 3 At 30 disk accessing 4 Current fluctuation Typ at 5V when power is turned on Figure ...

Page 27: ...he environmental specifications Table 1 5 Environmental specifications Temperature Operating Non operating Thermal Gradient 5 C to 55 C ambient 5 C to 60 C disk enclosure surface 40 C to 65 C 20 C h or less Humidity Operating Non operating Maximum Wet Bulb 8 to 90 RH Non condensing 5 to 95 RH Non condensing 29 C Altitude relative to sea level Operating Non operating 300 to 3 000 m 300 to 12 000 m ...

Page 28: ...ween failures MTBF Conditions of 300 000 h Current time 250H month or less 3000H years or less Operating time 20 or less of current time CSS operations 50 day or less Total 50 000 or less Power on off 1 day or more needed Environment 5 to 55 C 8 to 90 But humidity bulb temperature 29 C or less MTBF is defined as follows Total operation time in all fields MTBF H number of device failure in all fiel...

Page 29: ...ock assignment 1 8 Error Rate Known defects for which alternative blocks can be assigned are not included in the error rate count below It is assumed that the data blocks to be accessed are evenly distributed on the disk media 1 Unrecoverable read error Read errors that cannot be recovered by maximum 252 times read retries without user s retry and ECC corrections shall occur no more than 10 times ...

Page 30: ... 1 CHAPTER 2 Device Configuration 2 1 Device Configuration 2 2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate ...

Page 31: ... of disks used varies with the model as described below The disks are rated at over 50 000 start stop operations MHC2032AT 2 disks 4 Heads MHD2032AT 2 disks 4 Heads MHC2040AT 3 disks 6 Heads MHD2021AT 2 disks 3 Heads 2 Head The heads are of the contact start stop CSS type The head touches the disk surface while the disk is not rotating and automatically lifts when the disk starts Figure 2 2 illust...

Page 32: ...all less DC motor 4 Actuator The actuator uses a revolving voice coil motor VCM structure which consumes low power and generates very little heat The head assembly at the edge of the actuator arm is controlled and positioned by feedback of the servo information read by the read write head If the power is not on or if the spindle motor is stopped the head assembly stays in the specific CSS zone on ...

Page 33: ...er It improves data reliability by preventing errors caused by external noise 7 Controller circuit The controller circuit consists of an LSI chip to improve reliability The high speed microprocessor unit MPU achieves a high performance AT controller 2 2 System Configuration 2 2 1 ATA interface Figures 2 3 and 2 4 show the ATA interface system configuration The drive has a 44 pin PC AT interface co...

Page 34: ...sfer PIO mode 3 mode 4 or DMA mode 2 U DMA mode 2 occurence of ringing or crosstalk of the signal lines AT bus between the HA and the disk drive may be a great cause of the obstruction of system reliability Thus it is necessary that the capacitance of the signal lines including the HA and cable does not exceed the ATA 3 standard and the cable length between the HA and the disk drive should be as s...

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Page 36: ...n Conditions 3 1 Dimensions 3 2 Mounting 3 3 Cable Connections 3 4 Jumper Settings This chapter gives the external dimensions installation conditions surface temperature conditions cable connections and switch settings of the hard disk drives ...

Page 37: ...Conditions 3 2 C141 E050 02EN 3 1 Dimensions Figure 3 1 illustrates the dimensions of the disk drive and positions of the mounting screw holes All dimensions are in mm Figure 3 1 Dimensions MHC series 1 2 MHD2032AT ...

Page 38: ...3 2 Mounting C141 E050 02EN 3 3 Figure 3 1 Dimensions MHD series 2 2 ...

Page 39: ...141 E050 02EN 3 2 Mounting 1 Orientation Figure 3 2 illustrates the allowable orientations for the disk drive Figure 3 2 Orientation Sample MHC2040AT e Vertical 3 f Vertical 4 c Vertical 1 d Vertical 2 b Horizontal 1 a Horizontal 1 ...

Page 40: ...m frame do not allow the system frame to touch parts cover and base other than parts to which the HDD is attached 3 Limitation of side mounting Do not use the center hole For screw length see Figure 3 3 Note These dimensions are recommended values if it is not possible to satisfy them contact us Figure 3 3 Mounting frame structure Screw Screw Details of B Details of A 3 0 or less 3 0 or less Frame...

Page 41: ...erature from exceeding 60 C Provide air circulation in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface temperatures of the DE Regardless of the ambient temperature this surface temperature must meet the standards listed in Table 3 1 Figure 3 4 shows the temperature measurement point Figure 3 4 Surface temperature meas...

Page 42: ... and after installation Figure 3 5 Service area Sample MHC2040AT 6 External magnetic fields Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields Mounting screw hole Mounting screw hole Cable connection ...

Page 43: ...tions 3 3 1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices Figure 3 6 shows the locations of these connectors and terminals Figure 3 6 Connector locations Sample MHC2040AT Connector setting pins PCA ...

Page 44: ...ble 44 pin type FV08 A440 Junkosha For the host interface cable use a ribbon cable A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines This is because the interface is designed for ribbon cables and not for cables carrying differential signals 3 3 3 Device connection Figure 3 7 shows how to connect the devices Figure 3 7 Cable c...

Page 45: ...gure 3 8 shows the pin assignment of the power supply connector CN1 Figure 3 8 Power supply connector pins CN1 3 4 Jumper Settings 3 4 1 Location of setting jumpers Figure 3 9 shows the location of the jumpers to select drive configuration and functions Figure 3 9 Jumper location ...

Page 46: ...3 10 shows the default setting position at the factory Figure 3 10 Factory default setting 3 4 3 Master drive slave drive setting Master device device 0 or slave device device 1 is selected Figure 3 11 Jumper setting of master or slave device Note Pins A and C should be open 2 2 ...

Page 47: ...g unique interface cables By connecting the CSEL of the master device to the CSEL Line conducer of the cable and connecting it to ground further the CSEL is set to low level The device is identified as a master device At this time the CSEL of the slave device does not have a conductor Thus since the slave device is not connected to the CSEL conductor the CSEL is set to high level The device is ide...

Page 48: ...3 4 Jumper Settings C141 E050 02EN 3 13 Figure 3 14 Example 2 of Cable Select ...

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Page 50: ...4 3 Circuit Configuration 4 4 Power on Sequence 4 5 Self calibration 4 6 Read write Circuit 4 7 Servo Control This chapter explains basic design concepts of the disk drive Also this chapter explains subassemblies of the disk drive each sequence servo control and electrical circuit blocks ...

Page 51: ...sk drive has one PCA For details see Sections 4 3 4 2 1 Disk The DE contains disks with an outer diameter of 65 mm and an inner diameter of 20 mm The MHC2040AT has three disks and MHC2032AT MHD2032AT and MHD2021AT have two disks The head contacts the disk each time the disk rotation stops the life of the disk is 50 000 contacts or more Servo data is recorded on top disk Servo data is recorded on e...

Page 52: ...ong the inner or outer edge of the disk The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read write head 4 2 5 Air filter There are two types of air filters a breather filter and a circulation filter The breather filter makes an air in and out of the DE to prevent unnecessary pressu...

Page 53: ...ng GCR encoder and decoder and servo demodulation circuit 2 Servo circuit The position and speed of the voice coil motor are controlled by 2 closed loop servo using the servo information recorded on the data surface The servo information is an analog signal converted to digital for processeing by a MPU and then reconverted to an analog signal for control of the voice coil motor The MPU precisely s...

Page 54: ...4 3 Circuit Configuration C141 E050 02EN 4 5 Figure 4 2 Circuit Configuration ...

Page 55: ...is data buffer read write test after enabling response to the ATA bus c After confirming that the spindle motor has reached rated speed the disk drive releases the heads from the actuator magnet lock mechanism by applying current to the VCM This unlocks the heads which are parked at the inner circumference of the disks d The disk drive positions the heads onto the SA area and reads out the system ...

Page 56: ... 1 Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution The torque vary with the disk drive and the cylinder where the head is positioned To execute stable fast seek operations external forces are occasionally sensed The firmware of the drive measures and stores the force value of the actuator motor drive current...

Page 57: ...op gain from the position signal and stores the compensation value against to the target gain as ratio For compensating the direction current value to the power amplifier is multiplied by the compensation value By this compensation loop gain becomes constant value and the stable servo control is realized To compensate torque constant value change depending on cylinder whole cylinders from most inn...

Page 58: ...rite service is necessary the disk drive positions the head to the track requested by the host reads or writes data and restarts calibration This enables the host to execute the command without waiting for a long time even when the disk drive is performing self calibration The command execution wait time is about maximum 100 ms 4 6 Read write Circuit The read write circuit consists of the read wri...

Page 59: ...y the encoder circuit then sent to the PreAMP and the data is written onto the media 1 16 17 GCR The disk drive converts data using the 16 17 0 12 8 group coded recording GCR algorithm This code follows a format in which 0 to 12 0 s are inserted while the code bit is 1 and 0 to 8 0 s are inserted while the 0DD EVEN bit is 1 2 Write precompensation Write precompensation compensates during a write p...

Page 60: ...4 6 Read write Circuit C141 E050 02EN 4 11 Figure 4 4 Read write circuit block diagram ...

Page 61: ...uctuates The AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer inner head positions 2 Programmable filter The programmable filter circuit has a low pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost up function that equalizes the waveform of the read signal Cut...

Page 62: ... converts the 17 bit read data into the 16 bit NRZ data 4 6 4 Digital PLL circuit The drive uses constant density recording to increase total capacity This is different from the conventional method of recording data with a fixed data transfer rate at all data area In the constant density recording method data area is divided into zones by radius and the data transfer rate is set so that the record...

Page 63: ...vo data that is written on the data side beforehand 4 7 1 Servo control circuit Figure 4 6 is the block diagram of the servo control circuit The following describes the functions of the blocks Figure 4 6 Block diagram of servo control circuit 1 Microprocessor unit MPU The MPU includes the DSP unit and the MPU starts the spindle motor moves the heads to the reference cylinders seeks the specified c...

Page 64: ...d to reference cylinder Drives the VCM to position the head at the any cylinder in the data area The logical initial cylinder is at the outermost circumference cylinder 0 c Seek to specified cylinder Drives the VCM to position the head to the specified cylinder d Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator and stores the calibration valu...

Page 65: ...e Operation 4 16 C141 E050 02EN Figure 4 7 Physical sector servo configuration on disk surface Servo frame 60 servo frames revolution Circumference direction Diameter direction Erase DC erase area CYL n n even number ...

Page 66: ... D A converter DAC The D A converter DAC converts the VCM drive current value digital value calculated by the DSP unit into analog values and transfers them to the power amplifier 4 Power amplifier The power amplifier feeds currents corresponding to the DAC output signal voltage to the VCM 5 Spindle motor control circuit The spindle motor control circuit controls the sensor less spindle motor This...

Page 67: ... is used as the user data area SA area 3 Outer guard band This area is located at outer position of the user data area and the rotational speed of the spindle can be controlled on this cylinder area for head moving 4 7 3 Servo frame format As the servo information the IDD uses the two phase servo generated from the gray code and servo A to D This servo information is used for positioning operation...

Page 68: ...The MPU fetches the position sense data on the servo frame at a constant interval of sampling time executes calculation and updates the VCM drive current The servo control of the actuator includes the operation to move the head to the reference cylinder the seek operation to move the head to the target cylinder to read or write data and the track following operation to position the head onto the t...

Page 69: ...ference between the target position and the position clarified by the detected position sense data The filtering includes servo compensation These are digitally controlled by the firmware 4 7 5 Spindle motor control Hall less three phase twelve pole motor is used for the spindle motor and the 3 phase full half wave analog current control circuit is used as the spindle motor driver called SVC herea...

Page 70: ... SVC and accelerates till the rotational speed reaches 4 000 rpm When the rotational speed reaches 4 000 rpm the SVC enters the stable rotation mode 3 Stable rotation mode The MPU calcurates a time for one revolution of the spindle motor based on the PHASE signal from the SVC The MPU takes a difference between the current time and a time for one revolution at 4 000 rpm that the MPU already recogni...

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Page 72: ...PTER 5 Interface 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Ultra DMA Feature Set 5 6 Timing This chapter gives details about the interface and the interface commands and timings ...

Page 73: ...O PDIAG PASSED DIAGNOSTICS DASP DEVICE ACTIVE SLAVE PRESENT DIOW I O WRITE STOP STOP DURING ULTRA DMA DATA BURSTS D IOR I OREAD H D M A R D Y DMAREADYDURINGULTRADMADATAINBURSTS HSTROBE DATASTROBEDURINGULTRADMADATAOUTBURSTS IORDY I OREADY DDMARDY DMAR EADYDURINGULTRADMADATAOUTBURSTS DSTROBE DATASTROBEDURINGULTRADMADATAINBURSTS Figure 5 1 Interface signals ...

Page 74: ...E 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 ENCSEL ENCSEL KEY RESET DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND DMARQ DIOW STOP DIOR HDMRDY HSTROBE IORDY DDMARDY DSTROBE DMACK INTRQ DA1 DA0 CS0 DASP 5 VDC GND B D F 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 GND MSTR KEY GND DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 KEY GND GND GND CSEL GND ...

Page 75: ...e host later indicates that the transfer has been suspended DIOR I Read strobe signal from the host to read the device register or data port HDMARDY I Flow control signal for Ultra DMA data In transfer READ DMA command This signal is asserted by the host to inform the device that the host is ready to receive the Ultra DMA data In transfer The host can negate the HDMARDY signal to suspend the Ultra...

Page 76: ... a time multiplexed signal that indicates that the device is active and a slave device is present This signal is pulled up to 5 V through 10 kΩ resistor at each device IORDY O This signal requests the host system to delay the transfer cycle when the device is not ready to respond to a data transfer request from the host system DDMARDY O Flow control signal for Ultra DMA data Out transfer WRITE DMA...

Page 77: ...nal from the host to the device O indicates output signal from the device to the host I O indicates common output or bi directional signal between the host and the device 5 2 Logical Interface The device can operate for command execution in either address specified mode cylinder head sector CHS or Logical block address LBA mode The IDENTIFY DEVICE information indicates whether the device supports ...

Page 78: ...ow Cylinder Low X 1F4 L H H L H Cylinder High Cylinder High X 1F5 L H H H L Device Head Device Head X 1F6 L H H H H Status Command X 1F7 L L X X X Invalid Invalid Control block registers H L H H L Alternate Status Device Control X 3F6 H L H H H X 3F7 Notes 1 The Data register for read or write operation can be accessed by 16 bit data bus DATA0 to DATA15 2 The registers for read or write operation ...

Page 79: ... Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICRC UNC X IDNF X ABRT TK0NF AMNF X Unused Bit 7 Interface CRC Error ICRC This bit indicates that a CRC error occurred during Ultra DMA transfer Bit 6 Uncorrectable Data Error UNC This bit indicates that an uncorrectable data error has been encountered Bit 5 Unused Bit 4 ID Not Found IDNF This bit indicates an error except for bad sector uncorrectab...

Page 80: ...read or write operation between the host system and the device When the value in this register is X 00 the sector count is 256 When this register indicates X 00 at the completion of the command execution this indicates that the command is completed succefully If the command is not completed scuccessfully this register indicates the number of sectors to be transferred to complete the request from t...

Page 81: ...r 8 bits of the cylinder address are set to the Cylinder High register Under the LBA mode this register indicates LBA bits 23 to 16 8 Device Head register X 1F6 The contents of this register indicate the device and the head number When executing INITIALIZE DEVICE PARAMETERS command the contents of this register defines the number of heads minus 1 a maximum head No Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit...

Page 82: ...tem should not write the command block registers If the host system reads any command block register when BSY bit is 1 the contents of the Status register are posted This bit is set by the device under following conditions a Within 400 ns after RESET is negated or SRST is set in the Device Control register the BSY bit is set the BSY bit is cleared when the reset process is completed The BSY bit is...

Page 83: ...tes that the device is ready to transfer data of word unit or byte unit between the host system and the device Bit 2 Always 0 Bit 1 Always 0 Bit 0 Error ERR bit This bit indicates that an error was detected while the previous command was being executed The Error register indicates the additional information of the cause for the error 10 Command register X 1F7 The Command register contains a comman...

Page 84: ...he device is held reset state When two device are daisy chained on the interface setting this bit resets both device simultaneously The slave device is not required to execute the DASP handshake Bit 1 nIEN bit enables an interrupt INTRQ signal from the device to the host When this bit is 0 and the device is selected an interruption INTRQ signal can be enabled through a tri state buffer When this b...

Page 85: ... Y Y Y Y READ VERIFY SECTOR S 0 1 0 0 0 0 0 R N Y Y Y Y WRITE MULTIPLE 1 1 0 0 0 1 0 1 N Y Y Y Y WRITE DMA 1 1 0 0 1 0 1 R N Y Y Y Y WRITE VERIFY 0 0 1 1 1 1 0 0 N Y Y Y Y WRITE SECTOR S 0 0 1 1 0 0 0 R N Y Y Y Y RECALIBRATE 0 0 0 1 X X X X N N N N D SEEK 0 1 1 1 X X X X N N Y Y Y INITIALIZE DEVICE PARAMETERS 1 0 0 1 0 0 0 1 N Y N N Y IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D IDENTIFY DEVICE DMA 1...

Page 86: ... 0 1 0 0 1 0 0 0 1 N N N N D SMART 1 0 1 1 0 0 0 0 Y Y Y Y D SECURITY DISABLE PASSWORD 1 1 1 1 0 1 1 0 N N N N D SECURITY ERASE PREPARE 1 1 1 1 0 0 1 1 N N N N D SECURITY ERASE UNIT 1 1 1 1 0 1 0 0 N N N N D SECURITY FREEZE LOCK 1 1 1 1 0 1 0 1 N N N N D SECURITY SET PASSWORD 1 1 1 1 0 0 0 1 N N N N D SECURITY UNLOCK 1 1 1 1 0 0 1 0 N N N N D FLUSH CACHE 1 1 1 0 0 1 1 1 N N N N D Notes FR Features...

Page 87: ...ndication of the I O registers at command conpletion are shown as following in this subsection Example READ SECTOR S WITH RETRY At command issuance I O registers setting contents Bit 7 6 5 4 3 2 1 0 1F7H CM 0 0 1 0 0 0 0 0 1F6H DH L DV Head No LBA MSB 1F5H CH Start cylinder address MSB LBA 1F4H CL Start cylinder address LSB LBA 1F3H SN Start sector No LBA LSB 1F2H SC Transfer sector count 1F1H FR ...

Page 88: ...sectors specified in the Sector Count register from the address specified in the Device Head Cylinder High Cylinder Low and Sector Number registers Number of sectors can be specified to 256 sectors in maximum To specify 256 sectors reading 00 is specified For the DRQ INTRQ and BSY protocols related to data transfer see Subsection 5 4 1 If the head is not on the track specified by the host the devi...

Page 89: ...R 0 with Retry R 1 without Retry At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH L DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set ...

Page 90: ...d evenly having the same number of sectors block count as many full blocks as possible are transferred then a final partial block is transferred The number of sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when the READ MULTIPLE command is disabled the ...

Page 91: ...Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH L DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors...

Page 92: ...s a status to the host system The format of the error information is the same as the READ SECTOR S command In LBA mode The logical block address is specified using the start head No start cylinder No and first sector No fields At command completion the logical block address of the last sector and remaining number of sectors of which data was not transferred like in the CHS mode are set The host sy...

Page 93: ...l requested sectors are verified the device clears the BSY bit of the Status register and generates an interrupt Upon the completion of the command execution the command block registers contain the cylinder head and sector number of the last sector verified If an error occurs the verify operation is terminated at the sector where the error occurred The command block registers contain the cylinder ...

Page 94: ... of sectors of which data was not transferred is set in this register 5 WRITE SECTOR S X 30 or X 31 This command writes data of sectors from the address specified in the Device Head Cylinder High Cylinder Low and Sector Number registers to the address specified in the Sector Count register Number of sectors can be specified to 256 sectors in maximum Data transfer begins at the sector specified in ...

Page 95: ...d Then the host can read the command block registers to determine what error has occurred and on which sector the error has occurred At command issuance I O registers setting contents 1F7H CM 0 0 1 1 0 0 0 R 1F6H DH L DV StartheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count xx R 0 with Retry R 1...

Page 96: ...nd even if the value of the Sector Count register is less than the defined block count the value of the Sector Count should not be 0 If the number of requested sectors is not divided evenly having the same number of sectors block count as many full blocks as possible are transferred then a final partial block is transferred The number of sectors in the partial block to be transferred is n where n ...

Page 97: ...S command except for following events The data transfer starts at the timing of DMARQ signal assertion The device controls the assertion or negation timing of the DMARQ signal The device posts a status as the result of command execution only once at completion of the data transfer or completion of processing in the device The device posts a status as the result of command execution only once at co...

Page 98: ... without Retry At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH L DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 8...

Page 99: ...rmation 1F6H DH L DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 9 RECALIBRATE X 1x x X 0 to X F This command performs the calibration Upon receipt of this ...

Page 100: ...formation Note Also executable in LBA mode 10 SEEK X 7x x X 0 to X F This command performs a seek operation to the track and selects the head specified in the command block registers After completing the seek operation the device clears the BSY bit in the Status register and generates an interrupt The IDD always sets the DSC bit Drive Seek Complete status of the Status register to 1 In the LBA mod...

Page 101: ...h this command Upon receipt of this command the device sets the BSY bit of Status register and saves the parameters Then the device clears the BSY bit and generates an interrupt When the SC register is specified to X 00 an ABORTED COMMAND error is posted Other than X 00 is specified this command terminates normally The parameters set by this command are retained even after reset or power save oper...

Page 102: ... xx Number of sectors track Error infomation 12 IDENTIFY DEVICE X EC The host system issues the IDENTIFY DEVICE command to read parameter information 512 bytes from the device Upon receipt of this command the drive sets the BSY bit of Status register and sets required parameter information in the sector buffer The device then sets the DRQ bit of the Status register and generates an interrupt After...

Page 103: ...4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information Table 5 4 Information to be read by IDENTIFY DEVICE command 1 of 3 Word Value Description 0 X 0c5a General Configuration 1 1 X 18A0 X IF08 Number of cylinders MHC2032AT X 18A0 MHC2040AT X IF08 MHD2021AT X I068 MHD2032AT X I8A0 2 X 0000 Reserved 3 X 0010 Number of Heads 4 X 0000 Undefined 5 X 0000 Undefined 6 X 003F Number of sectors per t...

Page 104: ...ariable Number of current Head 56 Variable Number of current sectors per track 57 58 Variable Total number of current sectors 59 8 Transfer sector count currently set by READ WRITE MULTIPLE command 8 60 61 X 60F600 X 7A2F80 Total number of user addressable sectors LBA mode only MHC2032AT X 60F600 MHC2040AT X 7A2F80 MHD2021AT X 409980 MHD2032AT X 60F600 62 X 0000 Reserved 63 X xx07 Multiword DMA tr...

Page 105: ...command 2 of 3 1 Word 0 General configuration Bit 15 ATA device 0 ATAPI device 1 0 Bit 14 12 Undefined 0 Bit 11 Rotational speed tolerance is more than 0 5 1 Bit 10 Disk data transfer rate 10 Mbps 1 Bit 9 Disk data transfer rate is faster than 5 Mbps but 10 Mbps or slower 0 Bit 8 Disk data transfer rate is 5 Mbps or slower 0 Bit 7 Removable disk drive 0 Bit 6 Fixed drive 1 Bit 5 Spindle motor cont...

Page 106: ...n Bit 9 0 Undefined Bit 9 8 Always 1 Bit 7 0 Undefined 6 Word 51 PIO data transfer mode Bit 15 8 PIO data transfer mode X 02 PIO mode 2 Bit 7 0 Undefined 7 Word 53 Enable disable setting of word 54 58 and 64 70 Bit 15 3 Reserved Bit 2 Enable disable setting of word 88 1 Enable Bit 1 Enable disable setting of word 64 70 1 Enable Bit 0 Enable disable setting of word 54 58 1 Enable 8 Word 59 Transfer...

Page 107: ...tatus Bit 15 8 Reserved Bit 7 0 Advance PIO transfer mode Bit 1 1 Mode 4 Bit 0 1 Mode 3 11 WORD 80 Bit 15 4 Reserved Bit 3 ATA 3 supported 1 Bit 2 ATA 2 supported 1 Bit 1 ATA 1 supported 1 Bit 0 Undefined 12 WORD 82 Bit 15 4 Reserved Bit 3 Power Management feature set supported 1 Bit 2 Removable feature set supported 0 Bit 1 Security feature set supported 1 Bit 0 SMART feature set supported 1 13 W...

Page 108: ...IDENTIFY DEVICE DMA X EE When this command is not used to transfer data to the host in DMA mode this command functions in the same way as the Identify Device command At command issuance I O registers setting contents 1F7H CM 1 1 1 0 1 1 1 0 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH...

Page 109: ... Features register Table 5 5 Features register values and settable modes Features Register Drive operation mode X 02 Enables the write cache function X 03 Transfer mode depends on the contents of the Sector Count register Details are given later X 55 Disables read cache function X 66 Disables the reverting to power on default settings after software reset X 82 Disables the write cache function X A...

Page 110: ... sets X 03 to the Features register By issuing this command with setting a value to the Sector Count register the transfer mode can be selected Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value The IDD supports following values in the Sector Count register value If other value than below is specified an ABORTED COMMAND error is pos...

Page 111: ...pprots 2 4 8 16 and 32 sectors as the block counts Upon receipt of this command the device sets the BSY bit of the Status register and checks the contents of the Sector Count register If the contents of the Sector Count register is valid and is a supported block count the value is stored for all subsequent READ MULTIPLE and WRITE MULTIPLE commands Execution of these commands is then enabled If the...

Page 112: ... After power on or after hardware reset the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode The mode established before software reset is retained if disable default Features Reg 66h setting has been defined by the SET FEATURES command If disable default has not been defined after the software is the READ MULTIPLE and WRITE MULTIPLE commands are disabled The par...

Page 113: ...gnosis If device 1 is present Both devices shall execute self diagnosis The device 0 waits for up to 5 seconds until device 1 asserts the PDIAG signal If the device 1 does not assert the PDIAG signal but indicates an error the device 0 shall append X 80 to its own diagnostic status The device 0 clears the BSY bit of the Status register and generates an interrupt The device 1 does not generate an i...

Page 114: ...0 1F6H DH DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx 01H 1 01H Diagnostic code 1 This register indicates X 00 in the LBA mode 17 READ LONG X 22 or X 23 This command operates similarly to the READ SECTOR S command ...

Page 115: ...t command completion I O registers contents to be read 1F7H ST Status information 1F6H DH L DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER Cylinder No MSB LBA Cylinder No LSB LBA Sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error this register indicates 01 18 WRITE LONG X 32 or X 33 This command operates similarly to the READ SECTOR S command except...

Page 116: ...with Retry R 1 without Retry At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH L DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER Cylinder No MSB LBA Cylinder No LSB LBA Sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error this register indicates 01 19 READ BUFFER X E4 The host system can read the current content...

Page 117: ...xx xx xx Error information 20 WRITE BUFFER X E8 The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command Upon receipt of this command the device sets the BSY bit of the Status register Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data After that 512 bytes o...

Page 118: ...evice is already rotating the spin up sequence shall not be implemented By using this command the automatic power down function is enabled and the timer immediately starts the countdown When the timer reaches the specified value the device enters standby mode Enabling the automatic power down function means that the device automatically enters the standby mode after a certain period of time When t...

Page 119: ...5 X FE to X FF 21 minutes 15 seconds attention The automatic power down is excuted if no command is coming for 30 min default At command issuance I O registers setting contents 1F7H CM X 97 or X E3 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx Period of timer xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN...

Page 120: ...7H ST Status information 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information 23 STANDBY X 96 or X E2 Upon receipt of this command the device sets the BSY bit of the Status register and enters the standby mode The device then clears the BSY bit and generates an interrupt The device generates an interrupt even if the device has not fully entered the standby mode If th...

Page 121: ... setting contents 1F7H CM X 96 or X E2 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx Period of timer xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information 24 STANDBY IMMEDIATE X 94 or X E0 Upon receipt of this command the device sets the BSY bit of the Status registe...

Page 122: ... E6 This command is the only way to make the device enter the sleep mode Upon receipt of this command the device sets the BSY bit of the Status register and enters the sleep mode The device then clears the BSY bit and generates an interrupt The device generates an interrupt even if the device has not fully entered the sleep mode In the sleep mode the spindle motor is stopped and the ATA interface ...

Page 123: ...information 26 CHECK POWER MODE X 98 or X E5 The host checks the power mode of the device with this command The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector registers The device sets the BSY bit and sets the following register value After that the device clears the BSY bit and generates an interrupt Power save mode Sector Count ...

Page 124: ...fied in the FR register is supported the Aborted Command error is posted It is necessary for the host to set the keys CL 4Fh and CH C2h in the CL and CH registers prior to issuing this command If the keys are set incorrectly the Aborted Command error is posted In the default setting the failure prediction feature is disabled In this case the Aborted Command error is posted in response to subcomman...

Page 125: ...ned off and then on When the automatic saving feature is enabled the attribute values are saved before the device enters the power saving mode However if the failure prediction feature is disabled the attribute values are not automatically saved When the device receives this subcommand it asserts the BSY bit enables or disables the automatic saving feature then clears the BSY bit X D3 SMART Save A...

Page 126: ...gister D0h SMART Save Attribute Values subcommand FR register D3h or SMART Return Status subcommand FR register DAh to save the device attribute value data on a medium Alternative the device must issue the SMART Enable Disable Attribute AutoSave subcommand FR register D2h to use a feature which regularly save the device attribute value data to a medium The host can predict failures in the device b...

Page 127: ...cess this data using the SMART Read Attribute Thresholds subcommand FR register D1h Table 5 8 Format of device attribute value data Byte Item 00 01 Data format version number 02 Attribute 1 Attribute ID 03 04 Status flag 05 Current attribute value 06 Attribute value for worst case so far 07 to 0C Raw attribute value 0D Reserved 0E to 169 Attribute 2 to attribute 30 The format of each attribute val...

Page 128: ...he data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds The data format version numbers of the device attribute values and insurance failure thresholds are the same When a data format is changed the data format version numbers are updated Attribute ID The attribute ID is defined as follows Attribute ID Attribute n...

Page 129: ...rrences 5 If this bit 1 it indicates the attribute that can be collected saved even if the drive fault prediction function is disabled 6 to 15 Reserve bit Current attribute value The current attribute value is the normalized raw attribute data The value varies between 01h and 64h The closer the value gets to 01h the higher the possibility of a failure The device compares the attribute values with ...

Page 130: ...ired for next segment sec Indicates the time required to terminate the next segment Current segment pointer Indicates the number of the next segment to be executed Off line data collection capability Indicates the method of off line data collection carried out by the drive If the off line data collection capability is 0 it indicates that off line data collection is not supported Bit Meaning 0 Indi...

Page 131: ...ice The device compares the user password or master password in the transferred data with the user password or master password already set and releases the lock function if the passwords are the same Although this command invalidates the user password the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password If the user passw...

Page 132: ...1F3h SN 1F2h SC 1F1h FR xx xx xx xx xx At command completion I O register contents 1F7h ST Status information 1F6h DH DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information 29 SECURITY ERASE PREPARE F3h The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command The SECURITY ERASE PREPARE command pre...

Page 133: ...byte data shown in Table 5 10 to the device The device compares the user password or master password in the transferred data with the user password or master password already set The device erases user data invalidates the user password and releases the lock function if the passwords are the same Although this command invalidates the user password the master password is retained To recover the mas...

Page 134: ...puts the device into FROZEN MODE The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE SECURITY SET PASSWORD SECURITY UNLOCK SECURITY DISABLE PASSWORD SECURITY ERASE UNIT FROZEN MODE is canceled when the power is turned off If this command is reissued in FROZEN MODE the command is completed and FROZEN MODE remains unchanged Issuing...

Page 135: ...CURITY SET PASSWORD READ SECTORS WRITE SECTORS WRITE VERIFY At command issuance I O register contents 1F7h CM 1 1 1 1 0 1 0 1 1F6h DH DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h FR xx xx xx xx xx At command completion I O register contents 1F7h ST Status information 1F6h DH DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information ...

Page 136: ...cording to the specifications of the Identifier bit and Security level bit in the transferred data Table 1 3 Issuing this command in LOCKED MODE or FROZEN MODE returns the Aborted Command error Table 5 11 Contents of SECURITY SET PASSWORD data Word Contents 0 Control word Bit 0 Identifier 0 Sets a user password 1 Sets a master password Bits 1 to 7 Reserved Bit 8 Security level 0 High 1 Maximum Bit...

Page 137: ...512 byte data shown in Table 1 1 to the device Operation of the device varies as follows depending on whether the host specifies the master password When the master password is selected When the security level is LOCKED MODE is high the password is compared with the master password already set If the passwords are the same LOCKED MODE is conceled Otherwise the Aborted Command error is returned If ...

Page 138: ... the device into the medium BSY bit is held at 1 until every data has been written normally or a error has occurred The device performs every error recovery so that the data are read correctly When executing this command the reading of the data may take several seconds if much data are to be read Complete execution of this command may take 30 seconds or over In case a non recoverable error has occ...

Page 139: ... SN 1F2h SC 1F1h ER xx xx xx xx Error information 5 3 3 Error posting Table 5 7 lists the defined errors that are valid for each command Table 5 13 Command code and parameters 1 of 2 Command name Error register X 1F1 Status register X 1F7 BBK UNC INDF ABRT TK0NF DRDY DWF ERR READ SECTOR S V V V V V V V WRITE SECTOR S V V V V V V READ MULTIPLE V V V V V V V WRITE MULTIPLE V V V V V V READ DMA V V V...

Page 140: ...MA V V V V SET FEATURES V V V V SET MULTIPLE MODE V V V V EXECUTE DEVICE DIAGNOSTIC V READ LONG V V V V V V WRITE LONG V V V V V V READ BUFFER V V V V WRITE BUFFER V V V V IDLE V V V V IDLE IMMEDIATE V V V V STANDBY V V V V STANDBY IMMEDIATE V V V V SLEEP V V V V CHECK POWER MODE V V V V SMART V V V V V SECURITY DISABLE PASSWORD V V V V SECURITY ERASE PREPARE V V V V SECURITY ERASE UNIT V V V V SE...

Page 141: ... command 516 bytes are transferred Following shows the protocol outline a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head registers b The host writes a command code to the Command register c The device sets the BSY bit of the Status register and prepares for data transfer d When one sector of data is available for transfer to the host the...

Page 142: ... an example protocol for command abort Figure 5 3 Read Sector s command protocol Note For transfer of a sector of data the host needs to read Status register X 1F7 in order to clear INTRQ interrupt signal The Status register should be read within a period from the DRQ setting by the device to 50 ms after the completion of the sector data transfer Note that the host does not need to read the Status...

Page 143: ...erring commands from host to device The execution of the following commands involves Data transfer from the host to the drive WRITE SECTOR S WRITE LONG WRITE BUFFER WRITE VERIFY SECURITY DISABLE PASSWORD SECURITY ERASE UNIT SECURITY SET PASSWORD SECURITY UNCLOK The execution of these commands includes the transfer one or more sectors of data from the host to the device In the WRITE LONG command 51...

Page 144: ...e clears the DRQ bit and sets the BSY bit f When the drive completes transferring the data of the sector the device clears BSY bit and asserts INTRQ signal If transfer of another sector is requested the drive sets the DRQ bit g After detecting the INTRQ signal assertion the host reads the Status register h The device resets INTRQ the interrupt signal I If transfer of another sector is requested st...

Page 145: ...mal data transfer operation is not assured guaranteed When the host issues the command even if the drive requests the data transfer DRQ bit is set or when the host executes resetting the device correct operation is not guaranteed 5 4 3 Commands without data transfer Execution of the following commands does not involve data transfer between the host and the device RECABLIBRATE SEEK READY VERIFY SEC...

Page 146: ...ssue interruptions in any intermediate sector when a multisector command is executed The following outlines the protocol The interrupt processing for the DMA transfer differs the following point The interrupt processing for the DMA transfer differs the following point a The host writes any parameters to the Features Sector Count Sector Number Cylinder and Device Head register b The host initialize...

Page 147: ... completed the device clears both BSY and DRQ bits and asserts the INTRQ signal Then the host reads the Status register g The host resets the DMA channel Figure 5 7 shows the correct DMA data transfer protocol Figure 5 7 Normal DMA data transfer f d e e d g d f f ...

Page 148: ...Ultra DMA data out burst During an Ultra DMA burst a sender shall always drive data onto the bus and after a sufficient time to allow for propagation delay cable settling and setup time the sender shall generate a STROBE edge to latch the data Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data The highest fundamental freque...

Page 149: ...or HDMARDY and STROBE is used in cases that could apply to either DSTROBE or HSTROBE The following are general Ultra DMA rules a An Ultra DMA burst is defined as the period from an assertion of DMACK by the host to the subsequent negation of DMACK b A recipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra DMA burst 5 5 2 1 Ultra DMA burst initiation p...

Page 150: ...ansmission side and then should output the termination request signal when a certain wait time has elapsed e The transmitting side is allowed to send STROBE signal at a transfer speed that is lower than the one in the transferable fastest Ultra DMA mode but is not allowed to send the STROBE signal at a higher speed than this The receiving side should be able to receive the data in the transferable...

Page 151: ... DMA data in commands 5 5 3 1 Initiating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 1 and 5 6 4 2 for specific timing requirements 1 The host shall keep DMACK in the negated state before an Ultra DMA burst is initiated 2 The device shall assert DMARQ to initiate an Ultra DMA burst After assertion of DMARQ ...

Page 152: ...e to latch the new word no sooner than tDVS after changing the state of DD 15 0 The device shall generate a DSTROBE edge no more frequently than tCYC for the selected Ultra DMA Mode The device shall not generate two rising or two falling DSTROBE edges more frequently than 2tCYC for the selected Ultra DMA mode 3 The device shall not change the state of DD 15 0 until at least tDVH after generating a...

Page 153: ...minating an Ultra DMA data in burst a Device terminating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 5 and 5 6 4 2 for specific timing requirements 1 The device shall initiate termination of an Ultra DMA burst by not generating DSTROBE edges 2 The device shall negate DMARQ no sooner than tSS after generatin...

Page 154: ...at occurred see 5 5 5 12 The device shall release DSTROBE within tIORDYZ after the host negates DMACK 13 The host shall not negate STOP no assert HDMARDY until at least tACK after negating DMACK 14 The host shall not assert DIOR CS0 CS1 DA2 DA1 or DA0 until at least tACK after negating DMACK b Host terminating an Ultra DMA data in burst The following steps shall occur in the order they are listed ...

Page 155: ...ost has not placed the result of its CRC calculation on DD 15 0 since first driving DD 15 0 during 9 the host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 11 The host shall negate DMACK no sooner than tMLI after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY and no sooner than tDVS after the host places the result of its C...

Page 156: ...ll not release DDMARDY until after the host has negated DMACK at the end of an Ultra DMA burst 8 The host shall negate STOP within tENV after asserting DMACK The host shall not assert STOP until after the first negation of HSTROBE 9 The device shall assert DDMARDY within tLI after the host has negated STOP After asserting DMARQ and DDMARDY the device shall not negate either signal until after the ...

Page 157: ...diately negate DMARQ to initiate Ultra DMA burst termination when the host stops generating HSTROBE edges If the host does not assert STOP in order to initiate Ultra DMA burst termination the device shall negate DDMARDY and wait tRP before negating DMARQ 3 The host shall resume an Ultra DMA burst by generating an HSTROBE edge b Device pausing an Ultra DMA data out burst 1 The device shall not paus...

Page 158: ...fter the device has negated DMARQ No data shall be transferred during this assertion The device shall ignore this transition on HSTROBE HSTROBE shall remain asserted until the Ultra DMA burst is terminated 6 The host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 7 The host shall negate DMACK no sooner than tMLI after the host has asserted HSTROBE and STOP and the device has ne...

Page 159: ... shall not assert DMARQ again until after the Ultra DMA burst is terminated 6 The host shall assert STOP with tLI after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated 7 If HSTROBE is negated the host shall assert HSTROBE with tLI after the device has negated DMARQ No data shall be transferred during this assertion The device shall ig...

Page 160: ...s CRC calculation function to the device on DD 15 0 with the negation of DMACK f The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function If the two values do not match the device shall save the error and report it at the end of the command A subsequent Ultra DMA burst for the same command that does not have a CRC error shall not clear ...

Page 161: ...f4 XOR f9 XOR f16 CRCIN5 f11 XOR f CRCIN13 f3 XOR f8 XOR f15 CRCIN6 f10 XOR f15 CRCIN14 f2 XOR f7 XOR f14 CRCIN7 f9 XOR f14 CRCIN15 f1 XOR f6 XOR f13 f1 DD0 XOR CRCOUT15 f9 DD8 XOR CRCOUT7 XOR f5 f2 DD1 XOR CRCOUT14 f10 DD9 XOR CRCOUT6 XOR f6 f3 DD2 XOR CRCOUT13 f11 DD10 XOR CRCOUT5 XOR f7 f4 DD3 XOR CRCOUT12 f12 DD11 XOR CRCOUT4 XOR f1 XOR f8 f5 DD4 XOR CRCOUT11 XOR f1 f13 DD12 XOR CRCOUT3 XOR f2...

Page 162: ...0 DA1 DA2 33 ohm 82 ohm DMACK 33 ohm 82 ohm DD15 through DD0 33 ohm 240 ohm 100 MHz DMARQ 82 ohm 33 ohm INTRQ 82 ohm 33 ohm IORDY DDMARDY DSTROBE 82 ohm 22 ohm Note Only those signals requiring termination are listed in this table If a signal is not listed series termination is not required for operation in an Ultra DMA Mode For signals also requiring a pull up or pull down resistor at the host se...

Page 163: ...Interface 5 92 C141 E050 02EN 5 6 Timing 5 6 1 PIO data transfer Figure 5 10 shows of the data transfer timing between the device and the host system ...

Page 164: ...5 6 Timing C141 E050 02EN 5 93 Figure 5 10 Data transfer timing ...

Page 165: ...e 5 94 C141 E050 02EN 5 6 2 Single word DMA data transfer Figure 5 9 show the single word DMA data transfer timing between the device and the host system Figure 5 11 Single word DMA data transfer timing mode 2 ...

Page 166: ...6 3 Multiword DMA data transfer Figure 5 10 shows the multiword DMA data transfer timing between the device and the host system Delay time from DIOR DIOW assertion to DMARQ negation Figure 5 12 Multiword DMA data transfer timing mode 2 ...

Page 167: ... Ultra DMA Burst Table 5 13 includes the timing for each Ultra DMA mode 5 6 4 1 Starting of Ultra DMA data In Burst The timing for each Ultra DMA mode is included in 5 6 4 2 Note The definitions of STOP HDMARDY and DSTROBE signals are valid before the assertion of DMACK signal Figure 5 13 Starting of Ultra DMA data In Burst transfer ...

Page 168: ... edge until data may become invalid tFS 0 230 0 200 0 170 First STROBE time for device to first negate DSTROBE from STOP during a data in burst tLI 0 150 0 150 0 150 Limited interlock time see Note 1 tMLI 20 20 20 Interlock time with minimum see Note 1 tUI 0 0 0 Unlimited interlock time see Note 1 tAZ 10 10 10 Maximum time allowed for output drivers to release from being asserted or negated tZAH 2...

Page 169: ...to negation of DMARQ or assertion of STOP when sender terminates a burst Notes 1 tUI tMLI and tLI indicate sender to recipient or recipient to sender interlocks that is one agent either sender or recipient is waiting for the other agent to respond with a signal before proceeding tUI is an unlimited interlock that has no maximum time value tMLI is a limited time out that has a defined minimum tLI i...

Page 170: ...of the Ultra DMA Modes Note DD 15 0 and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Figure 5 14 Sustained Ultra DMA data in burst ...

Page 171: ...mings for each of the Ultra DMA Modes Notes 1 The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY is negated 2 If the tSR timing is not satisfied the host may receive zero one or two more data words from the device Figure 5 15 Host pausing an Ultra DMA data in burst ...

Page 172: ... data in burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 16 Device terminating an Ultra DMA data in burst ...

Page 173: ...data in burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 17 Host terminating an Ultra DMA data in burst ...

Page 174: ...A data out burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 18 Initiating an Ultra DMA data out burst ...

Page 175: ...he Ultra DMA Modes Note DD 15 0 and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Figure 5 19 Sustained Ultra DMA data out burst ...

Page 176: ...ings for each of the Ultra DMA Modes Notes 1 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY is negated 2 If the tSR timing is not satisfied the device may receive zero one or two more data words from the host Figure 5 20 Device pausing an Ultra DMA data out burst ...

Page 177: ...data out burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 21 Host terminating an Ultra DMA data out burst ...

Page 178: ... data in burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 22 Device terminating an Ultra DMA data out burst ...

Page 179: ...and reset Figure 5 11 shows power on and reset hardware and software reset timing 1 Only master device is present 2 Master and slave devices are present 2 drives configulation Figure 5 23 Power on Reset Timing 31 Power on Reset RESET PDIAG negation ...

Page 180: ...C141 E050 02EN 6 1 CHAPTER 6 Operations 6 1 Device Response to the Reset 6 2 Address Translation 6 3 Power Save 6 4 Defect Management 6 5 Read Ahead Cache 6 6 Write Cache ...

Page 181: ...recognizes presence of the slave device when it confirms assertion of the DASP signal Then the master device checks a PDIAG signal to see if the slave device has sucessfully completed the power on diagnostics If the master device cannot confirm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is connected After the slave device device 1 releases its own ...

Page 182: ...6 1 Device Response to the Reset C141 E050 02EN 6 3 Figure 6 1 Response to power on 31 sec 30 sec ...

Page 183: ...nal Then the master device checks a PDIAG signal to see if the slave device has successfully completed the self diagnostics If the master device cannot confirm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is connected After the slave device receives the hardware reset the slave device shall report its presense and the result of the self diagnostics t...

Page 184: ...fully After the slave device receives the software reset the slave device shall report its presense and the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 30 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting the PDIAG sig...

Page 185: ...oes not check the DASP signal After the slave device receives the EXECUTE DEVICE DIAGNOSTIC command it shall report the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 5 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting th...

Page 186: ...on mode The parameters in Table 6 1 are called BIOS specification Table 6 1 Default parameters MHC2032AT MHC2040AT MHD2021AT MHD2032AT Number of cylinders 6 304 7 944 4 200 6 304 Number of heads 16 16 16 16 Number of sectors track 63 63 63 63 Formatted capacity MB 3 253 4 4 099 8 2167 6 3253 4 As long as the formatted capacity of the IDD does not exceed the value shown on Table 6 1 the host can fr...

Page 187: ...a zone of a physical head is used the track is switched and the next logical sector is placed in the initial sector in the same zone of the subsequent physical head After the last physical sector of the last physical head is used in the zone the subsequent zone is used and logical sectors are assigned from physical head 0 in the same way Figure 6 5 shows an example of 6 heads configuration assumin...

Page 188: ... used and LBA is assigned from physical head 0 in the same way Figure 6 6 shows an example of 4 heads configuration assuming there is no track skew 459 230 229 228 229 230 230 229 458 232 231 230 6 5 Figure 6 6 Address translation example in LBA mode 6 3 Power Save The host can change the power consumption state of the device by issuing a power command to the device 6 3 1 Power save mode There are...

Page 189: ...circuits on the device is set to power save mode The device enters the Idle mode under the following conditions After completion of power on sequence After completion of the command execution other than SLEEP and STANDBY commands After completion of the reset sequence 3 Standby mode In this mode the VCM circuit is turned off and the spindle motor is stopped The device can receive commands through ...

Page 190: ...urn from the standby mode is to execute a software or hardware reset The drive enters the sleep mode under the following condition A SLEEP command is issued Issued commands are invalid ignored in this mode 6 3 2 Power commands The following commands are available as power commands IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE 6 4 Defect Management Defective sectors of which ...

Page 191: ... defective sector is not used and is skipped and a logical sector address is assigned to the subsequent normal sector physically adjacent sector to the defective sector When defective sector is present the sector slip processing is performed in the formatting Figure 6 7 shows an example where physical sector 5 is defective on head 0 in cylinder 0 If an access request to physical sector 5 is specif...

Page 192: ...cal sector 5 is specified the device accesses the alternated sector in the alternate cylinder instead of sector 5 When an access request to sectors next to sector 5 is specified the device seeks to cylinder 0 head 0 and continues the processing 3 Automatic alternate assignment The device performs the automatic alternate assignment when ECC correction performance is increased during read error retr...

Page 193: ...MB 524 288 bytes 262 144 byte 512 sector 131 072 byte 256 sector 131 072 byte Figure 6 9 Data buffer configuration The read ahead operation is performed at execution of the READ SECTOR S READ MULTIPLE or READ DMA command and read ahead data is stored in the buffer for read commands 6 5 2 Caching operation Caching operation is performed only at issurance of the following commands The device transfe...

Page 194: ...e data However since the hit check at issurance of read command is performed to the data buffer for read command prioritily caching write data is limited to the case that the hit check is missed at the data buffer for read command When all data requested by the read command are stored in the data buffer for write command hit all the device transfers data from the data buffer for write command At t...

Page 195: ...command is issued write data kept until now are invalidated 6 5 3 Usage of read segment This subsection explains the usage of the read segment buffer at following cases 6 5 3 1 Mis hit no hit A lead block of the read requested data is not stored in the data buffer The requested data is read from the disk media The read ahead operation is performed only when the last sector address of the previous ...

Page 196: ... HAP 4 Following shows the cache enabled data for next read command Cache enabled data Empty area 6 5 3 2 Sequential read When the disk drive receives the read command that targets the sequential address to the previous read command the disk drive starts the read ahead operation a Sequential command just after non sequential command When the previously executed read command is an non sequential co...

Page 197: ...ing the requested data Requested data DAP HAP Mis hit data Empty area 3 After completion of the reading and transferring the requested data to the host system the disk drive performs the read ahead operation continuously Requested data DAP HAP Completion of transferring requested data Empty area Read ahead data 4 The disk drive performs the read ahead operation for all area of segment with overwri...

Page 198: ...he same time as the disk drive starts transferring data to the host system 1 In the case that the contents of buffer is as follows at receiving a read command Start LBA Last LBA DAP HAP Continued from the previous read request data Hit data Read ahead data 2 The disk drive starts the read ahead operation to the empty area that becomes vacant by data transfer at the same time as the disk drive star...

Page 199: ...tarts transferring the requested data from the address of which the requested data is stored After completion of command a previously existed cache data before the full hit reading are still kept in the buffer and the disk drive does not perform the read ahead operation 1 In the case that the contents of the data buffer is as follows for example and the previous command is a sequential read comman...

Page 200: ...ot perform the read ahead operation after data transfer Following is an example of partially hit to the cache data Last LBA Cache data 1 The disk drive sets the HAP to the address where the partially hit data is stored and sets the DAP to the address just after the partially hit data HAP DAP Partially hit data Lack data 2 The disk drive starts transferring partially hit data and reads lack data fr...

Page 201: ... by the host system At this time if the write operation of the previous command is still been executed the drive continuously executes the write operation of the next command from the sector next to the last sector of the previous write operation Thus the latency time for detecting a target sector of the next command is eliminated This shortens the access time The drive generates an interrupt of c...

Page 202: ...e cache function is operated with the following command WRITE SECTOR S WRITE MULTIPLE WRITE DMA Ultra Write DMA When Write Cache is permitted the writing of the data transferred from the host by the abovementioned Write Cache permit command into the disk medium may not be completed at the moment a normal ending interrupt has occurred In case a non recoverable error has occurred during receiving mo...

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Page 204: ... The physical specifications of the drive do not always correspond to these parameters The BIOS of a PC AT cannot make full use of the physical specifications of these drivers To make the best use of these drives a BIOS that can handle the standard parameters of these drives is required Command Commands are instructions to input data to and output data from a drive Commands are written in command ...

Page 205: ...e spindle motor is stopped and circuits other than the interface control circuit are sleeping The drive enters sleep mode when the host issues the SLEEP command Reserved Reserved bits bytes and fields are set to zero and unusable because they are reserved for future standards Rotational delay Time delay due to disk rotation The mean delay is the time required for half a disk rotation The mean dela...

Page 206: ...rmation posted from the drive to the host when command execution is ended The status indicates the command termination state VCM Voice coil motor The voice coil motor is excited by one or more magnets In this drive the VCM is used to position the heads accurately and quickly ...

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Page 208: ...ter DRDY Drive ready DRQ Ddata request bit DSC Drive seek complete DWF Drive write fault E ECC Error checking and correction ER Error register ERR Error F FR Feature register H HA Host adapter HDD Hard disk drive I IDNF ID not found IRQ14 Interrupt request 14 L LED Light emitting diode M MB Mega byte MB S Mega byte per seconds MPU Micro processor unit P PCA Printed circuit assembly PIO Programed i...

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Page 210: ...positioning time 1 2 B Block diagram read write circuit 4 11 Block diagram of servo control circuit 4 14 Blower 4 3 Blower effect 2 4 Breather filter 4 3 BSY 5 11 Buffer data 1 3 C Cable connection 3 7 3 8 Cable connector specification 3 8 Cache write 1 3 Cache system read ahead 1 3 Caching operation 6 14 Calibration 4 15 Carriage head 4 3 CHECK POWER MODE 5 52 Check sum 5 58 CHS mode 6 8 Circuit ...

Page 211: ... when power is turned on 1 6 Current requirement 1 6 Cylinder High register 5 10 Cylinder Low register 5 10 D DAC 4 17 D A converter 4 17 Data object of caching operation 6 15 Data area 4 18 Data assurance in event of power failure 1 9 Data buffer 1 3 Data buffer configuration 6 14 Data corruption 3 6 Data format version number 5 57 Data register 5 8 Data separator circuit 4 13 Data surface servo ...

Page 212: ...ode 4 19 Guard band inner 4 18 Guard band outer 4 18 H HA 2 5 Head 2 2 4 2 Head carriage 4 3 Head structure 4 3 High speed transfer rate 1 2 Hit full 6 20 Hit no 6 16 Hit partially 6 21 Hit sequential 6 19 Hit all 6 20 Host command 5 13 I ID attribute 5 57 IDENTIFY DEVICE 5 31 IDENTIFY DEVICE DMA 5 37 IDLE 5 47 IDLE IMMEDIATE 5 49 Idle mode 6 10 INITIALIZE DEVICE PARAMETERS 5 30 Inner guard band 4...

Page 213: ...O Mode 4 2 4 Positioning error 1 9 Power amplifier 4 17 Power commands 6 11 Power dissipation 1 6 Power on 5 79 Power on off sequence 1 6 Power on sequence 4 6 Power on timing 5 80 Power requirement 1 5 Power save 6 9 Power save mode 1 2 6 9 Power supply connector 3 9 PreAMP 4 9 Processing command 4 9 Processing sector slip 16 12 Product number model name 1 5 Programmable filter 4 12 Programmable ...

Page 214: ...re circuit 4 17 Servo C 4 19 Servo circuit 4 4 Servo control 4 14 Servo control circuit 4 14 Servo D 4 19 Servo format data surface 4 18 Servo frame format 4 18 Servo mark 4 19 SET FEATURES 5 38 SET MULTIPLE MODE 5 40 Setting CSEL 3 11 Setting factory default 3 10 Setting jumper 3 9 Setting master drive 3 10 Setting slave drive 3 10 Shock 1 8 Signal interface 5 2 Signal assignment on connector 5 2...

Page 215: ...g power 5 80 Timing reset 5 80 Timing single word DMA data transfer 5 78 Track following operation 4 20 Transfer rate data 4 13 U Translation address 6 7 6 8 Unrecoverable read error 1 9 Usage of read segment 6 16 User password 5 66 V VCM 4 3 VCM current sense resistor CSR 4 17 Vibration 1 8 Viterbi detection circuit 4 13 Voice coil motor 4 3 W WRITE BUFFER 5 46 Write cache 1 3 6 22 Write circuit ...

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Page 217: ... F Fair P Poor General appearance Technical level Organization Clarity Accuracy Illustration Glossary Acronyms Abbreviations Index Comments Suggestions List any errors or suggestions for improvement Page Line Contents Please send this form to the address below We will use your comments in planning future editions Address Fujitsu Learning Media Limited 22 7 Minami Ooi 6 Chome Shinagawa Ku Tokyo 140...

Page 218: ...MHC2032 2040AT MHD2032 2021AT DISK DRIVES PRODUCT MANUAL C141 E050 02EN MHC2032 2040AT MHD2032 2021AT DISK DRIVES PRODUCT MANUAL C141 E050 02EN ...

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