Fujitsu MB90460 Series, Hardware Manual, Page: 241 / 739

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CHAPTER 11 WATCHDOG TIMER
11.3 Watchdog Timer Control Register (WDTC)
The watchdog timer control register (WDTC) activates and clears the watchdog timer,
and displays the reset cause.
■
Watchdog Timer Control Register (WDTC)
Figure 11.3-1 shows the watchdog timer control register (WDTC). Table 11.3-1 describes the function of
each bit of the watchdog timer control register (WDTC).
Figure 11.3-1 Watchdog Timer Control Register (WDTC)
The interval becomes 3.5 to 4.5 times longer than the count clock (time-base timer output value) cycle. For
details, see "11.4 Operation of the Watchdog Timer".
Addre ss
0000A 8
H
Initi a l v a l u e
X-XXX111
B
PONR - WR S T ER S T S R S T WTE WT1 WT0 (TBTC)
WT1 WT0
Interv a l s election b it (for 4 MHz HCLK)
Interv a l
Minim u m M a xim u m
O s cill a tion clock
cycle co u nt
0
0
0
Approx. 3 .5 8 m s Approx. 4.61 m s
Power-on
W a tchdog timer
Extern a l pin (R S TX inp u t)
R S T b it ( s oftw a re re s et)
2
14
±2
11
cycle
2
16
±2
1 3
cycle
2
1 8
±2
15
cycle
2
21
±2
1 8
cycle
Approx. 14. 33 m s
HCLK: O s cill a tion clock
Approx. 1 8 . 3 m s
Approx. 57.2 3 m s Approx. 7 3 .7 3 m s
Approx. 45 8 .75 m s Approx. 5 8 9. 8 2 m s
1
1
0
1
1
WTE
0
- Activ a tion of the w a tchdog timer
(At fir s t write a fter re s et)
- Cle a ring of the w a tchdog timer
(At s econd or subs e qu ent write a fter re s et)
No oper a tion 1
W a tchdog control b it
15 b it
R R R R W W W
8 6 7 5 4 3 2 1 0
PONR
* *
1 *
* 1
1 X X X
*
*
*
1
*
*
WR S T ER
S T S R S T
Re s et c aus e b it
Re s et c aus e
R: Re a d only
W: Write only
X: Undefined
*: Ret
a in s the previo us s t a t us .
: Initi a l v a l u e