Fujitsu MB90460 Series, Hardware Manual, Page: 242 / 739

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CHAPTER 11 WATCHDOG TIMER
Table 11.3-1 Function Description of Each bit of the Watchdog Timer Control Register (WDTC)
Bit name Function
bit7,
bit5
to
bit3
PONR, WRST,
ERST, SRST:
Reset cause bits
•
Read-only bits for indicating the reset cause. If more than one reset cause occurs, the bit
for each reset cause occurring is set to "1".
•
These bits are all cleared to "0" after the watchdog timer control register (WDTC) is read.
•
At power-on, the contents of the bits other than the PONR bit are not guaranteed.
Therefore, when the PONR bit is "1", ignore the contents of the bits other than the PONR
bit.
bit2
WTE:
Watchdog timer
control bit
•
When "0" is written to this bit, the watchdog timer is activated (first write after reset) or
the 2-bit counter is cleared (second or subsequent write after reset).
•
Writing "1" does not affect operation.
bit1,
bit0
WT1, WT0:
Interval selection bit
•
Used to select the watchdog timer interval.
•
Only data at watchdog timer activation is valid.
Data written after watchdog timer activation is ignored.
•
These bits are write-only.