Fujitsu MB90390 Series, Hardware Manual

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CHAPTER 28 3M-BIT FLASH MEMORY
28.8 Notes on using 3M-bit Flash Memory
This section contains notes on using 3M-bit flash memory.
■
Notes on Using Flash Memory
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Input of a hardware reset (RST)
To input a hardware reset when the automatic algorithm has not been started and reading is in progress, a
minimum low-level width of 500 ns must be maintained. In this case, a maximum of 500 ns is required
until data can be read from the flash memory after a hardware reset has been activated.
Similarly, to input a hardware reset when the automatic algorithm has been activated and writing or erasing
is in progress, a minimum low-level width of 500 ns must be maintained. In this case, 20 ns are required
until data can be read after the operation for initializing the flash memory has terminated.
A hardware reset during writing may cause the data being written to be undefined. A hardware reset during
erasing and, power supply cut-off may make the sector being erased unusable.
●
Canceling of a software reset and watchdog timer reset
When the flash memory is being written to or erased with CPU access and if reset conditions occur while
the automatic algorithm is active, the CPU may run out of control. This occurs because these reset
conditions cause the automatic algorithm to continue without initializing the flash memory unit, possibly
preventing the flash memory unit from entering the read state when the CPU starts the sequence after the
reset has been deasserted. These reset conditions must be disabled during writing to or erasing of the flash
memory.
●
Program access to flash memory
When the automatic algorithm is operating, read access to the flash memory is disabled. With the memory
access mode of the CPU set to built-in ROM mode, writing or erasing must be started after the program
area is switched to another area such as RAM.
In this case, when sectors (SA8/SA13) containing interrupt vectors are erased or written to, interrupt
processing cannot be executed. For the same reason, all interrupt sources other than the flash memory must
be disabled while the automatic algorithm is operating.
●
Hold function
When the CPU accepts a hold request, the Write signal WE of the flash memory unit may be skewed,
causing erroneous writing or erasing due to an erroneous write. When the acceptance of a hold request is
enabled (HDE bit of EPCR set to "1"), ensure that the WE bit of the control status register (FMCS) is "0".
●
Extended intelligent I/O service (EI
2
OS)
Because write and erase interrupts issued to the CPU from the flash memory interface circuit cannot be
accepted by the EI
2
OS, they should not be used.