Fujitsu MB15E07SL User Manual Download Page 20 | Manualshive

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MB15E07SL

20

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REFERENCE INFORMATION

(Continued)

S.G

Spectrum

Analyzer

OSC

IN

fin

Do

LPF

VCO

Test Circuit

f

VCO

= 810.45 MHz

K

V

= 17 MHz/V

fr = 25 kHz
f

OSC

= 14.4 MHz

V

CC

=V

P

= 3.0 V

V

VCO

= 2.3 V

Ta = +25

°

C

CP : 6 mA mode

9.1 k

Ω

4.2 k

Ω

0.047

µ

F

1500 pF

4700 pF

LPF

REF –5.0 dBm

ATT 10 dB

10 dB/

RBW
1 kHz
SAMPLE

VBW

1 kHz

MKR

25.0 kHz

–78.0 dB

CENTER 810.000 MHz

SPAN 200 kHz

SWP 1.0 s

REF –5.0 dBm

ATT 10 dB

10 dB/

RBW
100 Hz
SAMPLE

VBW

100 Hz

MKR

2.28 kHz

–53.1 dB

CENTER 810.000 MHz

SPAN 20.0 kHz

SWP 10 s

PLL Reference Leakage

PLL Phase Noise

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Summary of Contents for MB15E07SL

Page 1: ...y 3 5 mA at 2 7 V A refined charge pump supplies well balanced output currents of 1 5 mA and 6 mA The charge pump current is selectable by serial data MB15E07SL is ideally suited for wireless mobile communications such as GSM Global System for Mobile Communications and PCS FEATURES High frequency operation 2 5 GHz Max Low power supply voltage VCC 2 4 to 3 6 V Ultra Low power supply current ICC 3 5...

Page 2: ...7 Software selectable charge pump current On chip phase control for phase comparator Operating temperature Ta 40 to 85 C Pin compatible with MB15E07 MB15E07L PIN ASSIGNMENTS OSCIN OSCOUT VP VCC DO GND Xfin fin φR φP LD fout ZC PS LE Data Clock 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 OSCOUT VP VCC DO GND Xfin φP LD fout ZC PS LE Data OSCIN φR fin Clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FPT 16P ...

Page 3: ...ol bit Open is prohibited 11 10 LE I Load enable signal input Open is prohibited When LE is set high the data in the shift register is transferred to a latch according to the control bit in the serial data 12 11 PS I Power saving mode control This pin must be set at L at Power ON Open is prohibited PS H Normal mode PS L Power saving mode 13 12 ZC I Forced high impedance control for the charge pump...

Page 4: ... 9 8 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reference oscillator circuit Binary 14 bit reference counter Phase comparator Lock detector LD fr fp selector Charge pump Current switch 14 bit latch 7 bit latch Intermittent mode control power save 11 bit latch 1 bit control latch 4 bit latch 19 bit shift register Binary 7 bit swallow counter Binary 11 bit programmable counter SSOP BCC ...

Page 5: ...d operating condition ranges Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not represented on the data sheet Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand Parameter Symbol Condition Rating Un...

Page 6: ...IIH 0 100 µA L level input current IIL 4 100 0 H level input current ZC IIH 4 1 0 1 0 µA L level input current IIL 4 Pull up input 100 0 L level output voltage φ φ φ φP VOL Open drain output 0 4 V H level output voltage φ φ φ φR LD fout VOH VCC VP 3 0 V IOH 1 mA VCC 0 4 V L level output voltage VOL VCC VP 3 0 V IOL 1 mA 0 4 H level output voltage Do VDOH VCC VP 3 0 V IDOH 0 5 mA VP 0 4 V L level o...

Page 7: ...minus means direction of current flow 5 VCC VP 3 0 V Ta 25 C I3 I4 I3 I4 2 100 6 VCC VP 3 0 V Ta 25 C I2 I1 2 I1 I2 2 100 Applied to each IDOL IDOH 7 VCC VP 3 0 V VDO VP 2 IDO 85 C IDO 40 C 2 IDO 85 C IDO 40 C 2 100 Applied to each IDOL IDOH I1 I1 I3 I2 I2 I4 IDOL IDOH 0 5 Charge Pump Output Voltage V Vp 2 Vp Vp 0 5 V ...

Page 8: ...al data is entered through the Data pin One bit of data is shifted into the shift register on the rising edge of the Clock When the LE signal pin is taken high stored data is latched according to the control bit data as follows Table 1 Control Bit 1 Shift Register Configuration Control bit CNT Destination of serial data H For the programmable reference divider L For the programmable divider 1 2 3 ...

Page 9: ... 1 1 1 1 1 1 1 1 1 Divide ratio N N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 3 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 1 0 0 2047 1 1 1 1 1 1 1 1 1 1 1 Divide ratio A A7 A6 A5 A4 A3 A2 A1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 127 1 1 1 1 1 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 C N T A 1 A 2 A 3 A 4 A 5 A 6 A 7 N 1 N 2 N 3 N 4 N 5 N 6 N 7 N 8 N 9 N 10 N 11 Programmable Counter LSB MSB Data Flow CNT...

Page 10: ... comparator output φR φP are reversed according to the FC bit Also the monitor pin fOUT output is controlled by the FC bit The relationship between the FC bit and each of DO φR and φP is shown below Table 8 FC Bit Data Setting LDS H High Z SW Prescaler divide ratio H 32 33 L 64 65 CS Current value H 6 0 mA L 1 5 mA LDS LD fOUT output signal H fout signal L LD signal FC High FC Low DO φ φ φ φR φ φ ...

Page 11: ...mooth startup when the device returns to normal operation When the PLL is returned to normal operation the phase comparator output signal is unpredictable This is because of the unknown relationship between the comparison frequency fp and the reference frequency fr which can cause a major change in the comparator output resulting in a VCO frequency jump and an increase in lockup time To prevent a ...

Page 12: ...Power ON ON OFF VCC Clock Data LE PS 1 2 3 tV 1 µs tPS 100 ns 1 PS L power saving mode at Power ON 2 Set serial data 1 µs later after power supply remains stable VCC 2 2 V 3 Release power saving mode PS L H 100 ns later after setting serial data ...

Page 13: ...SB t1 t2 t3 t6 t5 t4 t7 Note LE should be L when the data is transferred into the shift register Parameter Min Typ Max Unit t1 20 ns t2 20 ns t3 30 ns t4 30 ns Parameter Min Typ Max Unit t5 100 ns t6 20 ns t7 100 ns On the rising edge of the clock one bit of data is transferred into the shift register ...

Page 14: ... to prevent dead zone LD output becomes low when phase is tWU or more LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more tWU and tWL depend on OSCIN input frequency tWU 2 fosc s e g tWU 156 3 ns fosc 12 8 MHz tWU 4 fosc s e g tWL 312 5 ns fosc 12 8 MHz LD becomes high during the power saving mode PS L FC H FC L ...

Page 15: ...ut Sensitivity fin OSCIN S G 50 Ω 1000 pF S G 50 Ω 1000 pF 0 1 µF 0 1 µF 8 6 4 3 1 9 10 11 12 14 7 5 2 13 15 16 1000 pF VCC fin Xfin GND DO VCC VP OSCOUT OSCIN Clock Data LE PS ZC LD fout φP φR Controller setting divide ratio Oscilloscope Note SSOP 16 ...

Page 16: ...t sensitivity Input frequency Prescaler 32 33 Input sensitivity Pfin dBm Input frequency fin MHz 10 0 10 20 30 40 50 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 VCC 2 4 V VCC 3 0 V VCC 3 6 V Ta 25 C 10 0 10 20 30 40 50 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 VCC 2 7 V VCC 3 0 V VCC 3 6 V Ta 25 C SPEC SPEC ...

Page 17: ...5E07SL 17 2 OSCIN input sensitivity Input sensitivity Input frequency Input frequency fOSC MHz Input sensitivity V OSC dBm 10 0 10 20 30 40 50 60 0 50 100 150 200 VCC 2 4 V VCC 3 0 V VCC 3 6 V Ta 25 C SPEC ...

Page 18: ... Charge pump output current I DO mA Charge pump output voltage VDO V Charge pump output current I DO mA 10 00 10 00 0 6000 div 4 800 2 000 div 0 Ta 25 C VCC 3 0 V Vp 3 0 V IDOH IDOL 10 00 10 00 0 6000 div 4 800 2 000 div 0 Ta 25 C VCC 3 0 V Vp 3 0 V IDOH IDOL 1 5 mA mode 6 0 mA mode ...

Page 19: ...2 156 Ω 12 136 Ω 1 5 GHz 33 805 Ω 11 869 Ω 2 GHz 1 2 3 4 23 715 Ω 8 9629 Ω 2 5 GHz 1 4 3 2 START 500 000 000 MHz STOP 2 500 000 000 MHz 9 917 Ω 3 643 Ω 3 MHz 3 7903 Ω 4 812 Ω 10 MHz 1 574 Ω 3 4046 Ω 20 MHz 1 2 3 4 453 12 Ω 1 9213 Ω 40 MHz 1 2 3 4 START 1 000 000 MHz STOP 50 000 000 MHz ...

Page 20: ...VP 3 0 V VVCO 2 3 V Ta 25 C CP 6 mA mode 9 1 kΩ 4 2 kΩ 0 047 µF 1500 pF 4700 pF LPF REF 5 0 dBm ATT 10 dB 10 dB RBW 1 kHz SAMPLE VBW 1 kHz MKR 25 0 kHz 78 0 dB CENTER 810 000 MHz SPAN 200 kHz SWP 1 0 s REF 5 0 dBm ATT 10 dB 10 dB RBW 100 Hz SAMPLE VBW 100 Hz MKR 2 28 kHz 53 1 dB CENTER 810 000 MHz SPAN 20 0 kHz SWP 10 s PLL Reference Leakage PLL Phase Noise ...

Page 21: ...Hz 826 000 MHz 806 000 MHz 500 0 µs div 500 0 µs div 810 MH 826 MHz within 1 kHz Lch Hch 1 30 ms 838 000 MHz 818 000 MHz 798 000 MHz 500 0 µs div PLL Lock Up time PLL Lock Up time 826 MH 810 MHz within 1 kHz Hch Lch 1 28 ms 500 0 µs div 810 004000MHz 810 000000MHz 809 996000MHz ...

Page 22: ...07SL From a controller PS LE Data OSCIN OSCOUT VP VCC DO GND Xfin fin VP 5 5 V Max Notes SSOP 16 In case of using a crystal resonator it is necessary to optimize matching between the crystal and this LSI and perform detailed system evaluation It is recommended to consult with a supplier of the crystal resonator Reference oscillator circuit provides its own bias feedback resistor is 100 kΩ Typ ...

Page 23: ...ive containers Use properly grounded workstations tools and equipment Turn off power before inserting device into or removing device from a socket Protect leads with a conductive sheet when transporting a board mounted device ORDERING INFORMATION Part number Package Remarks MB15E07SLPFV1 16 pin Plastic SSOP FPT 16P M05 MB15E07SLPV1 16 pad Plastic BCC LCC 16P M06 ...

Page 24: ...03 007 001 M 0 13 005 004 004 Details of A part 0 8 024 006 0 60 0 15 020 008 0 50 0 20 0 25 010 LEAD No INDEX 1 2 Dimensions in mm inches Note The values in parentheses are reference values 16 pin plastic SSOP FPT 16P M05 Note 1 1 Resin protrusion Each side 0 15 006 Max Note 2 2 These dimensions do not include resin protrusion Note 3 Pins width and pins thickness include plating thickness Note 4 ...

Page 25: ...1 MAX Mounting height 0 075 0 025 003 001 Stand off 0 05 002 6 9 1 14 9 14 1 6 0 40 0 10 016 004 0 75 0 10 030 004 Details of A part 1 725 068 REF 1 15 045 REF B Details of B part 024 004 0 60 0 10 024 004 0 60 0 10 0 65 026 TYP INDEX AREA 134 004 3 40 0 10 16 pad plastic BCC LCC 16P M06 Dimensions in mm inches Note The values in parentheses are reference values ...

Page 26: ...described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public a...

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