Fujitsu MB15C02 Datasheet Download

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MB15C02

7. Spectrum Wave Form

ATTEN 10 dB
RL 0 dBm

UAUG 16

10dB/

∆

MKR

−

85.50 dB

25.0 kHz

CENTER 286.0000 MHz
*RBW 1.0 kHz

VBW 1.0 kHz

SPAN 200.0 kHz
*SWP 1.00 s

D
S

∆

MKR

25.0 kHz

−

85.50 dB

•

LOCK Frequency : 286.0 MHz

(fr = 25 kHz)

•

= 1.2 V, V

= 1.2 V

Ta = +25

ATTEN 10 dB
RL 0 dBm

UAUG 50

10dB/

∆

MKR

−

53.84 dB

800 Hz

CENTER 286.00000 MHz
*RBW 100 Hz

VBW 100 kHz

SPAN 20.00 kHz
*SWP 3.00 s

D
S

∆

MKR

800 Hz

−

53.84 dB

•

LOCK Frequency : 286.0 MHz

( fr = 25 kHz)

•

= 1.2 V, V

= 1.2 V

Ta = +25

VT (to VCO)

6800 pF

68000 pF

4700 pF

15 k

Ω

4.3 k

Ω

* VCO : K

= 6 MHz/v

• Test circuit

Summary of Contents for MB15C02

Page 1: ...s with a supply voltage of 1 0 V min MB15C02 is suitable for mobile communications such as paging systems FEATURES High frequency operation 220 MHz max VDD 1 0 V to 1 5 V 330 MHz max VDD 1 2 V to 1 5 V 450 MHz max VDD 1 3 V to 1 5 V Single power supply VDD 1 0 to 1 5 V Power saving function Pulse swallow function 64 65 Serial input 14 bit programmable reference divider R 5 to 16 383 Serial input 1...

Page 2: ... 8 10 9 View VDD VSS Data LE Clock fin OSCIN OSCOUT TEST FC LD Do φP Vp PS NC NC 17 18 19 20 φR NC NC FPT 20P M03 Top 1 2 3 4 5 6 16 15 14 13 12 11 7 8 10 9 View VDD VSS Data LE Clock fin OSCIN OSCOUT TEST FC LD Do φP Vp PS φR FPT 16P M05 SSOP 16 pin SSOP 20 pin ...

Page 3: ...ing LD outputs L 8 10 Do O Charge pump output Phase of the charge pump can be reversed by FC input The Do output may be inverted by FC input The relationships between the programmable reference divider output fr and the programmable divider output fp are shown below fr fp H level FC L L level FC H fr fp High impedance fr fp L level FC L H level FC H 9 11 Vp Power supply for the charge pump 10 12 φ...

Page 4: ...cillator output Connection for an external crystal 18 NC No connection 15 19 OSCIN I Programmable reference divider input Oscillator input Clock can be input to OSCIN from outside In the case please leave OSCOUT pin open and make connection with OSCIN as AC coupling 16 20 VSS Ground pin ...

Page 5: ...erence counter Data 18 bit shift register 18 bit latch Binary 6 bit swallow counter Binary 12 bit programma ble counter LD fin Clock LE TEST VSS Prescaler Charge pump fp fr Intermittent mode control circuit PS FC Control circuit Lock detector φP φR 14 14 18 6 12 VDD Output control circuit Output control circuit Crystal oscillator circuit ...

Page 6: ... ranges Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not represented on the data sheet Users considering application outside the listed conditions are advised to contact their representatives beforehand Parameter Symbol Rating Unit Remark Min Max Power supply voltage ...

Page 7: ...pply current Active Mode IDD 1 VDD 1 0V 220MHz VDD 1 2V 330MHz VDD 1 3V 450MHz 0 6 1 0 1 3 1 2 1 8 2 2 mA Power saving current Power sav ing mode IDDS 2 VDD 1 0V VDD 1 2V VDD 1 3V 50 70 80 250 300 350 µA Operating frequency fin fin Programmable divider VDD 1 0 to 1 5V VDD 1 2 to 1 5V VDD 1 3 to 1 5V 10 10 10 220 330 450 MHz OSCIN fOSC Programmable reference divider 5 20 MHz Input sensitivity fin V...

Page 8: ...ror signal and resultant lock frequency fluctuations The intermittent mode control circuit is controlled by the PS pin Setting pin PS high provides the normal operation mode and setting the pin low provides the power saving mode The MB15C02 behavior in the active and power saving modes is summarized below Active mode PS H All MB15C02 circuits are active and provide the normal operation Power savin...

Page 9: ...n pin the connection must be AC coupled and OSCout pin is left open Also to prevent OSCout from malfunctioning its traces on the printed circuit board must be kept minimal or eliminated entirely whenever possible it must be free of any form of load The following divider is used Programmable reference counter R 5 to 16383 The fr and fosc have the following relation fr fosc R 4 Phase comparator The ...

Page 10: ...s logic levels summarized in Table 1 according to the phase error between fr and fp Note that φP is an Nch open drain output The pulse width of the phase comparator outputs are identical and equal to the phase error between fr and fp as shown in Figure 1 Figure 1 Phase comparator input output waveform fp fr When FC L When FC H Do Do High Z High Z φR φP φR φP High Z High Z High Z High impedance sta...

Page 11: ...states of the PLL The lock detector outputs H when the PLL enters the lock state and outputs L when the PLL enters the unlock state as shown in Figure 2 When PS L the lock detector outputs H compulsorily Figure 2 Phase comparator input output waveforms Lock detector fr fp LD ...

Page 12: ...divider the serial data consists of 14 divider bits and 1 control bit as shown in Figure 3 2 The control bit is set to 0 to identify the serial data for the programmable divider and to 1 to select the serial data for the programmable reference divider C A 0 A 1 A 2 A 3 A 4 A 5 N 0 N 1 N 2 N 3 N 4 N 5 N 6 N 7 N 8 N 9 N 10 N 11 Direction of data input Figure 3 Serial data format C R 0 R 1 R 2 R 3 R ...

Page 13: ...s A0 to A5 of Table 2 1 represent the divide ratio of the swallow counter and columns N0 to N11 of Table2 2 represent the divide ratio of programmable counter Table 2 Divide ratio for the programmable divider Table 2 1 Swallow counter divider A Table2 2 Programmable counter divider N Note Less than 5 is prohibited Divide ratio A A 0 A 1 A 2 A 3 A 4 A 5 Divide ratio N N 0 N 1 N 2 N 3 N 4 N 5 N 6 N ...

Page 14: ...ial data than defined for the target divider are received only the last valid serial data bits are effective To set the divide ratio for the MB15C02 dividers it is necessary to supply the Data Clock and LE signals at the timing shown in Figure 5 t1 1 µs Data setup time t2 1 µs Data hold time t3 µs Clock pulse width t4 1 µs LE setup time to the rising edge of last clock t5 1 µs LE pulse width Divid...

Page 15: ...ference divider set LE to H level before setting the divide ratio for the other dividers e g programmable divider To change the divide ratio of one of the divider after initialization input the serial data only for that divider the divide ratio for the other divider is preserved Figure 6 Inputting serial data Setting divisors Data Clock LE Serial data for program mable reference divider 1 0 Serial...

Page 16: ...500 600 700 800 900 1000 fin input frequency vs Input sensitivity fin input frequency MHz Ta 25 C V DD 1 0 V V DD 1 2 V V DD 1 3 V V DD 1 5 V Input sensitivity dBm 20 0 10 0 0 0 10 0 20 0 30 0 40 0 50 0 60 0 0 50 100 150 200 250 300 350 400 450 500 OSC IN input frequency vs Input sensitivity OSC IN input frequency MHz Ta 25 C V DD 1 0 V V DD 1 2 V V DD 1 3 V V DD 1 5 V ...

Page 17: ...0 100 0 0 9 1 0 1 1 1 2 1 3 1 4 1 6 1 7 1 8 Power supply voltage vs fin input frequency Power supply voltage V Ta 25 C Vfin 2 0 dBm 1 5 Input frequency MHz 500 450 400 350 300 250 200 150 100 50 0 0 9 1 0 1 1 1 2 1 3 1 4 1 6 1 7 1 8 Power supply voltage vs OSC IN input frequency Power supply voltage V Ta 25 C Vfin 2 0 dBm 1 5 ...

Page 18: ...r Supply Current 5 0 4 5 4 0 3 5 3 0 2 5 2 0 1 5 1 0 0 5 0 0 I DD mA Input frequency vs power supply current Ta 25 C 0 100 200 300 400 500 600 700 800 900 1000 Input frequency MHz V DD 1 0 V V DD 1 2 V V DD 1 3 V V DD 1 5 V ...

Page 19: ... 2 5 2 0 1 5 1 0 0 5 0 0 0 8 0 9 1 0 1 1 1 2 1 3 1 5 1 6 1 7 1 8 V DD V p vs I OL at V OL 0 2 V V DD V Ta 25 C 1 4 I OL mA 5 0 4 5 4 0 3 5 3 0 2 5 2 0 1 5 1 0 0 5 0 0 0 8 0 9 1 0 1 1 1 2 1 3 1 5 1 6 1 7 1 8 V DD V p vs I OH at V OH V DD 0 2 V V DD V Ta 25 C 1 4 I OH mA ...

Page 20: ...0 kHz 85 50 dB LOCK Frequency 286 0 MHz fr 25 kHz V DD 1 2 V V p 1 2 V Ta 25 C ATTEN 10 dB RL 0 dBm UAUG 50 10dB MKR 53 84 dB 800 Hz CENTER 286 00000 MHz RBW 100 Hz VBW 100 kHz SPAN 20 00 kHz SWP 3 00 s D S MKR 800 Hz 53 84 dB LOCK Frequency 286 0 MHz fr 25 kHz VDD 1 2 V V p 1 2 V Ta 25 C D O VT to VCO 6800 pF 68000 pF 4700 pF 15 kΩ 4 3 kΩ VCO K V 6 MHz v Test circuit ...

Page 21: ...ms 4 00 ms MKr A euts N A x 6 19999943 ms y 4 00082 MHz 290 0050 MHz 2 00 kHz div 289 9950 MHz 0 s 10 0000000 ms 6 20 ms LOCK Frequency 290 0 MHz to 286 0 MHz fr 25 kHz VDD 1 2 V VP 1 2 V Ta 25 C 290 0 MHz 286 0 MHz within 1 kHz LOCK Frequency 286 0 MHz to 290 0 MHz fr 25 kHz VDD 1 2 V VP 1 2 V Ta 25 C 286 0 MHz 290 0 MHz within 1 kHz ...

Page 22: ...pply off before inserting or removing the device from its socket Protect leads with a conductive sheet when handling or transporting PC boards with devices ORDERING INFORMATION Parts number Package Remarks MB15C02PFV1 16 pin Plastic SSOP FPT 16P M05 MB15C02PFV2 20 pin Plastic SSOP FPT 20P M03 MKr A euts N A x 1 99999978 ms y 680 Hz 286 0050 MHz 2 00 kHz div 285 9950 MHz 0 s 8 0000000 ms 2 00 ms PS...

Page 23: ...15 006 0256 0047 173 004 252 008 NOM 6 40 0 20 4 40 0 10 5 40 213 0 65 0 12 5 00 0 10 197 004 4 55 179 REF Details of A part 0 10 STAND OFF 0 10 0 10 004 004 020 008 0 50 0 20 1994 FUJITSU LIMITED F16013S 2C 4 C FPT 16P M05 These dimensions do not include resin protrusion Dimensions in mm inches Mounting height 16 pins Plastic SSOP ...

Page 24: ...6 0047 173 004 252 008 NOM 6 40 0 20 4 40 0 10 5 40 213 0 65 0 12 6 50 0 10 256 004 5 85 230 REF Details of A part 0 10 STAND OFF 0 10 0 10 004 004 020 008 0 50 0 20 1994 FUJITSU LIMITED F20012S 2C 4 C FPT 20P M03 These dimensions do not include resin protrusion Dimensions in mm inches Mounting height 20 pins Plastic SSOP ...

Page 25: ...25 MB15C02 MEMO ...

Page 26: ...26 MB15C02 MEMO ...

Page 27: ...27 MB15C02 MEMO ...

Page 28: ... this document including descriptions of function and schematic diagrams shall not be construed as license of the use or exercise of any intellectual property right such as patent right or copyright or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non infringement of any third party s intellectual property right or other right by using such...

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