Fujitsu EVB JADE--D Manual Download

Page: 24 / 45

Preliminary

24(45)

Prepared

Document Number

Manfred Ortmann

Approved

Checked

Date

Revision

Storage

20091005

PA 4.2

Mycable01

Pin

Signal

Function

JADE_VO0_13

Digital RGB output 0 Data G3

VIN0_5

Video Capture Data

JADE_VO0_20

Digital RGB output 0 Data B4

VIN0_6

Video Capture Data

JADE_VO0_17

Digital RGB output 0 Data G7

VIN0_1

Video Capture Data

JADE_VO0_12

Digital RGB output 0 Data G2

VIN0_2

Video Capture Data

JADE_VO0_8

Digital RGB output 0 Data R4

CCLK0

Video Capture Input Clock

JADE_VO0_16

Digital RGB output 0 Data G6

VIN0_0

Video Capture Data

DCLKO0

Video output interface dot clock output

DCLKIN0

Video output interface dot clock input

JADE_VO0_9

Digital RGB output 0 Data R5

JADE_VO0_6

Digital RGB output 0 Data R2

DE0

DE / CSYNC

JADE_VO0_7

Digital RGB output 0 Data R3

HSYNC0

Video output interface horizontal sync output
Horizontal sync input in external sync mode

JADE_VO0_10

Digital RGB output 0 Data R6

GV0

Video output interface graphics / video switch

JADE_VO0_11

Digital RGB output 0 Data R7

VSYNC0

Video output interface vertical sync output.
Vertical sync input in external sync mode

JADE_IO_G1_22

DOUTB1_3 / MEM_XWR_3 / DOUTB0_1

JADE_IO_G1_20

DOUTB1_5 / MEM_ED_17 / DOUTG0_1

JADE_IO_G1_21

DOUTB1_4 / MEM_ED_16 / DOUTG0_0

JADE_IO_G1_23

DOUTB1_2 / MEM_XWR_2 / DOUTB0_0

JADE_IO_G1_18

DOUTB1_7 / MEM_ED_19 / DOUTR0_1

JADE_IO_G1_16

DOUTG1_3 / MEM_ED_21 / GPIO_PD_7

JADE_IO_G1_17

DOUTG1_2 / MEM_ED_20 / GPIO_PD_6

100

JADE_IO_G1_19

DOUTB1_6 / MEM_ED_18 / DOUTR0_0

101

JADE_IO_G1_14

DOUTG1_5 / MEM_ED_23 / GPIO_PD_9

102

JADE_IO_G1_12

DOUTG1_7 / MEM_ED_25 / GPIO_PD_11

103

JADE_IO_G1_13

DOUTG1_6 / MEM_ED_24 / GPIO_PD_10

Summary of Contents for EVB JADE--D

Page 1: ...Manfred Ortmann Approved Checked Date Revision Storage 2009 10 05 PA 4 2 Mycable01 Receiver Info M Carstens Behrens mycable GmbH Manual EVB JADE D Interface Board Version PA4 2 October 5 2009 http www fujitsu com emea services microelectronics ...

Page 2: ...eral use including unrestricted ordinary industrial use general office use personal use and household use but are not designed developed and manufactured for use accompanying fatal risks or dangers that unless extremely high safety levels are ensured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss i e nuclear reaction ...

Page 3: ... board version PA 4 for evaluation and development purpose Enclosures None Product Information A JADE Evaluation board was developed to demonstrate the versatile features from the JADE and its interfaces The JADE together with DDR SDRAM and Flash memory is implemented as module which is called XXSvideo and can be plugged on the JADE Evaluation board Now also a module with the JADE D is available I...

Page 4: ...mo Documentation after finishing PCB PA3 2 2009 05 15 mo Pin table of X804 added PA3 3 2009 07 06 mo Pictures added PA4 1 2009 08 14 mo PCB revision PA4 video connector X804 APIX connector X802 PA4 2 2009 10 05 mo Picture change Contact Information mycable GmbH Michael Carstens Behrens hardware and commercial Email mcb mycable de Tel 49 4321 55956 55 mycable GmbH Carsten Schneider Software Email c...

Page 5: ... BOARD 7 2 1 System Architecture 7 2 2 Function Units 9 2 2 1 XXSvideo D Module 10 2 2 2 XXSvideo D Interface 11 2 2 3 XXSvideo Interface 21 2 2 4 Configuration 30 2 2 5 ADC Interface 30 2 2 5 I2C and Host SPI Interface 32 2 2 6 32 bit Flash Memory 33 2 2 7 USB 33 2 2 8 Audio CODEC 34 2 2 9 APIX 35 2 2 10 Video Output 37 2 2 11 RGB Input 40 2 3 Hardware Variants 41 2 4 Placement of Components 42 2...

Page 6: ...ering System architecture description and users manual Hardware architecture Mechanical information References to further information like design data data sheets software documentation It is the engineer s reference for evaluation system development and prototyping based on the board This document covers all available hardware versions regarding their configuration options and revision state 1 2 ...

Page 7: ...roved Checked Date Revision Storage 2009 10 05 PA 4 2 Mycable01 2 EVB JADE D Interface Board 2 1 System Architecture Picture 2 2 shows the top side of the EVB JADE D Interface board and picture 2 3 shows the bottom side Pic 2 2 EVB JADE D Interface board top side ...

Page 8: ...Preliminary 8 45 Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 2009 10 05 PA 4 2 Mycable01 Pic 2 3 EVB JADE D Interface board bottom side ...

Page 9: ...ed Document Number Manfred Ortmann Approved Checked Date Revision Storage 2009 10 05 PA 4 2 Mycable01 2 2 Function Units Overview in the available interfaces RGB Input 32 bit Flash memory USB Audio Connectors ADC Host SPI I2C ...

Page 10: ...ry 10 45 Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 2009 10 05 PA 4 2 Mycable01 2 2 1XXSvideo DModule Pic 2 4 XXSvideo D Module top side Pic 2 5 XXSvideo D Module bottom side ...

Page 11: ... and memory Detailed information on the XXSvideo D module see the manual to this board Do not plug the XXSvideo D module or EVB JADE D when the power supply is on Following tables shows the assignment from pins signals and function of these connectors Mostly the function is no further elucidated and only the name of the connected pin of the JADE D is stated For further details see the datasheet fr...

Page 12: ...Data 6 VCC33 Power Supply 3 3 V for XXSvideo D 7 CPU_A1 Address 8 GND Ground 9 CPU_A3 Address 10 CPU_D0 Data 11 CPU_A4 Address 12 CPU_D3 Data 13 CPU_A7 Address 14 CPU_D4 Data 15 CPU_A8 Address 16 CPU_D7 Data 17 CPU_A11 Address 18 CPU_D8 Data 19 CPU_A12 Address 20 CPU_D11 Data 21 CPU_A15 Address 22 CPU_D12 Data 23 CPU_A16 Address 24 CPU_D14 Data 25 CPU_A19 Address 26 CPU_D1 Data 27 CPU_A20 Address ...

Page 13: ...t 1 positive 52 CPU_A13 Address 53 APIX_SDIN3 Serial Data Input 0 negative 54 CPU_A18 Address 55 APIXGND Ground for APIX signals 56 CPU_A17 Address 57 APIX_SDOUT3 Serial Data Output 1 negative 58 HOST_SPI_DI HOST SPI Data Input MOSI 59 APIX_SDOUT2 Serial Data Output 1 positive 60 HOST_SPI_DO HOST SPI Data Output MISO 61 APIX_SDIN1 Serial Data Input 0 negative 62 HOST_SPI_SS HOST SPI Slave Select 6...

Page 14: ...7 VIN0_8 Video Capture 0 Clock 88 HSYNC0 Video Capture 0 Horizontal Syncronisation 89 VIN0_0 Video Capture Data Input 0 bit 0 90 GVO0 Video output interface 0 graphics video switch 91 TSG_R_7 TCON Timing Signal 92 VSYNC0 TCON Bypass Video output interface 0 vertical sync output vertical sync input in external sync mode 93 ATST_R APIX analog Test Clock 94 DOUTB1_R_5 Digital RGB output1 with serial ...

Page 15: ...al RGB output1 with serial resistor 114 VINHSYNC0 Video Capture 0 Horizontal Syncronisation 115 DOUTR1_R_6 Digital RGB output1 with serial resistor 116 VINVSYNC1 Video Capture 1 Vertical Syncronisation 117 VSYNC1 Video output interface 1 vertical sync output vertical sync input in external sync mode 118 VINFID0 Video input 0 field identification signal 119 HSYNC1 Video output interface 1 horizonta...

Page 16: ...C_SDA1 I2C 1 Data 12 I2C_SCL1 I2C 1 Clock 13 INT_A3 Interrupt 3 14 SPI_DO1 SPI1 Master Data Output MOSI 15 INT_A2 Interrupt 2 16 SPI_DI1 SPI1 Master Data Input MISO 17 TSG_R_10 TCON Timing Signal 10 18 TSG_R_8 TCON Timing Signal 8 19 TSG_R_11 TCON Timing Signal 11 20 TSG_R_9 TCON Timing Signal 9 21 SPI_SCK1 SPI1 Master serial clock 22 UART_SOUT1 UART 1 serial output 23 SPI_SS1 SPI1 Master Slave Se...

Page 17: ..._N_R_10 RSDS Output 10n in TTL Mode Default DOUTB0_5 46 VCC12 1 2 V from CPU core voltage regulator 47 DISP_P_R_7 RSDS Output 7p in TTL Mode Default DOUTG0_6 48 VCC12 1 2 V from CPU core voltage regulator 49 DISP_N_R_7 RSDS Output 7n in TTL Mode Default DOUTG0_7 50 DISP_P_R_0 RSDS Output 0p in TTL Mode Default DOUTR0_0 51 DISP_P_R_8 RSDS Output 8p in TTL Mode Default DOUTB0_0 52 DISP_N_R_0 RSDS Ou...

Page 18: ...ansmission 1 69 VIN1_9 Video Capture Data Input 1 bit 6 70 DISP_P_R_5 RSDS Output 5p in TTL Mode Default DOUTG0_2 71 I2S_WS 72 DISP_N_R_5 RSDS Output 5n in TTL Mode Default DOUTG0_3 73 VIN1_3 Video Capture Data Input 1 bit 3 74 DISP_P_R_6 RSDS Output 6p in TTL Mode Default DOUTG0_4 75 VIN1_0 Video Capture Data Input 1 bit 0 76 DISP_N_R_6 RSDS Output 6n in TTL Mode Default DOUTG0_5 77 VIN1_10 Video...

Page 19: ... Clock 100 VINFID1 Video input 1 field identification signal 101 TMS JTAG TMS 102 JTAGSEL JTAG Selector 0 Fujitsu TAP Controller 1 ARM Tap Controller 103 TDO JTAG TDO 104 XSRST ICE System reset 105 TRACEDATA_0 Trace data used by the trace tool such as RealView supplied by ARM Limited 106 XTRST Test reset 107 TRACEDATA_2 Trace data used by the trace tool such as RealView supplied by ARM Limited 108...

Page 20: ...D for DDR2 SDRAM 119 TRACECLK Trace clock 120 VCC18 1 8 V regulated on XXSvideo D for DDR2 SDRAM 121 GND Ground at center pin 122 GND Ground at center pin 123 GND Ground at center pin 124 GND Ground at center pin 125 GND Ground at center pin 126 GND Ground at center pin 127 GND Ground at center pin 128 GND Ground at center pin Tab 2 2 Pin assignment of connector X201 I O signals side ...

Page 21: ...ation board These interfaces are specified for the XXSvideo module with the JADE Evaluation board Mostly the function is no further elucidated and only the name of the connected pin of the JADE is stated For further details see the datasheet from the JADE and the schematic of the XXSvideo module Signals with the name JADE_IO_Gn are connected to multi function pins of the JADE N indicate the functi...

Page 22: ... 3 V for XXSvideo 5 GND Ground 6 GND Ground 7 GND Ground 8 GND Ground 9 CPU_D15 Data 10 CPU_D0 Data 11 CPU_A1 Address 12 CPU_D3 Data 13 CPU_A3 Address 14 CPU_D4 Data 15 CPU_A4 Address 16 CPU_D7 Data 17 CPU_A7 Address 18 CPU_D8 Data 19 CPU_A8 Address 20 CPU_D11 Data 21 CPU_A11 Address 22 CPU_D12 Data 23 CPU_A12 Address 24 CPU_D14 Data 25 CPU_A15 Address 26 CPU_D1 Data 27 CPU_A16 Address 28 CPU_D2 D...

Page 23: ... CPU_A14 Address 51 MEM_RDY Ready input for slow device 52 CPU_A13 Address 53 JADE_VO0_23 Digital RGB output 0 Data B7 54 CPU_A18 Address 55 JADE_VO0_22 Digital RGB output 0 Data B6 56 CPU_A17 Address 57 JADE_VO0_18 Digital RGB output 0 Data B2 58 JADE_IO_G4_28 IDE_DD_3 GPIO_PD_15 59 JADE_VO0_19 Digital RGB output 0 Data B3 60 JADE_IO_G4_29 IDE_DD_2 GPIO_PD_14 61 JADE_VO0_14 Digital RGB output 0 D...

Page 24: ...DE_VO0_6 Digital RGB output 0 Data R2 86 DE0 DE CSYNC 87 JADE_VO0_7 Digital RGB output 0 Data R3 88 HSYNC0 Video output interface horizontal sync output Horizontal sync input in external sync mode 89 JADE_VO0_10 Digital RGB output 0 Data R6 90 GV0 Video output interface graphics video switch 91 JADE_VO0_11 Digital RGB output 0 Data R7 92 VSYNC0 Video output interface vertical sync output Vertical ...

Page 25: ...EM_ED_28 I2S_SDI0 108 JADE_IO_G1_11 DOUTR1_2 MEM_ED_26 GPIO_PD_12 109 JADE_IO_G1_6 DOUTR1_7 MEM_ED_31 I2S_ECLK0 110 JADE_IO_G1_1 DCLKO1 111 JADE_IO_G1_7 DOUTR1_6 MEM_ED_30 I2S_SCK0 112 JADE_IO_G1_5 GV1 DREQ_7 DREQ_7 113 JADE_IO_G1_4 VSYNC1 XDACK_6 XDACK_6 114 USB_PWR_CTRL USB Port Power Control 115 JADE_IO_G1_3 HSYNC1 DREQ_6 DREQ_6 116 USB_DP D for HS and FS 117 JADE_IO_G1_2 DE1 XDACK_7 XDACK_7 11...

Page 26: ...r XXSvideo 4 VCC33 Power Supply 3 3 V for XXSvideo 5 GND Ground 6 GND Ground 7 GND Ground 8 GND Ground 9 INT_A0 INT_A0 10 I2C1 I2C_SDA0 11 INT_A1 INT_A1 12 I2C0 I2C_SCL0 13 I2C3 I2C_SDA1 14 I2C2 I2C_SCL1 15 INT_A3 INT_A3 16 SD_CARD7 SD_XMCD 17 INT_A2 INT_A2 18 SD_CARD6 SD_WP 19 SD_CARD5 SD_DAT3 20 SD_CARD3 SD_DAT1 21 SD_CARD4 SD_DAT2 22 SD_CARD2 SD_DAT0 23 SD_CARD0 SD_CLK 24 UART5 UART_SOUT1 25 SD...

Page 27: ...ltage regulated on XXSvideo 49 JADE_IO_G4_8 IDE_DA_1 PWMO1 50 JADE_IO_G4_10 IDE_XDCS_1 51 JADE_IO_G4_24 IDE_DD_7 GPIO_PD_19 52 JADE_IO_G4_11 IDE_XDCS_0 53 JADE_IO_G4_25 IDE_DD_6 GPIO_PD_18 54 JADE_IO_G4_14 IDE_CSEL 55 JADE_IO_G4_20 IDE_DD_11 GPIO_PD_23 56 JADE_IO_G4_9 IDE_DA_0 PWMO0 57 JADE_IO_G4_21 IDE_DD_10 GPIO_PD_22 58 JADE_IO_G4_27 IDE_DD_4 GPIO_PD_16 59 JADE_IO_G4_16 IDE_DD_15 CAN_TX0 60 JAD...

Page 28: ...SYNC1 I2S_ECLK1 I2S_ECLK1 I2S_ECLK1 78 JADE_IO_G4_5 IDE_XCBLID I2S_SCK1 79 JADE_IO_G2_21 I2S_SDI0 BI1_2 I2S_SDI2 SPI_DI I2S_SDI2 80 JADE_IO_G2_15 PWMO0 GI1_2 GPIO_PD_3 GPIO_PD_3 GPIO_PD_3 81 JADE_IO_G2_10 VIN1_4 RI1_4 CAN_RX0 CAN_RX0 CAN_RX0 82 JADE_IO_G2_18 I2S_ECLK0 BI1_5 I2S_ECLK2 reserved GPIO_PD_0 83 JADE_IO_G2_13 VIN1_1 GI1_7 I2S_SCK1 I2S_SCK1 I2S_SCK1 84 JADE_IO_G2_16 PWMO1 BI1_7 GPIO_PD_2 ...

Page 29: ...ODE USB_MODE 101 JTAG4 TMS 102 JTAGSEL JTAGSEL 103 JTAG6 TDO 104 JTAG1 XSRST 105 JADE_IO_G5_0 TRACECLK UART_SIN3 UART_SIN3 106 JTAG3 XTRST 107 JADE_IO_G5_2 TRACEDATA_3 UART_SIN4 UART_SIN4 108 JTAG5 TDI 109 JADE_IO_G5_4 TRACEDATA_1 UART_SIN5 PWMO1 110 VCC_CORE_PG VCC_CORE_PG Pin 11 LTC3417 U200 Power good VCC12 and VCC18 111 JADE_IO_G5_1 TRACECTL UART_SOUT3 UART_SOUT3 112 MR MR Pin 3 ADM6320 U201Ma...

Page 30: ...als side 2 2 4Configuration R201 R204 R301 R306 R401 R408 2 2 5ADCInterface Pic 2 8 ADC interface The pins of the ADC interface from the JADE D on the XXSvideo D are available at connector X805 FTSH 106 01 L DV from Samtec At AD_VR0 and AD_VR1 are capacitors with 100 nF to Ground connected Resistors R840 R845 with connection to AD_VRH0 AD_VRL0 AD_VRH1 and AD_VRL1 can be populated As default these ...

Page 31: ...PA 4 2 Mycable01 Following table shows the assignment of pins signals and function from the connector X805 Pin Signal Function 1 AD_VRH0 2 AD_VRL0 3 AD_VIN0 4 AD_VR0 5 AD_VRH1 6 AD_VRL1 7 AD_VIN1 8 AD_VINR1 9 AD_VIN2 10 AD_VIN3 11 ADCGND ADC Ground 12 ADCGND ADC Ground Tab 2 5 Pin assignment of connector X805 ...

Page 32: ... D on the XXSvideo D are available at connector X806 FTSH 106 01 L DV from Samtec Following table shows the assignment of pins signals and function from the connector X806 Pin Signal Function 1 Not connected 2 I2C_SDA1 SDA from I2C interface 1 3 I2C_SCL1 SCL from I2C interface 1 4 GND Ground 5 HOST_SPI_SCK 6 GND Ground 7 HOST_SPI_DI 8 GND Ground 9 HOST_SPI_DO 10 GND Ground 11 HOST_SPI_SS 12 VCC33 ...

Page 33: ... switch SW901 on JADE Evaluation board 2 2 7USB A USB 2 0 high speed mode host and device controller LSI with 16 bit width standard CPU bus S1R72V18 U601 from Seiko Epson Corporation is populated The S1R72V18 has two host ports to function as a USB root hub One of the ports can be used as a USB device port after setting On the EVB JADE D Interface board only the host port will be used The interrup...

Page 34: ...ering decimation Sampled data is transmitted by the serial audio interface at rates from 4 kHz to 192 kHz in either Slave or Master Mode The D A converter is based on a 4th order multi bit delta sigma modulator with an ultra linear low pass filter and offers a volume control that operates with a 0 5 dB step size It incorporates selectable soft ramp and zero crossing transition functions to elimina...

Page 35: ...P copper cable The downlink channel provides a sustained data rate of up to 1 Gbit s another 18 Mbit s can be transmitted simultaneously in uplink direction The APIX interface 0 from the JADE D is connected to connector X801 with pinning for input side The APIX interface 1 from the JADE D is connected to connector X802 with pinning for output side On revision PA3 both connectors have input pinning...

Page 36: ...ansmission line 5 SDOUT0_M CML serial data interface upstream Interface to differential transmission line 6 NC Not connected 7 NC Not connected 8 NC Not connected Tab 2 7 Pin assignment of input connector X801 Pin Signal Function 1 SDOUT1_P CML serial data interface upstream Interface to differential transmission line 2 SDOUT1_M CML serial data interface upstream Interface to differential transmis...

Page 37: ...ignals are connected to the JADE Evaluation board connector X301 over 0 Ohm resistors So the RGB interface 0 on the JADE Evaluation board can be used If the TCON interface will be used and the long connection to the JADE Evaluation board make disruptions remove the 0 Ohm resistors On revision PA3 the pin 3 to 14 have another order Pin Signal Function 1 GND Ground 2 NC Testpoint 801 3 DISP_N_R_11 D...

Page 38: ... DOUTG0_2 15 GND 16 DISP_SYNC_R_3 DCLKP 17 DISP_SYNC_R_4 DCLKN 18 NC Testpoint 802 19 NC Testpoint 800 20 DISP_P_R_3 DOUTR0_6 21 DISP_N_R_3 22 DISP_P_R_2 DOUTR0_4 23 DISP_N_R_2 24 DISP_P_R_1 DOUTR0_2 25 DISP_N_R_1 26 DISP_P_R_8 27 DISP_N_R_8 28 DISP_P_R_4 29 DISP_N_R_4 30 DISP_P_R_0 31 DISP_N_R_0 32 TSG_R_4 33 TSG_R_5 34 TSG_R_6 35 TSG_R_7 36 TSG_R_8 37 TSG_R_9 38 TSG_R_10 39 TSG_R_11 40 GND 41 TS...

Page 39: ... Revision Storage 2009 10 05 PA 4 2 Mycable01 Pin Signal Function 42 GND 43 DISP_SYNC_R_0 HSYNC0 44 DISP_SYNC_R_1 VSYNC0 45 DISP_SYNC_R_2 GVO0 46 Testpoint 803 47 GND Ground 48 Testpoint 804 49 DISP_SYNC_R_5 DE0 50 VCC33 3 3 V output voltage Tab 2 9 Pin assignment of connector X804 ...

Page 40: ...terface board The AD9883A is a complete 8 bit 140 MSPS monolithic analog interface optimized for capturing RGB graphics signals Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports resolutions up to SXGA 1280 1024 at 75 Hz The AD9883A includes a 140 MHz triple ADC with internal 1 25 V reference a PLL and programmable gain offset and clamp control This interface i...

Page 41: ...N2_BLUE Analog Blue Signal 4 NC Not connected 5 GND Ground 6 GND Ground 7 GND Ground 8 GND Ground 9 NC Not connected 10 GND Ground 11 NC Not connected 12 NC Not connected 13 AVIN2_HSYNC Horizontal Sync Signal 14 AVIN2_VSYNC Vertical Sync Signal 15 NC Not connected Tab 2 10 Pin assignment of connector X900 2 3 Hardware Variants Prototypes have the version PA3 For this revision PA4 hardware variants...

Page 42: ...09 10 05 PA 4 2 Mycable01 2 4 Placement of Components The placement of components on the EVB JADE D Interface board is shown below Pictures from placement of components with a better resolution are available as separate pdf documents Pic 2 6 EVB JADE D Interface board placement of components top side ...

Page 43: ...Preliminary 43 45 Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 2009 10 05 PA 4 2 Mycable01 Pic 2 7 EVB JADE D Interface board placement of components bottom side ...

Page 44: ... Storage 2009 10 05 PA 4 2 Mycable01 2 5 Mechanical Dimensions The EVB JADE D Interface board has a size of 142 0 x 100 0 mm Pictures from mechanical dimensions with a better resolution are available as separate pdf documents Pic 2 8 EVB JADE D Interface board mechanical dimensions top side ...

Page 45: ...Preliminary 45 45 Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 2009 10 05 PA 4 2 Mycable01 Pic 2 8 EVB JADE D Interface board mechanical dimensions bottom side ...

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