Fujitsu DISK DRIVES MHL2300AT Product Manual Download Page 199

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Interface

5-122

C141-E104-03EN

5.6.4 Power-on and reset

Figure 5.22 shows power-on and reset (hardware and software reset) timing.

(1) Only master device is present

(2) Master and slave devices are present (2-drives configuration)

Figure 5.22 Power on Reset Timing

Power-on Reset
RESET–

PDIAG- negation

Summary of Contents for DISK DRIVES MHL2300AT

Page 1: ...C141 E104 03EN MHL2300AT MHM2200AT MHM2150AT MHM2100AT DISK DRIVES PRODUCT MANUAL ...

Page 2: ...mes no liability to any party for any damage caused by any error or omission contained in this manual its updates or supplements whether such errors or omissions result from negligence accident or any other cause In addition FUJITSU assumes no liability with respect to the application or use of any product or system in accordance with the descriptions or instructions contained herein including any...

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Page 4: ... in Section 5 3 2 Table 5 17 Specification Number of Sections for MHL2300AT was altered Order No was changed SET MAX commands are added Values of host termination for DIOR DIOW and DMACK signals are changed 03 2000 12 13 Figure 3 1 Tolerances of measurement have been corrected 1 Section s with asterisk refer to the previous edition when those were deleted ...

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Page 6: ...MHL Series and MHM Series and describes their features CHAPTER 2 Device Configuration This chapter describes the internal configurations of the MHL Series and MHM Series and the configuration of the systems in which they operate CHAPTER 3 Installation Conditions This chapter describes the external dimensions installation conditions and switch settings of the MHL Series and MHM Series CHAPTER 4 The...

Page 7: ...alert signal is centered followed below by the indented message A wider line space precedes and follows the alert message to show where the alert message begins and ends The following is an example Example CAUTION Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields The main alert mes...

Page 8: ...nvolve adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system or other causes outside the disk drive ...

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Page 10: ...t perform the procedure correctly Task Alert message Page Normal Operation Data corruption Avoid mounting the disk near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When h...

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Page 12: ...ES PRODUCT MANUAL C141 E104 This manual Device Overview Device Configuration Installation Conditions Theory of Device Operation Interface Operations MHL2300AT MHM2200AT MHM2150AT MHM2100AT DISK DRIVES MAINTENANCE MANUAL C141 F043 Maintenance and Diagnosis Removal and Replacement Procedure ...

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Page 14: ...ns summary 1 4 1 2 2 Model and product number 1 5 1 3 Power Requirements 1 5 1 4 Environmental Specifications 1 7 1 5 Acoustic Noise 1 8 1 6 Shock and Vibration 1 8 1 7 Reliability 1 9 1 8 Error Rate 1 10 1 9 Media Defects 1 10 CHAPTER 2 Device Configuration 2 1 2 1 Device Configuration 2 2 2 2 System Configuration 2 4 2 2 1 ATA interface 2 4 2 2 2 1 drive connection 2 4 2 2 3 2 drives connection ...

Page 15: ... default setting 3 13 3 4 3 Master drive slave drive setting 3 13 3 4 4 CSEL setting 3 14 CHAPTER 4 Theory of Device Operation 4 1 4 1 Outline 4 2 4 2 Subassemblies 4 2 4 2 1 Disk 4 2 4 2 2 Head 4 2 4 2 3 Spindle 4 3 4 2 4 Actuator 4 3 4 2 5 Air filter 4 3 4 3 Circuit Configuration 4 4 4 4 Power on Sequence 4 7 4 5 Self calibration 4 8 4 5 1 Self calibration contents 4 8 4 5 2 Execution timing of ...

Page 16: ...gnment on the connector 5 3 5 2 Logical Interface 5 6 5 2 1 I O registers 5 7 5 2 2 Command block registers 5 8 5 2 3 Control block registers 5 13 5 3 Host Commands 5 13 5 3 1 Command code and parameters 5 14 5 3 2 Command descriptions 5 16 5 3 3 Error posting 5 83 5 4 Command Protocol 5 85 5 4 1 Data transferring commands from device to host 5 85 5 4 2 Data transferring commands from host to devi...

Page 17: ...ination required for Ultra DMA 5 106 5 6 Timing 5 107 5 6 1 PIO data transfer 5 107 5 6 2 Multiword DMA data transfer 5 109 5 6 3 Transfer of Ultra DMA data 5 110 5 6 3 1 Starting of Ultra DMA data In Burst 5 110 5 6 3 2 Ultra DMA data burst timing requirements 5 111 5 6 3 3 Sustained Ultra DMA data in burst 5 113 5 6 3 4 Host pausing an Ultra DMA data in burst 5 114 5 6 3 5 Device terminating an ...

Page 18: ... Power Save 6 9 6 3 1 Power save mode 6 9 6 3 2 Power commands 6 11 6 4 Defect Management 6 11 6 4 1 Spare area 6 12 6 4 2 Alternating defective sectors 6 12 6 5 Read Ahead Cache 6 14 6 5 1 Data buffer configuration 6 14 6 5 2 Caching operation 6 14 6 5 3 Usage of read segment 6 16 6 5 3 1 Mis hit no hit 6 16 6 5 3 2 Sequential read 6 17 6 5 3 3 Full hit hit all 6 20 6 5 3 4 Partially hit 6 21 6 6...

Page 19: ...le MHL2300AT 3 10 Figure 3 9 Cable connections 3 11 Figure 3 10 Power supply connector pins CN1 3 12 Figure 3 11 Jumper location 3 12 Figure 3 12 Factory default setting 3 13 Figure 3 13 Jumper setting of master or slave device 3 13 Figure 3 14 CSEL setting 3 14 Figure 3 15 Example 1 of Cable Select 3 14 Figure 3 16 Example 2 of Cable Select 3 15 Figure 4 1 Head structure 4 3 Figure 4 2 Power Supp...

Page 20: ...gure 5 18 Sustained Ultra DMA data out burst 5 118 Figure 5 19 Device pausing an Ultra DMA data out burst 5 119 Figure 5 20 Host terminating an Ultra DMA data out burst 5 120 Figure 5 21 Device terminating an Ultra DMA data out burst 5 121 Figure 5 22 Power on Reset Timing 5 122 Figure 6 1 Response to power on 6 3 Figure 6 2 Response to hardware reset 6 4 Figure 6 3 Response to software reset 6 5 ...

Page 21: ...e 5 8 Format of device attribute value data 5 68 Table 5 9 Format of insurance failure threshold value data 5 68 Table 5 10 SMART error log data format 5 72 Table 5 11 SMART self test log data format 5 74 Table 5 12 Contents of security password 5 76 Table 5 13 Contents of SECURITY SET PASSWORD data 5 80 Table 5 14 Relationship between combination of Identifier and Security level and operation of ...

Page 22: ...1 6 Shock and Vibration 1 7 Reliability 1 8 Error Rate 1 9 Media Defects Overview and features are described in this chapter and specifications and power requirement are described The MHL Series and MHM Series are 2 5 inch hard disk drives with built in disk controllers These disk drives use the AT bus hard disk interface protocol and are compact and reliable ...

Page 23: ...eed Transfer rate The disk drives the MHL Series and MHM Series have an internal data rate up to 28 7 MB s The disk drive supports an external data rate up to 66 6 MB s U DMA mode 4 4 Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed The average positioning time is 12 ms at read 1 1 2 Adaptability 1 Power save mode T...

Page 24: ... access But if the read ahead data corresponds to the data requested by the next read command the data in the buffer can be transferred instead 4 Master slave The disk drives the MHL Series and MHM Series can be connected to ATA interface as daisy chain configuration Drive 0 is a master device drive 1 is a slave device 5 Error correction and retry by ECC If a recoverable error occurs the disk driv...

Page 25: ...ding Method 16 17 MTR Track Density 32 300 TPI 1271 track mm Bit Density 499 7 Kbpi 19 67 k bit mm Rotational Speed 4 200 rpm 1 Average Latency 7 14 ms Positioning time read and seek Minimum Track to Track Average Maximum Full 1 5 ms typ Read 12 ms typ 22 ms typ Start Stop time Start 0 rpm to Drive Read Stop at Power Down Typ 5 sec Typ 5 sec Interface ATA 5 Max Cable length 0 46 m Data Transfer Ra...

Page 26: ...AT 8 45 GB 16 383 16 63 MHM2100AT 8 45 GB 16 383 16 63 1 2 2 Model and product number Table 1 2 lists the model names and product numbers of the MHL Series and MHM Series Table 1 2 Model names and product numbers Model Name Capacity user area Mounting screw Order No MHL2300AT 30 GB M3 depth 3 CA05428 B061 MHM2200AT 20 GB M3 depth 3 CA05429 B041 MHM2150AT 15 GB M3 depth 3 CA05429 B031 MHM2100AT 10 ...

Page 27: ...y 50 mA 50 mA 0 25 W 0 25 W Sleep 20 mA 20 mA 0 1 W 0 1 W Energy Efficiency 4 0 032 W GB rank E 0 040 W GB rank E MHM2200AT 0 040 W GB rank E MHM2150AT 0 080 W GB rank D MHM2100AT 1 Current at starting spindle motor 2 At 30 disk accessing 3 Power requirements reflect nominal values for 5V power 4 Energy efficiency based on the Law concerning the Rational Use of Energy indicates the value obtained ...

Page 28: ...ed to be concerned with the power on off sequence 1 4 Environmental Specifications Table 1 4 lists the environmental specifications Table 1 4 Environmental specifications Item Specification Temperature Operating Non operating Thermal Gradient 5 C to 55 C ambient 5 C to 60 C disk enclosure surface 40 C to 65 C 20 C h or less Humidity Operating Non operating Maximum Wet Bulb 8 to 90 RH Non condensin...

Page 29: ...tem Specification Vibration swept sine one octave per minute Operating Non operating 5 to 500 Hz 1 0G 0 peak MHL series 5 to 400 Hz 1 0G 0 peak MHM series without non recovered errors 9 8 m s2 0 peak 5 to 500 Hz 5G 0 peak MHL series 5 to 400 Hz 5G 0 peak MHM series no damage 49 m s2 0 peak Shock half sine pulse Operating Non operating 175G 0 peak 1 715 m s2 0 peak 2 ms duration without non recover...

Page 30: ...2 Mean time to repair MTTR The mean time to repair MTTR is 30 minutes or less if repaired by a specialist maintenance staff member 3 Service life In situations where management and handling are correct the disk drive requires no overhaul for five years when the DE surface temperature is less than 48 C When the DE surface temperature exceeds 48 C the disk drives requires no overhaul for five years ...

Page 31: ...ta of 1014 bits Read retries are executed according to the disk drive s error recovery procedure and include read retries accompanying head offset operations 2 Positioning error Positioning seek errors that can be recovered by one retry shall occur no more than 10 times in 107 seek operations 1 9 Media Defects Defective sectors are replaced with alternates when the disk the MHL Series and MHM Seri...

Page 32: ... 1 CHAPTER 2 Device Configuration 2 1 Device Configuration 2 2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate ...

Page 33: ... of disks used varies with the model as described below The disks are rated at over 50 000 start stop operations MHL2300AT 3 disks MHM2200AT 2 disks MHM2150AT 2 disks MHM2100AT 1 disk 2 Head The heads are of the contact start stop CSS type The head touches the disk surface while the disk is not rotating and automatically lifts when the disk starts Figure 2 2 illustrates the configuration of the di...

Page 34: ...tays in the specific CSS zone on the disk and is fixed by a mechanical lock 5 Air circulation system The disk enclosure DE is sealed to prevent dust and dirt from entering The disk enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk This system continuously circulates the air through the circulation filter to maintain the cleanliness of the...

Page 35: ...e 4 transfer at 66 6 MB s 2 2 2 1 drive connection MHC2032AT MHC2040AT Figure 2 3 1 drive system configuration 2 2 3 2 drives connection MHC2032AT MHC2040AT MHC2032AT MHC2040AT Host adaptor Note When the drive that is not conformed to ATA is connected to the disk drive above configuration the operation is not guaranteed Figure 2 4 2 drives configuration MHG2102AT MHH2064AT MHH2032AT MHL2300AT MHM2...

Page 36: ...sstalk of the signal lines AT bus between the HA and the disk drive may be a great cause of the obstruction of system reliability Thus it is necessary that the capacitance of the signal lines including the HA and cable does not exceed the ATA 5 standard and the cable length between the HA and the disk drive should be as short as possible No need to push the top cover of the disk drive If the over ...

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Page 38: ...n Conditions 3 1 Dimensions 3 2 Mounting 3 3 Cable Connections 3 4 Jumper Settings This chapter gives the external dimensions installation conditions surface temperature conditions cable connections and switch settings of the hard disk drives ...

Page 39: ...tion Conditions 3 2 C141 E104 03EN 3 1 Dimensions Figure 3 1 illustrates the dimensions of the disk drive and positions of the mounting screw holes All dimensions are in mm Figure 3 1 Dimensions MHL series 1 2 ...

Page 40: ...3 1 Dimensions C141 E104 03EN 3 3 Figure 3 1 Dimensions MHM series 2 2 ...

Page 41: ...N 3 2 Mounting 1 Orientation Figure 3 2 illustrates the allowable orientations for the disk drive Figure 3 2 Orientation Sample MHL2300AT e Vertical 3 f Vertical 4 c Vertical 1 d Vertical 2 b Horizontal 1 a Horizontal 1 gravity gravity gravity ...

Page 42: ...he system frame do not allow the system frame to touch parts cover and base other than parts to which the HDD is attached 3 Limitation of mounting Do not use the center hole For screw length see Figure 3 3 Note These dimensions are recommended values if it is not possible to satisfy them contact us Figure 3 3 Mounting frame structure Screw Screw Details of B Details of A 3 0 or less 3 0 or less Fr...

Page 43: ...reather hole mounted to the HDD do not allow this to close during mounting Locating of breather hole is shown as Figure 3 4 in both MHL series and MHM series For breather hole of Figure 3 4 at least do not allow its around φ3 to block Figure 3 4 Location of breather ...

Page 44: ...e from exceeding 60 C Provide air circulation in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface temperatures of the DE Regardless of the ambient temperature this surface temperature must meet the standards listed in Table 3 1 Figure 3 5 shows the temperature measurement point Figure 3 5 Surface temperature measuremen...

Page 45: ...the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device disconnect the body ground 500 kΩ or greater Do not touch the printed circuit board but hold it by the edges 6 Handling cautions Please keep the following caut...

Page 46: ...que of the screw strictly M3 0 49 N m 5 Kg cm Recommended equipments Contents Model Maker Wrist strap JX 1200 3056 8 SUMITOMO 3M ESD ESD mat 76000DES ASK7876 COMKYLE Shock Low shock driver SS 3000 HIOS Place the shock absorbing mat on the operation table and place ESD mat on it Use the Wrist strap Do not hit HDD each other Do not stack when carrying Do not place HDD vertically to avoid falling dow...

Page 47: ...tions 3 3 1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices Figure 3 8 shows the locations of these connectors and terminals Figure 3 8 Connector locations Sample MHL2300AT Connector setting pins PCA ...

Page 48: ...ly cable 44 pin type Cable socket 44 pin type 89361 144 BERG IMPORTANT For the host interface cable use a ribbon cable A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines This is because the interface is designed for ribbon cables and not for cables carrying differential signals 3 3 3 Device connection Figure 3 9 shows how to co...

Page 49: ...re 3 10 shows the pin assignment of the power supply connector CN1 Figure 3 10 Power supply connector pins CN1 3 4 Jumper Settings 3 4 1 Location of setting jumpers Figure 3 11 shows the location of the jumpers to select drive configuration and functions Figure 3 11 Jumper location ...

Page 50: ...at the factory Figure 3 12 Factory default setting 3 4 3 Master drive slave drive setting Master drive disk drive 0 or slave drive disk drive 1 is selected b Slave drive a Master drive Open Open Short Open A 1 C B D 2 B D 2 A C 1 Figure 3 13 Jumper setting of master or slave drive Note Pins A and C should be open Open ...

Page 51: ...ction using unique interface cables By connecting the CSEL of the master drive to the CSEL Line conducer of the cable and connecting it to ground further the CSEL is set to low level The drive is identified as a master drive At this time the CSEL of the slave drive does not have a conductor Thus since the slave drive is not connected to the CSEL conductor the CSEL is set to high level The drive is...

Page 52: ...3 4 Jumper Settings C141 E104 03EN 3 15 Figure 3 16 Example 2 of Cable Select drive drive ...

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Page 54: ...4 3 Circuit Configuration 4 4 Power on Sequence 4 5 Self calibration 4 6 Read write Circuit 4 7 Servo Control This chapter explains basic design concepts of the disk drive Also this chapter explains subassemblies of the disk drive each sequence servo control and electrical circuit blocks ...

Page 55: ...r the disk drive The disk drive has one PCA For details see Sections 4 3 4 2 1 Disk The DE contains disks with an outer diameter of 65 mm and an inner diameter of 20 mm The MHL2300AT have three disks and MHM2200AT and MHM2150AT have two disks and MHM2100AT have one disk The head contacts the disk each time the disk rotation stops the disk surface is durable at least 50 000 CSS Contact Start Stop o...

Page 56: ...er edge of the disk The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read write head 4 2 5 Air filter There are two types of air filters a breather filter and a circulation filter The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindl...

Page 57: ... MTR Maximum Transitions Limited encoder Run Length and servo demodulation circuit 2 Servo circuit The position and speed of the voice coil motor are controlled by 2 closed loop servo using the servo information recorded on the data surface The servo information is an analog signal converted to digital for processing by a MPU and then reconverted to an analog signal for control of the voice coil m...

Page 58: ...4 3 Circuit Configuration C141 E104 03EN 4 5 Figure 4 2 Power Supply Configuration 5V 3 3V 3V HDC SVC HDIC MCU FROM RDC SDRAM ...

Page 59: ...Spindle Motor SVC Motor Controller and Driver Write Data Read Data Read Write Preamplifier Servo Pulse and Position Signal Write Data RDC Read Channel SVC Control Signal SDRAM Data Buffer RAM HDIC Control Signal Data Buffer Bus 16 bit 16 bit Local Bus RDC Control Signal Read and Write Data Printed Circuit Board ATA Interface Host Disk Enclosure Head Read Head Write Head Read Data ...

Page 60: ...s data buffer read write test after enabling response to the ATA bus c After confirming that the spindle motor has reached rated speed the disk drive releases the heads from the actuator magnet lock mechanism by applying current to the VCM This unlocks the heads which are parked at the inner circumference of the disks d The disk drive positions the heads onto the SA area and reads out the system i...

Page 61: ...e cylinder where the head is positioned To execute stable fast seek operations external forces are occasionally sensed The firmware of the drive measures and stores the force value of the actuator motor drive current that balances the torque for stopping head stably This includes the current offset in the power amplifier circuit and DAC system Start Self diagnosis 1 MPU bus test Internal register ...

Page 62: ...gain from the position signal and stores the compensation value against to the target gain as ratio For compensating the direction current value to the power amplifier is multiplied by the compensation value By this compensation loop gain becomes constant value and the stable servo control is realized To compensate torque constant value change depending on cylinder whole cylinders from most inner ...

Page 63: ...y the disk drive positions the head to the track requested by the host reads or writes data and restarts calibration This enables the host to execute the command without waiting for a long time even when the disk drive is performing self calibration The command execution wait time is about maximum 40 ms 4 6 Read write Circuit The read write circuit consists of the read write preamplifier HDIC the ...

Page 64: ... MTR MEEPRML This device converts data using the 16 17 MTR Maximum Transitions Run Length Limited algorithm This code is converted so that a maximum of three 1 s are placed continuously and so that there are two or fewer 1 s in a 17 bit border 2 Write precompensation Write precompensation compensates during a write process for write non linearity generated at reading Table 4 2 shows the write prec...

Page 65: ...k diagram HDIC WDX WDY RDX RDY Write PreCompen sation Serial I O Registers Digital PLL Flash Digitizer MEEPR Viterbi Detect 16 17 ENDEC ServoPulse Detector Programmable Filter AGC Amplifier RDC SD SC SE Position A B C D to reg WTGATE REFCLK RDGATE DATA 7 0 RWCLK SRV_OUT 1 0 SRV_CLK ...

Page 66: ...es The AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer inner head positions 2 Programmable filter circuit The programmable filter circuit has a low pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost up function that equalizes the waveform of the read signal C...

Page 67: ...it converts the 17 bit read data into the 16 bit NRZ data 4 6 4 Digital PLL circuit The drive uses constant density recording to increase total capacity This is different from the conventional method of recording data with a fixed data transfer rate at all data area In the constant density recording method data area is divided into zones by radius and the data transfer rate is set so that the reco...

Page 68: ...he block diagram of the servo control circuit The following describes the functions of the blocks Figure 4 7 Block diagram of servo control circuit 1 Microprocessor unit MPU The MPU includes the DSP unit and the MPU starts the spindle motor moves the heads to the reference cylinders seeks the specified cylinder and executes calibration according to the internal operations of the MPU Main internal ...

Page 69: ... head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area The logical initial cylinder is at the outermost circumference cylinder 0 c Seek to specified cylinder Drives the VCM to position the head to the specified cylinder d Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator and stores the calibration ...

Page 70: ...verts the VCM drive current value digital value calculated by the DSP unit into analog values and transfers them to the power amplifier 4 Power amplifier The power amplifier feeds currents corresponding to the DAC output signal voltage to the VCM 5 Spindle motor control circuit The spindle motor control circuit controls the sensor less spindle motor This circuit detects number of revolution of the...

Page 71: ...nd The head is in contact with the disk in this space when the spindle starts turning or stops and the rotational speed of the spindle can be controlled on this cylinder area for head moving 2 Data area This area is used as the user data area SA area 3 Outer guard band This area is located at outer position of the user data area and the rotational speed of the spindle can be controlled on this cyl...

Page 72: ...R Recovery Servo Mark Gray Code W R Recovery Servo Mark Gray Code Erase Servo A Erase Servo A Servo B Erase Servo B Erase Servo C Erase Servo C Erase Servo D Erase PAD CYLn 1 CYLn CYLn 1 n even number ÕÖ Diameter direction Ø Ø Circumference Direction Erase DC erase area OGB Data area IGB expand Servo frame 66 servo frames per revolution ...

Page 73: ...rated from the gray code and servo A to D This servo information is used for positioning operation of radius direction and position detection of circumstance direction The servo frame consists of 6 blocks write read recovery servo mark gray code servo A to D and PAD Figure 4 9 shows the servo frame format Figure 4 9 Servo frame format ...

Page 74: ...The MPU fetches the position sense data on the servo frame at a constant interval of sampling time executes calculation and updates the VCM drive current The servo control of the actuator includes the operation to move the head to the reference cylinder the seek operation to move the head to the target cylinder to read or write data and the track following operation to position the head onto the t...

Page 75: ...ference between the target position and the position clarified by the detected position sense data The filtering includes servo compensation These are digitally controlled by the firmware 4 7 5 Spindle motor control Hall less three phase twelve pole motor is used for the spindle motor and the 3 phase full half wave analog current control circuit is used as the spindle motor driver called SVC herea...

Page 76: ...rom the SVC and waits till the rotational speed reaches 4 200 rpm When the rotational speed reaches 4 200 rpm the SVC enters the stable rotation mode 3 Stable rotation mode The SVC calculates a time for one revolution of the spindle motor based on the PHASE signal The MPU takes a difference between the current time and a time for one revolution at 4 200 rpm that the MPU already recognized Then the...

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Page 78: ...PTER 5 Interface 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Ultra DMA Feature Set 5 6 Timing This chapter gives details about the interface and the interface commands and timings ...

Page 79: ... DMA REQUEST INTRO INTERRUPT REQUEST DIOW I O WRITE STOP STOP DURING ULTRA DMA DATA BURSTS DA 0 2 DEVICE ADDRESS CS0 CHIP SELECT 0 CS1 CHIP SELECT 1 RESET RESET CSEL CABLE SELECT MSTR Master ENCSEL ENABLE CSEL GND GROUND DIOR I O READ HDMARDY DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE DATA STROBE DURING ULTRA DMA DATA OUT BURST 5V DC 5 volt Host IORDY I O READY DDMARDY DMA READY DURING ULTR...

Page 80: ...11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 MSTR unused KEY RESET DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND DMARQ DIOW STOP DIOR HDMRDY HSTROBE IORDY DDMARDY DSTROBE DMACK INTRQ DA1 DA0 CS0 DASP 5 VDC GND B D F 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 MSTR ENCSEL ENCSEL KEY GND DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 KEY GND GND GND CSEL GND rese...

Page 81: ... by the host later indicates that the transfer has been suspended DIOR I Read strobe signal from the host to read the device register or data port HDMARDY I Flow control signal for Ultra DMA data In transfer READ DMA command This signal is asserted by the host to inform the device that the host is ready to receive the Ultra DMA data In transfer The host can negate the HDMARDY signal to suspend the...

Page 82: ...nd a slave device is present This signal is pulled up to 5 V through 10 kΩ resistor at each device IORDY O This signal requests the host system to delay the transfer cycle when the device is not ready to respond to a data transfer request from the host system DDMARDY O Flow control signal for Ultra DMA data Out transfer WRITE DMA command This signal is asserted by the device to inform the host tha...

Page 83: ...nal from the host to the device O indicates output signal from the device to the host I O indicates common output or bi directional signal between the host and the device 5 2 Logical Interface The device can operate for command execution in either address specified mode cylinder head sector CHS or Logical block address LBA mode The IDENTIFY DEVICE information indicates whether the device supports ...

Page 84: ...ow Cylinder Low X 1F4 L H H L H Cylinder High Cylinder High X 1F5 L H H H L Device Head Device Head X 1F6 L H H H H Status Command X 1F7 L L X X X Invalid Invalid Control block registers H L H H L Alternate Status Device Control X 3F6 H L H H H X 3F7 Notes 1 The Data register for read or write operation can be accessed by 16 bit data bus DATA0 to DATA15 2 The registers for read or write operation ...

Page 85: ... Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICRC UNC X IDNF X ABRT TK0NF AMNF X Unused Bit 7 Interface CRC Error ICRC This bit indicates that a CRC error occurred during Ultra DMA transfer Bit 6 Uncorrectable Data Error UNC This bit indicates that an uncorrectable data error has been encountered Bit 5 Unused Bit 4 ID Not Found IDNF This bit indicates an error except for bad sector uncorrectab...

Page 86: ...ead or write operation between the host system and the device When the value in this register is X 00 the sector count is 256 When this register indicates X 00 at the completion of the command execution this indicates that the command is completed successfully If the command is not completed successfully this register indicates the number of sectors to be transferred to complete the request from t...

Page 87: ...der 8 bits of the cylinder address are set to the Cylinder High register Under the LBA mode this register indicates LBA bits 23 to 16 8 Device Head register X 1F6 The contents of this register indicate the device and the head number When executing INITIALIZE DEVICE PARAMETERS command the contents of this register defines the number of heads minus 1 a maximum head No Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B...

Page 88: ...tem should not write the command block registers If the host system reads any command block register when BSY bit is 1 the contents of the Status register are posted This bit is set by the device under following conditions a Within 400 ns after RESET is negated or SRST is set in the Device Control register the BSY bit is set the BSY bit is cleared when the reset process is completed The BSY bit is...

Page 89: ...tes that the device is ready to transfer data of word unit or byte unit between the host system and the device Bit 2 Always 0 Bit 1 Always 0 Bit 0 Error ERR bit This bit indicates that an error was detected while the previous command was being executed The Error register indicates the additional information of the cause for the error 10 Command register X 1F7 The Command register contains a comman...

Page 90: ...he device is held reset state When two device are daisy chained on the interface setting this bit resets both device simultaneously The slave device is not required to execute the DASP handshake Bit 1 nIEN bit enables an interrupt INTRQ signal from the device to the host When this bit is 0 and the device is selected an interruption INTRQ signal can be enabled through a tri state buffer When this b...

Page 91: ...0 R N Y Y Y Y WRITE MULTIPLE 1 1 0 0 0 1 0 1 N Y Y Y Y WRITE DMA 1 1 0 0 1 0 1 R N Y Y Y Y WRITE VERIFY 0 0 1 1 1 1 0 0 N Y Y Y Y WRITE SECTOR S 0 0 1 1 0 0 0 R N Y Y Y Y RECALIBRATE 0 0 0 1 X X X X N N N N D SEEK 0 1 1 1 X X X X N N Y Y Y INITIALIZE DEVICE PARAMETERS 1 0 0 1 0 0 0 1 N Y N N Y IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D IDENTIFY DEVICE DMA 1 1 1 0 1 1 0 0 N N N N D SET FEATURES 1 1 ...

Page 92: ... 0 1 0 0 1 0 0 0 1 N N N N D SMART 1 0 1 1 0 0 0 0 Y Y Y Y D SECURITY DISABLE PASSWORD 1 1 1 1 0 1 1 0 N N N N D SECURITY ERASE PREPARE 1 1 1 1 0 0 1 1 N N N N D SECURITY ERASE UNIT 1 1 1 1 0 1 0 0 N N N N D SECURITY FREEZE LOCK 1 1 1 1 0 1 0 1 N N N N D SECURITY SET PASSWORD 1 1 1 1 0 0 0 1 N N N N D SECURITY UNLOCK 1 1 1 1 0 0 1 0 N N N N D FLUSH CACHE 1 1 1 0 0 1 1 1 N N N N D Notes FR Features...

Page 93: ...indication of the I O registers at command completion are shown as following in this subsection Example READ SECTOR S At command issuance I O registers setting contents Bit 7 6 5 4 3 2 1 0 1F7H CM 0 0 1 0 0 0 0 0 1F6H DH x L x DV Head No LBA MSB 1F5H CH Start cylinder address MSB LBA 1F4H CL Start cylinder address LSB LBA 1F3H SN Start sector No LBA LSB 1F2H SC Transfer sector count 1F1H FR xx At ...

Page 94: ...pecified in the Sector Count register from the address specified in the Device Head Cylinder High Cylinder Low and Sector Number registers Number of sectors can be specified to 256 sectors in maximum To specify 256 sectors reading 00 is specified For the DRQ INTRQ and BSY protocols related to data transfer see Subsection 5 4 1 If the head is not on the track specified by the host the device perfor...

Page 95: ...tor count xx R Retry At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x L x DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this ...

Page 96: ...ly having the same number of sectors block count as many full blocks as possible are transferred then a final partial block is transferred The number of sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when the READ MULTIPLE command is disabled the device...

Page 97: ...Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x L x DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sec...

Page 98: ...rupt using the INTRQ signal and posts a status to the host system The format of the error information is the same as the READ SECTOR S command In LBA mode The logical block address is specified using the start head No start cylinder No and first sector No fields At command completion the logical block address of the last sector and remaining number of sectors of which data was not transferred like...

Page 99: ...command except that the data is not transferred to the host system After all requested sectors are verified the device clears the BSY bit of the Status register and generates an interrupt Upon the completion of the command execution the command block registers contain the cylinder head and sector number of the last sector verified If an unrecoverable error occurs the verify operation is terminated...

Page 100: ...ta of sectors from the address specified in the Device Head Cylinder High Cylinder Low and Sector Number registers to the address specified in the Sector Count register Number of sectors can be specified to 256 sectors in maximum Data transfer begins at the sector specified in the Sector Number register For the DRQ INTRQ and BSY protocols related to data transfer see Subsection 5 4 2 If the head i...

Page 101: ... has occurred At command issuance I O registers setting contents 1F7H CM 0 0 1 1 0 0 0 R 1F6H DH x L x DV StartheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x L x DV EndheadNo LBA MSB 1F5H CH 1F4H CL...

Page 102: ...nd even if the value of the Sector Count register is less than the defined block count the value of the Sector Count should not be 0 If the number of requested sectors is not divided evenly having the same number of sectors block count as many full blocks as possible are transferred then a final partial block is transferred The number of sectors in the partial block to be transferred is n where n ...

Page 103: ...TOR S command except for following events The data transfer starts at the timing of DMARQ signal assertion The device controls the assertion or negation timing of the DMARQ signal The device posts a status as the result of command execution only once at completion of the data transfer or completion of processing in the device The device posts a status as the result of command execution only once a...

Page 104: ...information 1F6H DH x L x DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 8 WRITE VERIFY X 3C This command operates similarly to the WRITE SECTOR S command e...

Page 105: ...CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 9 RECALIBRATE X 1x x X 0 to X F This command performs the calibration Upon receipt of this command the device sets BSY bit of the Statu...

Page 106: ...ror information Note Also executable in LBA mode 10 SEEK X 7x x X 0 to X F This command performs a seek operation to the track and selects the head specified in the command block registers After completing the seek operation the device clears the BSY bit in the Status register and generates an interrupt The IDD always sets the DSC bit Drive Seek Complete status of the Status register to 1 In the L...

Page 107: ... with this command Upon receipt of this command the device sets the BSY bit of Status register and saves the parameters Then the device clears the BSY bit and generates an interrupt When the SC register is specified to X 00 an ABORTED COMMAND error is posted Other than X 00 is specified this command terminates normally The parameters set by this command are retained even after reset or power save ...

Page 108: ...xx xx xx Number of sectors track Error information 12 IDENTIFY DEVICE X EC The host system issues the IDENTIFY DEVICE command to read parameter information 512 bytes from the device Upon receipt of this command the drive sets the BSY bit of Status register and sets required parameter information in the sector buffer The device then sets the DRQ bit of the Status register and generates an interrupt...

Page 109: ...1F1H ER xx xx xx xx Error information Table 5 4 Information to be read by IDENTIFY DEVICE command 1 of 8 Word Value Description 0 X 045A General Configuration 1 1 2 Number of cylinders 2 2 X C837 Detailed Configuration 3 2 Number of Heads 2 4 5 X 0000 Undefined 6 2 Number of sectors per track 2 7 9 X 0000 Undefined 10 19 Set by a device Serial number ASCII code 20 characters right 20 X 0000 Undefi...

Page 110: ...ctors per track 57 58 Variable Total number of current sectors 59 6 Transfer sector count currently set by READ WRITE MULTIPLE command 6 60 61 2 Total number of user addressable sectors LBA mode only 2 62 X 0000 Reserved 63 X xx07 Multiword DMA transfer mode 7 64 X 0003 Advance PIO transfer mode support status 8 65 X 0078 Minimum multiword DMA transfer cycle time per word 120 ns 66 X 0078 Manufact...

Page 111: ...re configuration 94 127 X 0000 Reserved 128 Variable Security status 16 129 159 X 0000 Undefined 160 254 X 0000 Reserved 255 X xxA5 Check sum The 2 complement of the lower order byte resulting from summing bits 7 to 0 of word 0 to 254 and word 255 in byte units 1 Word 0 General configuration Bit 15 ATA device 0 ATAPI device 1 Bit 14 8 Undefined Bit 7 Removable disk drive 1 Bit 6 Fixed drive 1 Bit ...

Page 112: ...e setting of word 88 1 Enable Bit 1 Enable disable setting of word 64 70 1 Enable Bit 0 Enable disable setting of word 54 58 1 Enable 6 Word 59 Transfer sector count currently set by READ WRITE MULTIPLE command Bit 15 9 Reserved Bit 8 Multiple sector transfer 1 Enable Bit 7 0 Transfer sector count currently set by READ WRITE MULTIPLE command without interrupt supports 2 4 8 and 16 sectors 7 Word 6...

Page 113: ...and Bit 11 Undefined Bit 10 1 Supports the Host Protected Area feature set Bit 9 1 Supports the DEVICE RESET command Bit 8 1 Supports the SERVICE interrupt Bit 7 1 Supports the release interrupt Bit 6 1 Supports the read cache function Bit 5 1 Supports the write cache function Bit 4 1 Supports the PACKET command feature set Bit 3 1 Supports the power management feature set Bit 2 1 Supports the Rem...

Page 114: ...t 12 1 Enables the WRITE BUFFER command Bit 11 Undefined Bit 10 1 Enables the Host Protected Area function Bit 9 1 Enables the DEVICE RESET command Bit 8 1 Enables the SERVICE interrupt Bit 7 1 Enables the release interrupt Bit 6 1 Enables the read cache function Bit 5 1 Enables the write cache function Bit 4 1 Enables the P PACKET command set Bit 3 1 Enables the Power Management function Bit 2 1 ...

Page 115: ...r than VIL Bits 12 8 In the case of Device 1 slave drive a valid value is set Bit 12 Reserved Bit 11 1 Device asserts PDIAG Bit 10 9 Method for deciding the device No of Device 1 00 Reserved 01 Using a jumper 10 Using the CSEL signal 11 Other method Bit 8 Reserved Bits 7 0 In the case of Device 0 master drive a valid value is set Bit 7 Reserved Bit 6 1 Device 1 is selected Device 0 responds Bit 5 ...

Page 116: ...Enhanced security erase supported Bit 4 1 Security counter expired Bit 3 1 Security frozen Bit 2 1 Security locked Bit 1 1 Security enabled Bit 0 1 Security supported 13 IDENTIFY DEVICE DMA X EE When this command is not used to transfer data to the host in DMA mode this command functions in the same way as the Identify Device command At command issuance I O registers setting contents 1F7H CM 1 1 1...

Page 117: ...g the device features to be executed For the transfer mode Feature register 03 detail setting can be done using the Sector Count register Upon receipt of this command the device sets the BSY bit of the Status register and saves the parameters in the Features register Then the device clears the BSY bit and generates an interrupt If the value in the Features register is not supported or it is invali...

Page 118: ...fter software reset X 82 Disables the write cache function X 85 Disables the advanced power management function X AA Enables the read cache function X BB Specifies the transfer of 4 byte ECC for READ LONG and WRITE LONG commands X CC Enables the reverting to power on default settings after software reset At power on or after hardware reset the default mode is the same as that is set with a value g...

Page 119: ...st sets X 03 to the Features register By issuing this command with setting a value to the Sector Count register the transfer mode can be selected Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value The IDD supports following values in the Sector Count register value If other value than below is specified an ABORTED COMMAND error is p...

Page 120: ...lso specified by the SET MULTIPLE MODE command The number of sectors per block is written into the Sector Count register The IDD supports 2 4 8 16 and 32 sectors as the block counts Upon receipt of this command the device sets the BSY bit of the Status register and checks the contents of the Sector Count register If the contents of the Sector Count register is valid and is a supported block count ...

Page 121: ...on After power on or after hardware reset the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode The mode established before software reset is retained if disable default Features Reg 66h setting has been defined by the SET FEATURES command If disable default has not been defined after the software is the READ MULTIPLE and WRITE MULTIPLE commands are disabled The p...

Page 122: ...MAX FREEZE LOCK 05h FFh Reserved SET MAX ADDRESS This command allows the maximum address accessible by the user to be set in LBA or CHS mode Upon receipt of the command the device sets the BSY bit and saves the maximum address specified in the DH CH CL and SN registers Then it clears BSY and generates an interrupt The new address information set by this command is reflected in Words 1 54 57 58 60 ...

Page 123: ...H FR xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV Max head LBA MSB 1F5H CH Max cylinder MSB Max LBA 1F4H CL Max cylinder LSB Max LBA 1F3H SN Max sector Max LBA LSB 1F2H SC xx 1F1H ER Error information SET MAX SET PASSWORD FR 01h This command requests a transfer of 1 sector of data from the host and defines the contents of SET MAX password T...

Page 124: ...ontents 0 Reserved 1 to 16 Password 32 bytes 17 to 255 Reserved SET MAX LOCK FR 02h After this command is completed any other SET MAX commands except SET MAX UNLOCK and SET MAX FREEZE LOCK commands are rejected And the device returns command aborted The device remains in the SET MAX LOCK state until a power cycle or the acceptance of SET MAX UNLOCK or SET MAX FREEZE LOCK command The READ NATIVE MA...

Page 125: ...of data from the host and defines the contents of SET MAX ADDRESS password The data transferred controls the function of this command The password supplied in the sector of data transferred shall be compared with the stored password If the password compare fails the device returns command aborted and decrements the Unlock counter and remains in the Set Max Lock state On the acceptance of the SET M...

Page 126: ...Locked state 51h 04h ABORTED command At command issuance I O registers setting contents 1F7H CM 1 1 1 1 1 0 0 1 1F6H DH x L x DV xx 1F5H CH 1F4H CL 1F3H SN xx xx xx 1F2H SC xx 1F1H FR 03 At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH 1F5H CH 1F4H CL 1F3H SN 1F2H SC xx xx xx xx xx 1F1H ER Error information SET MAX FREEZE LOCK FR 04h After the device made ...

Page 127: ...F5H CH 1F4H CL 1F3H SN xx xx xx 1F2H SC xx 1F1H FR 04 At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH 1F5H CH 1F4H CL 1F3H SN 1F2H SC xx xx xx xx xx 1F1H ER Error information 17 READ NATIVE MAX ADDRESS F8 This command posts the maximum address intrinsic to the device which can be set by the SET MAX ADDRESS command Upon receipt of this command the device s...

Page 128: ...ually sets the DRV bit of the Drive Head register is to 0 however the DV bit is not checked If two devices are present both devices execute self diagnosis If device 1 is present Both devices shall execute self diagnosis The device 0 waits for up to 5 seconds until device 1 asserts the PDIAG signal If the device 1 does not assert the PDIAG signal but indicates an error the device 0 shall append X 8...

Page 129: ... self diagnosis the device 0 ORs X 80 with its own status and sets that code to the Error register Table 5 6 Diagnostic code Code Result of diagnostic X 01 X 03 X 05 X 8x No error detected Data buffer compare error ROM sum check error Failure of device 1 attention The device responds normally to this command without executing internal diagnostic test At command issuance I O registers setting conte...

Page 130: ...ata in the requested sector and the ECC bytes to the host system The ECC error correction is not performed for this command This command is used for checking ECC function by combining with the WRITE LONG command Number of ECC bytes to be transferred is fixed to 4 bytes and cannot be changed by the SET FEATURES command The READ LONG command supports only single sector operation At command issuance ...

Page 131: ...system to the disk medium The device does not generate ECC bytes by itself The WRITE LONG command supports only single sector operation The number of ECC bytes to be transferred is fixed to 4 bytes and can not be changed by the SET FEATURES command This command is operated under the following conditions READ LONG issued WRITE LONG Same address issues sequence After READ LONG is issued WRITE LONG c...

Page 132: ...ER X E4 The host system can read the current contents of the sector buffer of the device by issuing this command Upon receipt of this command the device sets the BSY bit of Status register and sets up the sector buffer for a read operation Then the device sets the DRQ bit of Status register clears the BSY bit and generates an interrupt After that the host system can read up to 512 bytes of data fr...

Page 133: ...a pattern by issuing this command Upon receipt of this command the device sets the BSY bit of the Status register Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data After that 512 bytes of data is transferred from the host and the device writes the data to the sector buffer then generates an interrupt At command issuance I O regi...

Page 134: ... timer reaches the specified value the device enters standby mode Enabling the automatic power down function means that the device automatically enters the standby mode after a certain period of time When the device enters the idle mode the timer starts countdown If any command is not issued while the timer is counting down the device automatically enters the standby mode If any command is issued ...

Page 135: ...d 1F7H ST Status information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information 24 IDLE IMMEDIATE X 95 or X E1 Upon receipt of this command the device sets the BSY bit of the Status register and enters the idle mode Then the device clears the BSY bit and generates an interrupt This command does not support the automatic power down function At command issuance...

Page 136: ...spun down the spin down sequence is not implemented By using this command the automatic power down function is enabled and the timer starts the countdown when the device returns to idle mode When the timer value reaches 0 a specified time has padded the device enters standby mode Under the standby mode the spindle motor is stopped Thus when the command involving a seek such as the READ SECTOR s co...

Page 137: ...of the Status register and enters the standby mode The device then clears the BSY bit and generates an interrupt This command does not support the automatic power down sequence At command issuance I O registers setting contents 1F7H CM X 94 or X E0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status infor...

Page 138: ...d the sleep mode In the sleep mode the spindle motor is stopped and the ATA interface section is inactive All I O register outputs are in high impedance state The only way to release the device from sleep mode is to execute a software or hardware reset At command issuance I O registers setting contents 1F7H CM X 99 or X E6 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx ...

Page 139: ...ice clears the BSY bit and generates an interrupt Power save mode Sector Count register During moving to standby mode Standby mode During returning from the standby mode X 00 Idle mode X FF Active mode X FF At command issuance I O registers setting contents 1F7H CM X 98 or X E5 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents t...

Page 140: ...ted It is necessary for the host to set the keys CL 4Fh and CH C2h in the CL and CH registers prior to issuing this command If the keys are set incorrectly the Aborted Command error is posted In the default setting the failure prediction feature is enabled The device collects or updates several items to forecast failures In the following sections the values of items collected or updated by the dev...

Page 141: ... When the automatic saving feature is enabled the attribute values are saved before the device enters the power saving mode However if the failure prediction feature is disabled the attribute values are not automatically saved When the device receives this subcommand it asserts the BSY bit enables or disables the automatic saving feature then clears the BSY bit X D3 SMART Save Attribute Values Whe...

Page 142: ...t has prepared to receive data from the host computer it sets DRQ and clears the BSY bit Next it receives data from the host computer and writes the specified log sector in the SN register SN Log sector 80h 9Fh Host vendor log The host can write any desired data in the host vendor log X D8 SMART Enable Operations This subcommand enables the failure prediction feature The setting is maintained even...

Page 143: ...assed since the power was switched on or since the last time that off line data were collected off line data collection is performed without relation to any command from the host computer The host must regularly issue the SMART Read Attribute Values subcommand FR register D0h SMART Save Attribute Values subcommand FR register D3h or SMART Return Status subcommand FR register DAh to save the device...

Page 144: ...prediction status 4Fh F4h xx xx Error information The attribute value information is 512 byte data the format of this data is shown below The host can access this data using the SMART Read Attribute Values subcommand FR register D0h The insurance failure threshold value data is 512 byte data the format of this data is shown below The host can access this data using the SMART Read Attribute Thresho...

Page 145: ...data collection execution time sec 16E Reserved 16F Off line data collection capability 170 171 Trouble prediction capability flag 172 Error logging capability 173 Vendor unique 174 Simple self test execution time min 175 Comprehensive self test execution time min 176 to 181 Reserved 182 to 1FE Vendor unique 1FF Check sum Table 5 9 Format of insurance failure threshold value data Byte Item 00 01 D...

Page 146: ...me performance 9 Power on time 10 Number of retries made to activate the spindle motor 12 Number of power on power off times 13 to 198 Reserved 199 Ultra ATA CRC error rate 200 Write error rate 201 to 255 Unique to vendor Status Flag Bit Meaning 0 If this bit 1 it indicates that if the attribute exceeds the threshold it is the attribute covered by the drive warranty 1 If this bit is 1 0 it indicat...

Page 147: ...tribute value Raw attributes data is retained Off line data collection status Bits 0 to 6 Indicates the situation of off line data collection according to the table below Bit 7 If this bit is 1 it indicates that the automatic off line data collection function is enabled Status Byte Meaning 0 Off line data collection is not started 2 Off line data collection has been completed normally 4 Off line d...

Page 148: ...he method of off line data collection carried out by the drive If the off line data collection capability is 0 it indicates that off line data collection is not supported Bit Meaning 0 Indicates that Execute Off Line Immediate is supported 1 Vendor unique 2 Indicates that off line data collection being executed is aborted when a new command is received 3 Indicates that supports off line read scan ...

Page 149: ...mand FR register D5h SN register 01h and read the SMART error log Table 5 10 SMART error log data format 1 2 Byte Item 00 Error log version number 01 Error log index 02 Error log 1 Command Data 1 Device Control register 03 Features register 04 Sector Count register 05 Sector Number register 06 Cylinder Low register 07 Cylinder High register 08 Device Head register 09 Command register 0A to 0D Elap...

Page 150: ...r If an error has not occurred 00 is displayed Error log 1 to 5 When an error occurs the error log index value is incremented and information at the time the error occurred is recorded in the error log area specified by this value When the error log index exceeds 05 it returns to 01 Command data 1 to 5 Indicates five commands data in order received by the device until the error occurs Commands for...

Page 151: ...ta format Byte Item 00 01 Self test log data format version number 02 Self test log 1 Self test mode SN Register Value 03 Self test execution status 04 05 Total power on time until the self test is completed hours 06 Self test error No 07 to 0A Error LBA 0B to 19 Vendor unique 1A to 1F9 Self test log 2 to 21 Each log data format is the same as that in byte 02 to 19 1FA 1FB Vendor unique 1FC Self t...

Page 152: ...lready set and releases the lock function if the passwords are the same Although this command invalidates the user password the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password If the user password or master password transferred from the host does not match the Aborted Command error is returned Issuing this command while...

Page 153: ... SN 1F2h SC 1F1h FR xx xx xx xx xx At command completion I O register contents 1F7h ST Status information 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information 31 SECURITY ERASE PREPARE F3h The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command The SECURITY ERASE PREPARE command p...

Page 154: ...s the 512 byte data shown in Table 5 10 to the device The device compares the user password or master password in the transferred data with the user password or master password already set The device erases user data invalidates the user password and releases the lock function if the passwords are the same Although this command invalidates the user password the master password is retained To recov...

Page 155: ...ice into FROZEN MODE The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE SECURITY SET PASSWORD SECURITY UNLOCK SECURITY DISABLE PASSWORD SECURITY ERASE UNIT FROZEN MODE is canceled when the power is turned off or when hardware is reseted If this command is reissued in FROZEN MODE the command is completed and FROZEN MODE remains u...

Page 156: ...RITY SET PASSWORD READ SECTORS WRITE SECTORS WRITE VERIFY At command issuance I O register contents 1F7h CM 1 1 1 1 0 1 0 1 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h FR xx xx xx xx xx At command completion I O register contents 1F7h ST Status information 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information ...

Page 157: ...rd 32 bytes 17 Master password version number 18 to 255 Reserved Table 5 14 Relationship between combination of Identifier and Security level and operation of the lock function Identifier Level Description User High The specified password is saved as a new user password The lock function is enabled after the device is turned off and then on LOCKED MODE can be canceled using the user password or th...

Page 158: ...E is high the password is compared with the master password already set If the passwords are the same LOCKED MODE is canceled Otherwise the Aborted Command error is returned If the security level in LOCKED MODE is set to the highest level the Aborted Command error is always returned When the user password is selected The password is compared with the user password already set If the passwords are ...

Page 159: ...is command is used to order to write every write cache data stored by the device into the medium BSY bit is held at 1 until every data has been written normally or an error has occurred The device performs every error recovery so that the data are read correctly When executing this command the reading of the data may take several seconds if much data are to be read In case a non recoverable error ...

Page 160: ... ER xx xx xx xx Error information 5 3 3 Error posting Table 5 15 lists the defined errors that are valid for each command Table 5 15 Command code and parameters 1 of 2 Command name Error register X 1F1 Status register X 1F7 ICRC UNC INDF ABRT TK0NF DRDY DWF ERR READ SECTOR S V V V V V V WRITE SECTOR S V V V V V READ MULTIPLE V V V V V V WRITE MULTIPLE V V V V V READ DMA V V V V V V V WRITE DMA V V...

Page 161: ... V V V V V READ NATIVE MAX ADDRESS V V V V EXECUTE DEVICE DIAGNOSTIC V READ LONG V V V V V WRITE LONG V V V V V READ BUFFER V V V V WRITE BUFFER V V V V IDLE V V V V IDLE IMMEDIATE V V V V STANDBY V V V V STANDBY IMMEDIATE V V V V SLEEP V V V V CHECK POWER MODE V V V V SMART V V V V V SECURITY DISABLE PASSWORD V V V V SECURITY ERASE PREPARE V V V V SECURITY ERASE UNIT V V V V SECURITY FREEZE LOCK ...

Page 162: ...D LONG command 516 bytes are transferred Following shows the protocol outline a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head registers b The host writes a command code to the Command register c The device sets the BSY bit of the Status register and prepares for data transfer d When one sector of data is available for transfer to the ho...

Page 163: ...SECTOR S command protocol and Figure 5 4 shows an example protocol for command abort Figure 5 3 Read Sector s command protocol IMPORTANT For transfer of a sector of data the host needs to read Status register X 1F7 in order to clear INTRQ interrupt signal The Status register should be read within a period from the DRQ setting by the device to 50 ms after the completion of the sector data transfer ...

Page 164: ...tting in DRQ bit the correct device operation is not guaranteed Figure 5 4 Protocol for command abort 5 4 2 Data transferring commands from host to device The execution of the following commands involves Data transfer from the host to the drive WRITE SECTOR S WRITE LONG WRITE BUFFER WRITE VERIFY SECURITY DISABLE PASSWORD SECURITY ERASE UNIT SECURITY SET PASSWORD SECURITY UNCLOK The execution of th...

Page 165: ...e sector of data through the Data register e The device clears the DRQ bit and sets the BSY bit f When the drive completes transferring the data of the sector the device clears BSY bit and asserts INTRQ signal If transfer of another sector is requested the drive sets the DRQ bit g After detecting the INTRQ signal assertion the host reads the Status register h The device resets INTRQ the interrupt ...

Page 166: ...nsfer operation is not assured guaranteed When the host issues the command even if the drive requests the data transfer DRQ bit is set or when the host executes resetting the device correct operation is not guaranteed 5 4 3 Commands without data transfer Execution of the following commands does not involve data transfer between the host and the device RECABLIBRATE SEEK READY VERIFY SECTOR S EXECUT...

Page 167: ...nterruptions in any intermediate sector when a multisector command is executed The following outlines the protocol The interrupt processing for the DMA transfer differs the following point The interrupt processing for the DMA transfer differs the following point a The host writes any parameters to the Features Sector Count Sector Number Cylinder and Device Head register b The host initializes the ...

Page 168: ...ution is completed the device clears both BSY and DRQ bits and asserts the INTRQ signal Then the host reads the Status register g The host resets the DMA channel Figure 5 7 shows the correct DMA data transfer protocol Figure 5 7 Normal DMA data transfer f d e e d g d f f ...

Page 169: ...A data out burst During an Ultra DMA burst a sender shall always drive data onto the bus and after a sufficient time to allow for propagation delay cable settling and setup time the sender shall generate a STROBE edge to latch the data Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data The highest fundamental frequency on t...

Page 170: ...DDMARDY or HDMARDY and STROBE is used in cases that could apply to either DSTROBE or HSTROBE The following are general Ultra DMA rules a An Ultra DMA burst is defined as the period from an assertion of DMACK by the host to the subsequent negation of DMACK b A recipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra DMA burst 5 5 2 1 Ultra DMA burst init...

Page 171: ...on side and then should output the termination request signal when a certain wait time has elapsed e The transmitting side is allowed to send STROBE signal at a transfer speed that is lower than the one in the transferable fastest Ultra DMA mode but is not allowed to send the STROBE signal at a higher speed than this The receiving side should be able to receive the data in the transferable fastest...

Page 172: ...ta in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 1 and 5 6 4 2 for specific timing requirements 1 The host shall keep DMACK in the negated state before an Ultra DMA burst is initiated 2 The device shall assert DMARQ to initiate an Ultra DMA burst After assertion of DMARQ the device shall not negate DMARQ until after the first ...

Page 173: ...STROBE edge no more frequently than tCYC for the selected Ultra DMA Mode The device shall not generate two rising or two falling DSTROBE edges more frequently than 2tCYC for the selected Ultra DMA mode 3 The device shall not change the state of DD 15 0 until at least tDVH after generating a DSTROBE edge to latch the data 4 The device shall repeat steps 1 2 and 3 until the data transfer is complete...

Page 174: ... burst a Device terminating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 5 and 5 6 4 2 for specific timing requirements 1 The device shall initiate termination of an Ultra DMA burst by not generating DSTROBE edges 2 The device shall negate DMARQ no sooner than tSS after generating the last DSTROBE edge The d...

Page 175: ...red see 5 5 5 12 The device shall release DSTROBE within tIORDYZ after the host negates DMACK 13 The host shall not negate STOP no assert HDMARDY until at least tACK after negating DMACK 14 The host shall not assert DIOR CS0 CS1 DA2 DA1 or DA0 until at least tACK after negating DMACK b Host terminating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless o...

Page 176: ...If the host has not placed the result of its CRC calculation on DD 15 0 since first driving DD 15 0 during 9 the host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 11 The host shall negate DMACK no sooner than tMLI after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY and no sooner than tDVS after the host places the result ...

Page 177: ...release DDMARDY until after the host has negated DMACK at the end of an Ultra DMA burst 8 The host shall negate STOP within tENV after asserting DMACK The host shall not assert STOP until after the first negation of HSTROBE 9 The device shall assert DDMARDY within tLI after the host has negated STOP After asserting DMARQ and DDMARDY the device shall not negate either signal until after the first n...

Page 178: ...not immediately negate DMARQ to initiate Ultra DMA burst termination when the host stops generating HSTROBE edges If the host does not assert STOP in order to initiate Ultra DMA burst termination the device shall negate DDMARDY and wait tRP before negating DMARQ 3 The host shall resume an Ultra DMA burst by generating an HSTROBE edge b Device pausing an Ultra DMA data out burst 1 The device shall ...

Page 179: ...e device has negated DMARQ No data shall be transferred during this assertion The device shall ignore this transition on HSTROBE HSTROBE shall remain asserted until the Ultra DMA burst is terminated 6 The host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 7 The host shall negate DMACK no sooner than tMLI after the host has asserted HSTROBE and STOP and the device has negated D...

Page 180: ...he device shall not assert DMARQ again until after the Ultra DMA burst is terminated 6 The host shall assert STOP with tLI after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated 7 If HSTROBE is negated the host shall assert HSTROBE with tLI after the device has negated DMARQ No data shall be transferred during this assertion The device...

Page 181: ...alculation function to the device on DD 15 0 with the negation of DMACK f The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function If the two values do not match the device shall save the error and report it at the end of the command A subsequent Ultra DMA burst for the same command that does not have a CRC error shall not clear an erro...

Page 182: ...CRCIN12 f4 XOR f9 XOR f16 CRCIN5 f11 XOR f CRCIN13 f3 XOR f8 XOR f15 CRCIN6 f10 XOR f15 CRCIN14 f2 XOR f7 XOR f14 CRCIN7 f9 XOR f14 CRCIN15 f1 XOR f6 XOR f13 f1 DD0 XOR CRCOUT15 f9 DD8 XOR CRCOUT7 XOR f5 f2 DD1 XOR CRCOUT14 f10 DD9 XOR CRCOUT6 XOR f6 f3 DD2 XOR CRCOUT13 f11 DD10 XOR CRCOUT5 XOR f7 f4 DD3 XOR CRCOUT12 f12 DD11 XOR CRCOUT4 XOR f1 XOR f8 f5 DD4 XOR CRCOUT11 XOR f1 f13 DD12 XOR CRCOUT...

Page 183: ...1 DA2 33 Ω 82 Ω DMACK 22 Ω 82 Ω DD15 through DD0 33 Ω 120 Ω 100 MHz DMARQ 82 Ω 22 Ω INTRQ 82 Ω 22 Ω IORDY DDMARDY DSTROBE 82 Ω 22 Ω Note Only those signals requiring termination are listed in this table If a signal is not listed series termination is not required for operation in an Ultra DMA Mode For signals also requiring a pull up or pull down resistor at the host see Figure 5 9 Figure 5 9 Ultr...

Page 184: ...5 6 Timing C141 E104 03EN 5 107 5 6 Timing 5 6 1 PIO data transfer Figure 5 10 shows of the data transfer timing between the device and the host system ...

Page 185: ...Interface 5 108 C141 E104 03EN Figure 5 10 Data transfer timing ...

Page 186: ...6 2 Multiword DMA data transfer Figure 5 11 shows the multiword DMA data transfer timing between the device and the host system Delay time from DIOR DIOW assertion to DMARQ negation Figure 5 11 Multiword DMA data transfer timing mode 2 ...

Page 187: ... Starting of Ultra DMA data In Burst The timing for each Ultra DMA mode is included in 5 6 3 2 Note The definitions of STOP HDMARDY and DSTROBE signals are valid before the assertion of DMACK signal Figure 5 12 Starting of Ultra DMA data In Burst transfer DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DA0 DA1 DA2 CS0 CS1 tUI tENV tFS tENV tZAD tFS tZAD tDVH tVDS tAZ tZIORDY ...

Page 188: ... 5 tFS 0 230 0 200 0 170 0 130 0 120 First STROBE time for device to first negate DSTROBE from STOP during a data in burst tLI 0 150 0 150 0 150 0 100 0 100 Limited interlock time see Note 3 tMLI 20 20 20 20 20 Interlock time with minimum see Note 3 tUI 0 0 0 0 0 Unlimited interlock time see Note 3 tAZ 10 10 10 10 10 Maximum time allowed for output drivers to release from asserted or negated tZAH ...

Page 189: ...ender shall stop generating STROBE edges tRFS after the negation of DMARDY Both STROBE and DMARDY timing measurements are taken at the connector of the sender 2 All timing measurement switching points low to high and high to low shall be taken at 1 5 V 3 tUI tMLI and tLI indicate sender to recipient or recipient to sender interlocks i e one agent either sender or recipient is waiting for the other...

Page 190: ...he host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Figure 5 13 Sustained Ultra DMA data in burst DSTROBE at device DD 15 0 at device DSTROBE at host DD 15 0 at host t2CYC tCYC tDVS tDVH tDS tDH t2CYC tCYC tDVH tDVS tDVH tDS tDH tDH ...

Page 191: ... The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY is negated 2 If the tSR timing is not satisfied the host may receive zero one or two more data words from the device Figure 5 14 Host pausing an Ultra DMA data in burst tRP tSR tRFS DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 device ...

Page 192: ...a DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 15 Device terminating an Ultra DMA data in burst DMARQ device DMACK host DD 15 0 HDMARDY host DSTROBE device STOP host DA0 DA1 DA2 CS0 CS1 tMLI tLI tLI tLI tACK tACK tIORDYZ tSS tZAH tAZ tDVS tDVH CRC tACK ...

Page 193: ...MA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 16 Host terminating an Ultra DMA data in burst DMARQ device tLI tMLI tRP tZAH tAZ tRFS tLI tMLI tDVS tDVH tACK tACK tACK tIORDYZ CRC DA0 DA1 DA2 CS0 CS1 DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 ...

Page 194: ... the Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 17 Initiating an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tUI tACK tENV tZIORDY tUI tLI tACK tACK tDVS tDVH ...

Page 195: ...h the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Figure 5 18 Sustained Ultra DMA data out burst HSTROBE at host HSTROBE at device DD 15 0 at host DD 15 0 at device t2CYC tCYC tCYC t2CYC tDVH tDVS tDVH tDVS tDVH tDH tDS tDH tDS tDH...

Page 196: ... The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY is negated 2 If the tSR timing is not satisfied the device may receive zero one or two more data words from the host Figure 5 19 Device pausing an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host tRP tSR tRFS ...

Page 197: ...tra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 20 Host terminating an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host tLI tLI tSS tLI tMLI tACK tIORDYZ tACK tACK tDVH tDVS CRC DA0 DA1 DA2 CS0 CS1 ...

Page 198: ... DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 21 Device terminating an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tLI tLI tRP tRFS tMLI tMLI tDVS tDVS tIORDYZ tACK tACK tACK CRC ...

Page 199: ...and reset Figure 5 22 shows power on and reset hardware and software reset timing 1 Only master device is present 2 Master and slave devices are present 2 drives configuration Figure 5 22 Power on Reset Timing 31 Power on Reset RESET PDIAG negation ...

Page 200: ...C141 E104 03EN 6 1 CHAPTER 6 Operations 6 1 Device Response to the Reset 6 2 Address Translation 6 3 Power Save 6 4 Defect Management 6 5 Read Ahead Cache 6 6 Write Cache ...

Page 201: ...ecognizes presence of the slave device when it confirms assertion of the DASP signal Then the master device checks a PDIAG signal to see if the slave device has successfully completed the power on diagnostics If the master device cannot confirm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is connected After the slave device device 1 releases its own ...

Page 202: ...0 ms Max 30 sec Max 1 ms If presence of a slave device is confirmed PDIAG is checked for up to 31 seconds Checks DASP for up to 450 ms DASP PDIAG BSY bit Power On Reset Status Reg BSY bit Power On Reset Slave device Master device Power on Figure 6 1 Response to power on ...

Page 203: ...elf diagnostics If the master device cannot confirm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is connected After the slave device receives the hardware reset the slave device shall report its presence and the result of the self diagnostics to the master device as described below DASP signal Asserted within 400 ms PDIAG signal Negated within 1 ms a...

Page 204: ...e slave device shall report its presence and the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 30 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting the PDIAG signal Max 31 sec Max 30 sec Max 1 ms If the slave device is p...

Page 205: ...ves the EXECUTE DEVICE DIAGNOSTIC command it shall report the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 5 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting the PDIAG signal Max 6 sec Max 5 sec Max 1 ms If the slave d...

Page 206: ...The parameters in Table 6 1 are called BIOS specification Table 6 1 Default parameters MHL2300AT MHM2200AT MHM2150AT MHM2100AT Number of cylinders 16 383 16 383 16 383 16 383 Number of heads 16 16 16 16 Number of sectors track 63 63 63 63 Formatted capacity MB 30 005 82 20 003 88 15 103 03 10 056 13 As long as the formatted capacity of the IDD does not exceed the value shown on Table 6 1 the host ...

Page 207: ...n the initial sector of the subsequent physical track Figure 6 5 shows an example of 6 heads configuration assuming there is no track skew LS2 LS1 LS1 LS1 LS 63 Physical head 0 Physical cylinder 0 127 126 64 63 62 LH8 LH1 LH0 3 2 1 Physical sector LS 63 LS 63 505 506 504 LS4 LS3 LS 63 ex Zone 0 in 6 head device Physical parameter Physical head 0 to 5 Physical sector 1 to 506 Specification of INITI...

Page 208: ...is no track skew 459 230 229 228 229 230 230 229 458 232 231 230 6 5 Figure 6 6 Address translation example in LBA mode 6 3 Power Save The host can change the power consumption state of the device by issuing a power command to the device 6 3 1 Power save mode There are four types of power consumption state of the device including active mode where all circuits are active In the power save mode pow...

Page 209: ...the device is set to power save mode The device enters the Idle mode under the following conditions After completion of power on sequence After completion of the command execution other than SLEEP and STANDBY commands After completion of the reset sequence 3 Standby mode In this mode the VCM circuit is turned off and the spindle motor is stopped The device can receive commands through the interfac...

Page 210: ...urn from the standby mode is to execute a software or hardware reset The drive enters the sleep mode under the following condition A SLEEP command is issued Issued commands are invalid ignored in this mode 6 3 2 Power commands The following commands are available as power commands IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE 6 4 Defect Management Defective sectors of which ...

Page 211: ...ector is not used and is skipped and a logical sector address is assigned to the subsequent normal sector physically adjacent sector to the defective sector When defective sector is present the sector slip processing is performed in the formatting Figure 6 7 shows an example where physical sector 5 is defective on head 0 in cylinder 0 If an access request to physical sector 5 is specified the devi...

Page 212: ...ternate cylinder instead of sector 5 When an access request to sectors next to sector 5 is specified the device seeks to cylinder 0 head 0 and continues the processing Figure 6 8 Alternate cylinder assignment 3 Automatic alternate assignment The device performs the automatic alternate assignment when ECC correction performance is increased during read error retry a read error is recovered Before a...

Page 213: ...read commands for write commands for MPU work 2 MB 2 097 152 bytes 1 048 576 bytes 2048 sector 983 040 bytes 1920 sector 65 536 bytes Figure 6 9 Data buffer configuration The read ahead operation is performed at execution of the READ SECTOR S READ MULTIPLE or READ DMA command and read ahead data is stored in the buffer for read commands 6 5 2 Caching operation Caching operation is performed only a...

Page 214: ... data However since the hit check at issuance of read command is performed to the data buffer for read command preferentially caching write data is limited to the case that the hit check is missed at the data buffer for read command When all data requested by the read command are stored in the data buffer for write command hit all the device transfers data from the data buffer for write command At...

Page 215: ...command is issued write data kept until now are invalidated 6 5 3 Usage of read segment This subsection explains the usage of the read segment buffer at following cases 6 5 3 1 Mis hit no hit A lead block of the read requested data is not stored in the data buffer The requested data is read from the disk media The read ahead operation is performed only when the last sector address of the previous ...

Page 216: ... HAP 4 Following shows the cache enabled data for next read command Cache enabled data Empty area 6 5 3 2 Sequential read When the disk drive receives the read command that targets the sequential address to the previous read command the disk drive starts the read ahead operation a Sequential command just after non sequential command When the previously executed read command is an non sequential co...

Page 217: ...ing the requested data Requested data DAP HAP Mis hit data Empty area 3 After completion of the reading and transferring the requested data to the host system the disk drive performs the read ahead operation continuously Requested data DAP HAP Completion of transferring requested data Empty area Read ahead data 4 The disk drive performs the read ahead operation for all area of segment with overwri...

Page 218: ...he same time as the disk drive starts transferring data to the host system 1 In the case that the contents of buffer is as follows at receiving a read command Start LBA Last LBA DAP HAP Continued from the previous read request data Hit data Read ahead data 2 The disk drive starts the read ahead operation to the empty area that becomes vacant by data transfer at the same time as the disk drive star...

Page 219: ...arts transferring the requested data from the address of which the requested data is stored After completion of command a previously existed cache data before the full hit reading are still kept in the buffer and the disk drive does not perform the read ahead operation 1 In the case that the contents of the data buffer is as follows for example and the previous command is a sequential read command...

Page 220: ...ot perform the read ahead operation after data transfer Following is an example of partially hit to the cache data Last LBA Cache data 1 The disk drive sets the HAP to the address where the partially hit data is stored and sets the DAP to the address just after the partially hit data HAP DAP Partially hit data Lack data 2 The disk drive starts transferring partially hit data and reads lack data fr...

Page 221: ... by the host system At this time if the write operation of the previous command is still been executed the drive continuously executes the write operation of the next command from the sector next to the last sector of the previous write operation Thus the latency time for detecting a target sector of the next command is eliminated This shortens the access time The drive generates an interrupt of c...

Page 222: ...ite cache function is operated with the following command WRITE SECTOR S WRITE MULTIPLE WRITE DMA IMPORTANT When Write Cache is permitted the writing of the data transferred from the host by the above mentioned Write Cache permit command into the disk medium may not be completed at the moment a normal ending interrupt has occurred In case a non recoverable error has occurred during receiving more ...

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Page 224: ... The physical specifications of the drive do not always correspond to these parameters The BIOS of a PC AT cannot make full use of the physical specifications of these drivers To make the best use of these drives a BIOS that can handle the standard parameters of these drives is required Command Commands are instructions to input data to and output data from a drive Commands are written in command ...

Page 225: ...e spindle motor is stopped and circuits other than the interface control circuit are sleeping The drive enters sleep mode when the host issues the SLEEP command Reserved Reserved bits bytes and fields are set to zero and unusable because they are reserved for future standards Rotational delay Time delay due to disk rotation The mean delay is the time required for half a disk rotation The mean dela...

Page 226: ...rmation posted from the drive to the host when command execution is ended The status indicates the command termination state VCM Voice coil motor The voice coil motor is excited by one or more magnets In this drive the VCM is used to position the heads accurately and quickly ...

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Page 228: ...ter DRDY Drive ready DRQ Ddata request bit DSC Drive seek complete DWF Drive write fault E ECC Error checking and correction ER Error register ERR Error F FR Feature register H HA Host adapter HDD Hard disk drive I IDNF ID not found IRQ14 Interrupt request 14 L LED Light emitting diode M MB Mega byte MB S Mega byte per seconds MPU Micro processor unit P PCA Printed circuit assembly PIO Programmed ...

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Page 230: ... F Fair P Poor General appearance Technical level Organization Clarity Accuracy Illustration Glossary Acronyms Abbreviations Index Comments Suggestions List any errors or suggestions for improvement Page Line Contents Please send this form to the address below We will use your comments in planning future editions Address Fujitsu Learning Media Limited 22 7 Minami Ooi 6 Chome Shinagawa Ku Tokyo 140...

Page 231: ...C141 E104 03EN C141 E104 03EN MHL2300AT MHM2200AT MHM2150AT MHM2100AT DISK DRIVES PRODUCT MANUAL MHL2300AT MHM2200AT MHM2150AT MHM2100AT DISK DRIVES PRODUCT MANUAL ...

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