MSC8144E Reference Manual, Rev. 3
11-34
Freescale
Semiconductor
Internal Memory Subsystem
11.8.9 L2 ICache Cacheable Area Start Address (L2IC_CSA)
L2IC_CSA configures the start address of the cacheable area in the L2 ICache. To assure proper
operation, do not change this register while the L2IC_CEN[DEN] bit is set. This register is reset
by a soft reset. Table 11-15 defines the L2IC_CSA bit fields.
—
15–14
0
Reserved. Write to zero for future compatibility.
DBGAD
13–0
0
Debug Access Address
This field contains the access address in debug mode (extended up to 64 KB) as bits 13–0 on the
input address bus, using the following format:
• Index: bits 13–8
• VBR offset: bits 7–4
• Long (32-bit) offset within the VBR: bits 3–2
• Byte offset within the long: bits 1–0
To make an aligned access to the DBG_ACS_SIZE, use only the following options:
• For DBG_ACS_SIZE = 0b10 (long), the byte offset must = 0b00 only.
• For DBG_ACS_SIZE = 0b01 (word), the byte offset can be 0b00 or 0b10.
• For DBG_ACS_SIZE = 0b00 (byte), the byte offset can be 0b00, 0b01, 0b10, or 0b11.
L2IC_CSA
L2 ICache Cacheable Area Start Address
Offset 0xC04
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
—
SA
Type
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SA
Type
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 11-15. L2IC_CSA Bit Descriptions
Name
Reset
Description
Settings
—
31–20
0
Reserved. Write to zero for future compatibility.
SA
19–0
0
Start Address
Contains the 20 msbs of the L2 ICache cacheable window start address (bits 31–12). The 12 lsbs
are all zeros.
Table 11-14. L2IC_DBG_ACS Bit Descriptions (Continued)
Name
Reset
Description
Settings
Summary of Contents for MSC8144E
Page 1: ...MSC8144E Reference Manual Quad Core Media Signal Processor MSC8144ERM Rev 3 July 2009 ...
Page 48: ...MSC8144E Reference Manual Rev 3 xlviii Freescale Semiconductor ...
Page 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...
Page 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...
Page 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
Page 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...
Page 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...
Page 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...
Page 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...
Page 1070: ...MSC8144E Reference Manual Rev 3 21 28 Freescale Semiconductor Timers ...