Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
18-100 Freescale Semiconductor
Table 18-55 describes a list of methods to generate eDMA requests by the eQADC.
Table 18-54. eQADC FIFO Interrupt Summary
1
1
For details refer to Section 18.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn) ,” and
Section 18.3.2.7, “eQADC Interrupt and eDMA Control Registers 0–5 (EQADC_IDCRn) .”
Interrupt Condition Clearing Mechanism
Non Coherency Interrupt NCIE n = 1
NCF n = 1
Clear NCF n bit by writing a 1 to the bit.
Trigger Overrun Interrupt
2
TORIE n = 1
TORF n =1
Clear TORF n bit by writing a 1 to the bit.
Pause Interrupt PIE n = 1
PF n =1
Clear PF n bit by writing a 1 to the bit.
End of Queue Interrupt EOQIE n = 1
EOQF n = 1
Clear EOQF n bit by writing a 1 to the bit.
Command FIFO
Underflow Interrupt
2
CFUIE n = 1
CFUF n = 1
Clear CFUF n bit by writing a 1 to the bit.
Command FIFO
Fill Interrupt
CFFE n = 1
CFFS n = 0
CFFF n = 1
Clear CFFF n bit by writing a 1 to the bit.
Result FIFO Overflow
Interrupt
2
2
Apart from generating an independent interrupt request for when a RFIFO overflow interrupt, a CFIFO underflow
interrupt, and a CFIFO trigger overrun interrupt occurs, the eQADC also provides a combined interrupt request at
which these requests from ALL CFIFOs are ORed. Refer to
Figure 18-54 for details.
RFOIE n = 1
RFOF n = 1
Clear RFOF n bit by writing a 1 to the bit.
Result FIFO
Drain Interrupt
RFDE n = 1
RFDS n = 0
RFDF n = 1
Clear RFDF n bit by writing a 1 to the bit.
Table 18-55. eQADC FIFO eDMA Summary
1
1
For details refer to Section 18.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn) ,” and
Section 18.3.2.7, “eQADC Interrupt and eDMA Control Registers 0–5 (EQADC_IDCRn) .”
eDMA Request Condition Clearing Mechanism
Result FIFO Drain
eDMA Request
RFDE n = 1
RFDS n = 1
RFDF n = 1
The eQADC automatically clears the RFDF n when RFIFO n becomes
empty. Writing 1 to the RFDF n bit is not allowed while RDFS = 1.
Command FIFO Fill
eDMA Request
CFFE n = 1
CFFS n = 1
CFFF n = 1
The eQADC automatically clears the CFFF n when CFIFO n becomes
full. Writing 1 to the CFFF n bit is not allowed while CFDS = 1.