Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 18-83
Figure 18-45. Non-coherency Detection When Transfers From a Command Sequence Are Interrupted
18.4.4 Result FIFOs
18.4.4.1 RFIFO Basic Functionality
There are six RFIFOs located in the eQADC. Each RFIFO is four entries deep, and each RFIFO entry is
16 bits long. Each RFIFO serves as a temporary storage location for the one of the result queues allocated
in system memory. All result data is saved in the RFIFOs before being moved into the system result
queues. When an RFIFO is not empty, the eQADC sets the corresponding EQADC_FISRn[RFDF] (see
Section 18.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn) ”). If
EQADC_IDCR n [RFDE] is asserted (see Section 18.3.2.7), the eQADC generates a request so that the
RFIFO entry is moved to a result queue. An interrupt request, served by the host CPU, is generated when
EQADC_IDCR
n [RFDS] is negated, and an eDMA request, served by the eDMA, is generated when
RFDS is asserted. The host CPU or the eDMA responds to these requests by reading EQADC_RFPRn (see
Section 18.3.2.5, “eQADC Result FIFO Pop Registers 0–5 (EQADC_RFPRn) ”) to retrieve data from the
RFIFO.
NOTE
Reading a word, halfword, or any bytes from EQADC_RFPR n pops an
entry from RFIFO n , and the RFCTR n field is decremented by 1.
The eDMA controller should be configured to read a single result (16-bit
data) from the RFIFO pop registers for every asserted eDMA request it
acknowledges. Refer to
Section 18.5.2, “eQADC/eDMA Controller
Interface ” for eDMA controller configuration guidelines.
Figure 18-46 describes the important components in the RFIFO. Each RFIFO is implemented as a circular
set of registers to avoid the need to move all entries at each push/pop operation. The pop next data pointer
always points to the next RFIFO message to be retrieved from the RFIFO when reading eQADC_RFPR.
The receive next data pointer points to the next available RFIFO location for storing the next incoming
Command sequence became non-coherent before command 4
was transferred. After command transfers resume, eQADC checks
for coherency only after command 4.
CF5_CB1_CM6 7
CF5_CB1_CM5 6
CF5_CB1_CM4 5
CF5_CB1_CM3 4
CF5_CB1_CM2 3
CF5_CB1_CM1 2
CF5_CB1_CM0 1
CF5_CB1_CM13 14
CF5_CB1_CM12 13
CF5_CB1_CM11 12
CF5_CB1_CM10 11
CF5_CB1_CM9 10
CF5_CB1_CM8 9
CF5_CB1_CM7 8
Command sequence became non-coherent before command 11
was transferred. After command transfers resume, eQADC checks
for coherency only after command 11.