Freescale Semiconductor MPC5565, Reference Manual

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Reset
MPC5565 Microcontroller Reference Manual, Rev. 1.0
4-4 Freescale Semiconductor
The following figure shows the reset status register:
The following table describes the fields in the reset status register:
Address: Base + 0x000C Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R PORS ERS LLRS LCRS WDRS CRS 0 0 0 0 0 0 0 0 SSRS
SERF
W
Reset
1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R WKP
CFG
0 0 0 0 0 0 0 0 0 0 0 0 BOOTCFG
RGF
W
Reset —
2
0 0 0 0 0 0 0 0 0 0 0 0 —
3
—
3
0
1
The RESET values for this register are defined for power-on reset only.
2
The RESET value of this bit or field is determined by the value latched on the pin or pins at the negation of the last
reset.
3
The RESET value of this bit or field is determined by the value latched on the pin or pins at the negation of the last
reset. BOOTCFG can also be loaded with a default instead of what is on the pin or pins.
Figure 4-1. Reset Status Register (SIU_RSR)
Table 4-2. SIU_RSR Field Descriptions
Field Description
0
PORS
Power-on reset status
0 No power-on reset has occurred.
1 A power-on reset has occurred.
1
ERS
External reset status
0 No external reset has occurred.
1 An external reset has occurred.
The ERS bit is also set during a POR event.
2
LLRS
Loss-of-lock reset status
0 No loss-of-lock reset has occurred.
1 A loss-of-lock reset has occurred.
3
LCRS
Loss-of-clock reset status
0 No loss-of-clock reset has occurred.
1
A loss-of-clock reset has occurred due to a loss of the reference or failure of the FMPLL.
4
WDRS
Watchdog timer/debug reset status
0 No watchdog timer or debug reset occurred.
1 A watchdog timer or debug reset occurred.
5
CRS
Checkstop reset status
0 No enabled checkstop reset occurred.
1 An enabled checkstop reset occurred.
6–13 Reserved.
14
SSRS
Software system reset status
0 No software system reset occurred.
1 A software system reset occurred.