Freescale Semiconductor MPC5565, Reference Manual

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e200z6 Core Complex
MPC5565 Microcontroller Reference Manual, Rev. 1.0
3-2 Freescale Semiconductor
Figure 3-1. e200z6 Block Diagram
3.1.2 Overview
The e200z6 core integrates an integer execution unit, branch control unit, instruction fetch and load/store
units, and a multi-ported register file capable of sustaining three read and two write operations per clock.
Most integer instructions execute in a single-clock cycle. Branch target prefetching is performed by the
branch target address cache to allow single-cycle branches in many cases.
The e200z6 core complex is built on a single-issue, 32-bit Power Architecture design with 64-bit
general-purpose registers (GPRs). Power Architecture floating-point instructions are not supported in
hardware, but are trapped and may be emulated by software. A signal processing extension (SPE) auxiliary
CPU
control logic
Load/
cache
Data
Memory
Management
Unit (MMU)
Address
store
unit
Control
Instruction unit
Address
Branch
unit
PC
unit
Instruction buffer
GPRs
CR
SPR
Multiply
unit
Bus interface unit
Control
32
64
Data out
64
64
Signal
Processing
OnCE/NEXUS 1/
control logic
Engine
(SPE APU)
Unified
Integer
execution
unit
Data in
64
CTR
XER
LR
(64-bit)
NEXUS 3
8 KB