Freescale Semiconductor MPC5200 Application Note Download Page 3

ATA Interface

MPC5200 ATA Interface, Rev. 0

Freescale Semiconductor

3

2.1

Electrical Characteristics

ATA is a voltage level interface and the table below defines the voltage levels for logical ones and zeroes 
or input and output values.

2.2

Signals

Table 1. ATA DC Characteristics

Description

Min

Max

I

oL

Driver sink current

1

 

NOTES:

1

 I

oL

 for DASP shall be 12 mA minimum to meet legacy timing and signal integrity.

4 mA

I

oH

Driver source current

2

2

 IoH value at 400 mA is insufficient in the case of DMARQ that is typically pulled low by a 5.6 kW 
resistor.

400

µ

A

V

iH

Voltage input high (logical one)

2.0 Vdc

V

iL

Voltage input low (logical zero)

0.8 Vdc

V

oH

Voltage output high (I

oH

=-400 

µ

A, logical one)

2.4 Vdc

V

oL

Voltage output low (I

oL

= 12 mA, logical zero)

0.5 Vdc

Table 2. ATA Signals

ATA Signal

ATA Acronym

 MPC5200 Pin

Direction

 40-Pin 

ATA Cable

Cable select

CSEL

>

28

Chip select 0

CS0-

ATA_CSB0

>

37

Chip select 1

CS1-

ATA_CSB1

>

38

Data bus bit 0

DD0

ATA_DATA_0

<>

17

Data bus bit 1

DD1

ATA_DATA_1

<>

15

Data bus bit 2

DD2

ATA_DATA_2

<>

13

Data bus bit 3

DD3

ATA_DATA_3

<>

11

Data bus bit 4

DD4

ATA_DATA_4

<>

9

Data bus bit 5

DD5

ATA_DATA_5

<>

7

Data bus bit 6

DD6

ATA_DATA_6

<>

4

Data bus bit 7

DD7

ATA_DATA_7

<>

3

Data bus bit 8

DD8

ATA_DATA_8

<>

4

Data bus bit 9

DD9

ATA_DATA_9

<>

6

Data bus bit 10

DD10

ATA_DATA_10

<>

8

Data bus bit 11

DD11

ATA_DATA_11

<>

10

Data bus bit 12

DD12

ATA_DATA_12

<>

12

Data bus bit 13

DD13

ATA_DATA_13

<>

14

Summary of Contents for MPC5200

Page 1: ...roller is based on an e3001 core using the PowerPCTM instruction set The ATA interface is used to connect Hard disks CD ROMs DVDs Flash storage devices The MPC5200 ATA interface is fully compatible wi...

Page 2: ...ransfer is driven either by MPC5200 core PIO or by the BestComm DMA engine MDMA UDMA BestComm is designed to offload the MPC5200 core and can transfer data to from different peripherals simultaneously...

Page 3: ...2 0 Vdc ViL Voltage input low logical zero 0 8 Vdc VoH Voltage output high IoH 400 A logical one 2 4 Vdc VoL Voltage output low IoL 12 mA logical zero 0 5 Vdc Table 2 ATA Signals ATA Signal ATA Acron...

Page 4: ...5 18 Device active or slave Device 1 present DASP 39 Device address bit 0 DA0 ATA_SA_0 35 Device address bit 1 DA1 ATA_SA_1 33 Device address bit 2 DA2 ATA_SA_2 36 DMA acknowledge DMACK ATA_DACK_B 29...

Page 5: ...DD 4 DD 3 DD 2 DD 1 DD 0 First transfer Byte 1 Byte 0 Second transfer Byte 3 Byte 2 Last transfer Byte n 1 Byte n 2 Table 4 ATA Register Address Chip Select Decoding Addresses Functions MPC5200 regis...

Page 6: ...by using the LBA bit in the ATA drive device head register The LBA bit must be set if the host uses LBA addressing mode The MPC5200 allows 27 bit LBA addressing per device 2 7 ATA Programming Model F...

Page 7: ...start with the software examples published on the sample code CD These software examples include a set of already pre cooked BestComm tasks that handle all required peripherals via the BestComm C API...

Page 8: ...rdized function calls ATA device e g DVD drive ATA cable MDMA UDMA data ATA data buffers ATA software driver ATA level shifters ATA host interface MPC5200 Embedded computer Peripheral FIFOs Set of pre...

Page 9: ...le ATA clock in CDM clock enable register Install ATA interrupt handler and BestComm interrupt handler for MDMA UDMA modes Enable ATA BestComm interrupt 2 PIO initialization BestComm not needed for PI...

Page 10: ...AD BUFFER READ MULTIPLE READ SECTOR S SMART READ DATA PIO data out command protocol CFA WRITE MULTIPLE WITHOUT ERASE CFA WRITE SECTORS WITHOUT ERASE DOWNLOAD MICROCODE SECURITY DISABLE PASSWORD SECURI...

Page 11: ...Initialization Protocol Steps 1 Select drive according to device selection protocol in ATA ATAPI 4 spec a Wait for BSY 0 and DRQ 0 in ATA drive alternate status register b Write ATA drive device head...

Page 12: ...tcomm In the case of Bestcomm when snooping is not used cache needs to be invalidated first 2 9 3 PIO Data Write 2 9 3 1 PIO Data Out Command Protocol Steps 1 Select drive according to device selectio...

Page 13: ...READ in ATA drive device command register 8 If UDMA set UDMA bit UDAMA in ATA drive device command register Clear it for MDMA 9 Set Drive Interrupt bit IE in ATA drive device command register NOTE Thi...

Page 14: ...ive device command register by writing a logical zero bits HUT FR FE IE UDAMA READ WRITE The pending ATA drive interrupt is cleared by reading of the ATA drive device sstatus register as it is specifi...

Page 15: ...look ahead write cache etc First they need to be checked in the identify table to see if supported and then enabled by the SET FEATURES command Using IPBI 132 MHz as described above Utilizing Bestcom...

Page 16: ...d in Figure 4 is not as expected The answer is simple it is writing reading the same LBA address with the look ahead write cache feature disabled The time needed to read data from the interface is muc...

Page 17: ...E32B Programming Environments Manual for 32 Bit Implementations of the PowerPC Architecture www freescale com G2CORERM G2 Core Reference Manual www freescale com ATA ATAPI 4 AT Attachment with Packet...

Page 18: ...ata_dma1 MBAR 0x3A10 32 ATA multiword DMA timing 2 ata_dma2 MBAR 0x3A14 32 ATA ultra DMA timing 1 ata_udma1 MBAR 0x3A18 32 ATA ultra DMA timing 2 ata_udma2 MBAR 0x3A1C 32 ATA ultra DMA timing 3 ata_ud...

Page 19: ...res ata_drive_ftr MBAR 0x3A64 8 write only ATA drive error 8 read only ATA drive sector count ata_drive_sc MBAR 0x3A68 8 R W ATA drive sector number ata_drive_sn MBAR 0x3A6C 8 R W ATA drive cylinder l...

Page 20: ...emiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or inciden...

Reviews: