Freescale Semiconductor MPC5200, Application Note, Page: 13 / 20

ATA Interface
MPC5200 ATA Interface, Rev. 0
Freescale Semiconductor 13
2.9.4 DMA Data Read
2.9.4.1 DMA Command Protocol Steps
1. Select drive according to the device selection protocol in ATA/ATAPI-4 spec:
a) Wait for BSY=0 and DRQ = 0 in ATA drive alternate status register
b) Write ATA drive device/head register with appropriate DEV bit and LBA bit
c) Wait 400 ns
d) Wait for BSY=0 and DRQ = 0 in ATA drive alternate status register
2. If snooping is not used, cache needs to be invalidated
3. Initialize and start BestComm ATA task
4. Set ATA FIFO alarm and granularity in ATA Rx/Tx FIFO alarm register, ATA Rx/Tx FIFO
control register
5. Set FIFO Reset bit (FR) in ATA drive device command register when the direction is switched
from Tx to Rx
6. Clear FIFO Reset bit (FR) in ATA drive device command register*
7. Set FIFO Flush in Rx Mode bit (FE) and Read bit (READ) in ATA drive device command
register*
8. If UDMA, set UDMA bit (UDAMA) in ATA drive device command register. Clear it for
MDMA*
9. Set Drive Interrupt bit (IE) in ATA drive device command register*
NOTE
This could be done just by one command.
10. Wait 400 ns
11. Wait for BSY=0 and DRQ = 0 in ATA drive alternate status register
12. Write ATA drive cylinder low register, ATA drive cylinder high register, ATA drive sector number
register, ATA drive sector count register
13. Wait 400 ns
14. Wait for BSY=0 and DRQ = 0 in ATA drive alternate status register
15. Write
READ DMA
command into ATA drive device command register
16. Wait for BestComm interrupt – indicates all data moved from ATA Rx FIFO to the RAM
2.9.5 DMA Data Write
2.9.5.1 DMA Command Protocol Steps
1. Select drive according to device selection protocol in ATA/ATAPI-4 spec:
a) Wait for BSY=0 and DRQ = 0 in ATA drive alternate status register
b) Write ATA drive device/head register with appropriate DEV bit and LBA bit
c) Wait 400 ns
d) Wait for BSY=0 and DRQ = 0 in ATA drive alternate status register