Freescale Semiconductor MK22FN256VDC12, Reference Manual

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37.3.8 Channel n Delay 1 register (PDBx_CHnDLY1)
Address: 4003_6000h base + 1Ch (40d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DLY
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_CHnDLY1 field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–0
DLY
PDB Channel Delay
These bits specify the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts
when the counter is equal to DLY. Reading these bits returns the value of internal register that is effective
for the current PDB cycle.
37.3.9 DAC Interval Trigger n Control register (PDBx_DACINTCn)
Address: 4003_6000h base + 150h (8d × i), where i=0d to 0d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
EXT TOE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_DACINTCn field descriptions
Field Description
31–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
EXT
DAC External Trigger Input Enable
This bit enables the external trigger for DAC interval counter.
0 DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising
edge is detected on selected trigger input source or software trigger is selected and SWTRIG is
written with 1.
1 DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input
triggers the DAC interval trigger.
Table continues on the next page...
Chapter 37 Programmable Delay Block (PDB)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc. 807