PMC memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_D001
Low Voltage Detect Status And Control 2 register
(PMC_LVDSC2)
8
R/W
00h
4007_D002 Regulator Status And Control register (PMC_REGSC)
8
R/W
04h
16.5.1 Low Voltage Detect Status And Control 1 register
(PMC_LVDSC1)
This register contains status and control bits to support the low voltage detect function.
This register should be written during the reset initialization program to set the desired
controls even if the desired settings are the same as the reset settings.
While the device is in the very low power or low leakage modes, the LVD system is
disabled regardless of LVDSC1 settings. To protect systems that must have LVD always
on, configure the Power Mode Protection (PMPROT) register of the SMC module
(SMC_PMPROT) to disallow any very low power or low leakage modes from being
enabled.
See the device's data sheet for the exact LVD trip voltages.
NOTE
The LVDV bits are reset solely on a POR Only event. The
register's other bits are reset on Chip Reset Not VLLS. For
more information about these reset types, refer to the Reset
section details.
Address: 4007_D000h base + 0h offset = 4007_D000h
Bit
7
6
5
4
3
2
1
0
Read
0
Write
Reset
0
0
0
1
0
0
0
0
PMC_LVDSC1 field descriptions
Field
Description
7
LVDF
Low-Voltage Detect Flag
This read-only status field indicates a low-voltage detect event.
0
Low-voltage event not detected
1
Low-voltage event detected
Table continues on the next page...
Memory map and register descriptions
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
364
Freescale Semiconductor, Inc.
