Address: Base a 0h offset
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
UARTx_BDH field descriptions
Field
Description
7
LBKDIE
LIN Break Detect Interrupt Enable
Enables the LIN break detect flag, LBKDIF, to generate interrupt requests based on the state of
LBKDDMAS.
0
LBKDIF interrupt requests disabled.
1
LBKDIF interrupt requests enabled.
6
RXEDGIE
RxD Input Active Edge Interrupt Enable
Enables the receive input active edge, RXEDGIF, to generate interrupt requests.
0
Hardware interrupts from RXEDGIF disabled using polling.
1
RXEDGIF interrupt request enabled.
5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4–0
SBR
UART Baud Rate Bits
The baud rate for the UART is determined by the 13 SBR fields. See
NOTE:
• The baud rate generator is disabled until C2[TE] or C2[RE] is set for the first time after
reset.The baud rate generator is disabled when SBR = 0.
• Writing to BDH has no effect without writing to BDL, because writing to BDH puts the data
in a temporary location until BDL is written.
46.3.2 UART Baud Rate Registers: Low (UARTx_BDL)
This register, along with the BDH register, controls the prescale divisor for UART baud
rate generation. To update the 13-bit baud rate setting, SBR[12:0], first write to BDH to
buffer the high half of the new value and then write to BDL. The working value in BDH
does not change until BDL is written. BDL is reset to a nonzero value, but after reset, the
baud rate generator remains disabled until the first time the receiver or transmitter is
enabled, that is, when C2[RE] or C2[TE] is set.
Address: Base a 1h offset
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
1
0
0
Chapter 46 Universal Asynchronous Receiver/Transmitter (UART)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
1139
