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MCF5441X Tower Module Hardware Specification 

Page 19 of 31 

 

The value of BLL[15:0] of serial boot header (7-byte) will determine whether the code will continue to 
load from SPI memory at offset 7 to internal SRAM and boot from internal SRAM. If the value of 
BLL[15:0] is cleared, the serial boot facility will not continue to access SPI memory after offset 6. 
Instead, it will depend on the SBF_RCON bit 29 to determine whether the code will continue to load at 
address 0 either from FlexBus or NAND flash. 
 

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Table 13 - Easy Configurable Serial RCON 

Summary of Contents for MCF5441X

Page 1: ...Freescale Semiconductor Inc Microcontroller Solutions Group MCF5441X Tower Module User Manual Rev 1 1...

Page 2: ...M 8 4 4 2 OSBDM Bootloader Mode 10 4 4 3 OSBDM Debug Interface 10 4 5 RS232 HEADERS 10 4 6 SDRAM INTERFACE 11 4 7 NAND FLASH MEMORY INTERFACES 11 4 8 ACCELEROMETER 11 4 9 POTENTIOMETER 12 4 10 TEMPERA...

Page 3: ...2 Reference Documents MCF54418 Reference Manual TWR M54418 Quick Start Guide TWR M54418 Schematics MCF54418 Data Sheet MMA7361L Data Sheet Three Axis Accelerometer DDR2 SDRAM Specification JESD79 2C T...

Page 4: ...asters 64 channel DMA controller DDR1 DDR2 Controller USB 2 0 On the Go controller with ULPI support Two smart card ports Two 10 100 Ethernet Controllers IEEE 1588 2002 SDHC host controller Two CAN mo...

Page 5: ...X provides hardware to evaluate as many of the configurations of the MCF5441x family as possible The TWR MCF5441X features Tower compatible processor board MCF54418 in a 256 MAPBGA package DDR2 SDRAM...

Page 6: ...LEDs DIP Switches and push buttons for user input Potentiometer Audio Speaker Header Only uses LM4889 audio power amplifier 4 Hardware Specification This section provides specification details for th...

Page 7: ...og Switches FEC RMII USB ULPI UARTs Flexbus I2 C CAN etc 4 2 Clocking The MCF54418 requires 2 clocks sources in order to enable proper internal timing A 25 MHz crystal is connected to EXTAL to generat...

Page 8: ...AND frequency must not be greater than 80MHz 4 3 System Power The TWR MCF5411X board is powered by 5V either from the OSBDM circuit via the miniAB USB connector or the Tower Elevator power connections...

Page 9: ...MCF5441x determines the debug mode BDM or JTAG This signal is controllable by J6 as shown below Debug Mode Pin JTAG No shunt BDM Shunt on 1 2 Table 3 J6 Headers The TCLK and PSTCLK signals are the onl...

Page 10: ...2 5 and 3 3 of AN3561 for details on installing and running the application Note The JM60 GUI Installer should be run before connecting the OSBDM in Bootloader Mode to a host USB port Otherwise the J...

Page 11: ...2Gbit 48 pin TSOP NAND Flash device MT29F2G16A The NAND Flash device may uses up to 256MB 2048 blocks at 64 pages per block The first four pages of block 0 may use for boot code with an 8 bit bus inte...

Page 12: ...onnected to the edge connectors for use on a module connected to the TWR ELEV To change the connection of ADC 0 1 and 2 use the Cut Trace pads CT3 CT6 and CT9 respectively Using a tool with a razor bl...

Page 13: ...om TWR MCF5441X s 3 3V power circuit The Parasite Powered method where the power source is from data bus is not used in this platform By default the One Wire digital temperature sensor is connected to...

Page 14: ...EV GPIO MCF54418 Signal Name LED TWR ELEV GPIO Configuration Cut Trace Pad GPIO_G0 LED1 Amber GPIO9 A9 CT3 GPIO_G1 LED2 Yellow GPIO7 A11 CT6 GPIO_G2 LED3 Green GPIO1 B21 CT9 GPIO_G3 LED4 Orange Red GP...

Page 15: ...ernal SRAM If not booting from internal SRAM serial RCON configuration will decide the boot source at address 0 either from FlexBus or NAND Flash 11 OFF OFF Table 9 J5 Headers 4 13 1 Default Configura...

Page 16: ...SW1 DIP switch settings For SW1 a value of 0 implies that the dip is switched On Override Pins in Reset Function SW1 DIP 1 Boot Memory 0 Default NAND Flash 1 FlexBus SW1 2 PLL mode 0 Disabled 1 Defau...

Page 17: ...ernal SPI memory through serial boot using the SBF_DI SBF_DO SBF_CS and SBF_CLK signals The internal configuration signals are driven to reflect the data being received from the external SPI memory to...

Page 18: ...scillator mode 0 Crystal oscillator mode 1 Oscillator bypass mode SBF_RCON 24 PLL mode 0 Disabled 1 Enabled SBF_RCON 23 22 PLL Reference Divider PLL_CR REFDIV 00 1 01 2 Override Serial RCON Function 1...

Page 19: ...fter offset 6 Instead it will depend on the SBF_RCON bit 29 to determine whether the code will continue to load at address 0 either from FlexBus or NAND flash Serial RCON BOOT Port size Boot Memory Re...

Page 20: ...Source 25Mhz External Jumper J3 UART4 Header J4 Audio Speaker Header J5 Boot Mode Jumpers J6 BDM JTAG mode Jumper J7 JM60 BKGD MS Header J8 TCK PSTCLK_OSBDM Jumper J9 USB Mini B OSBDM PWR J10 JM60 IR...

Page 21: ...Source Default Sink Alternate Sink Alternate Source Alternate Sink 1 4 3 2 Trace Cut Pad Default Source Default Sink Alternate Sink Alternate Source Alternate Sink 1 4 3 2 Trace Cut Pad Default Source...

Page 22: ...to PST0 redundant connection 1 3 Connects PST0 to Accelerometer G Select CT8 GPIO PG2 1 2 Connects GPIO to TWR ELEV 1 3 Connect GPIO to LED 3 CT9 ADC_2 1 2 Connects Accelerometer Z axis to ADC_2 1 3...

Page 23: ...0_MDC X A14 ETH_MDIO Ethernet PI0 RMII0_MDIO X A15 ETH_RXCLK Ethernet A16 ETH_RXDV Ethernet PJ7 RMII0_CRS_DV X A17 ETH_RXD3 Ethernet A18 ETH_RXD2 Ethernet A19 ETH_RXD1 Ethernet PJ6 RMII0_RXD1 X A20 ET...

Page 24: ...USB0_ID USB 0 A57 USB0_VBUS USB 0 A58 TMR7 Timer A59 TMR6 Timer A60 TMR5 Timer A61 TMR4 Timer A62 RSTIN_b Reset RESET X A63 RSTOUT_b Reset RSTOUT X A64 CLKOUT0 Clock PB7 FB_CLK X A65 GND Power Ground...

Page 25: ...2 ETH_COL Ethernet B13 ETH_RXER Ethernet PJ4 RMII0_RXER X B14 ETH_TXCLK Ethernet B15 ETH_TXEN Ethernet PJ0 RMII0_TXEN X B16 ETH_TXER Ethernet B17 ETH_TXD3 Ethernet B18 ETH_TXD2 Ethernet B19 ETH_TXD1 E...

Page 26: ...RQ_F Interrupt PC4 IRQ4 X B58 IRQ_E Interrupt PC4 IRQ4 X B59 IRQ_D Interrupt PC3 IRQ3 X B60 IRQ_C Interrupt PC3 IRQ3 X B61 IRQ_B Interrupt PC2 IRQ2 X B62 IRQ_A Interrupt PC1 IRQ1 X B63 FB_ALE FB_CS1_b...

Page 27: ..._MDC X C14 ETH_MDIO Ethernet RMII1_MDIO X C15 ETH_RXCLK Ethernet C16 ETH_RXDV Ethernet RMII1_CRS_DV X C17 GPIO GPIO C18 GPIO GPIO C19 ETH_RXD1 Ethernet RMII1_RXD1 X C20 ETH_RXD0 Ethernet RMII1_RXD0 X...

Page 28: ...C58 TMR16 Timer C59 TMR15 Timer C60 TMR14 Timer C61 TMR13 Timer C62 LCD_D15 LCD15 Display C63 LCD_D16 LCD16 Display C64 LCD_D17 LCD17 Display C65 GND Power Ground X C66 FB_BE3 LCD28 Flexbus Display C6...

Page 29: ...hernet D15 ETH_TXEN Ethernet RMII1_TXEN X D16 GPIO GPIO D17 GPIO GPIO PH0 DIP Switches X D18 GPIO GPIO PH1 DIP Switches X D19 ETH_TXD1 Ethernet RMII1_TXD1 X D20 ETH_TXD0 Ethernet RMII1_TXD0 X D21 ULPI...

Page 30: ...2 IRQ_I Interrupt D63 LCD_D18 LCD18 Display D64 LCD_D19 LCD19 Display D65 GND Power Ground X D66 FB_AD20 LCD42 Flexbus Display FB_AD20 X D67 FB_AD21 LCD43 Flexbus Display FB_AD21 X D68 FB_AD22 LCD44 F...

Page 31: ...ification Page 31 of 31 Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semicond...

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