5
TABLES
T
ABLE
1 – JP2, CS0
SELECT
................................................................................................................................................ 12
T
ABLE
2 – JP1, DRAM SIMM V
OLTAGE
S
ELECTION
........................................................................................................... 12
T
ABLE
3 – JP3, BDM
OR
JTAG O
PERATION
......................................................................................................................... 13
T
ABLE
4 – JP4, 3.3V
OR
5V
SUPPLY
FOR
THE
BDM I/F ........................................................................................................ 13
T
ABLE
5 – JP5, C
URRENT
MEASUREMENT
OF
THE
MCF5206e ................................................................................................ 13
T
ABLE
6 - dBUG C
OMMANDS
.............................................................................................................................................. 18
T
ABLE
7 - T
HE
M5206eLITE
MEMORY
MAP
......................................................................................................................... 39
T
ABLE
8 - T
HE
J9 (T
ERMINAL
) C
ONNECTOR
PIN
ASSIGNMENT
.................................................................................................. 41
T
ABLE
9 - T
HE
J4 C
ONNECTOR
PIN
ASSIGNMENT
..................................................................................................................... 42
T
ABLE
10 - T
HE
J5 C
ONNECTOR
PIN
ASSIGNMENT
................................................................................................................... 42
T
ABLE
11 - T
HE
J1 C
ONNECTOR
PIN
ASSIGNMENT
................................................................................................................... 43
T
ABLE
12 - T
HE
J2 C
ONNECTOR
PIN
ASSIGNMENT
................................................................................................................... 44
T
ABLE
13 - T
HE
J3 C
ONNECTOR
PIN
ASSIGNMENT
................................................................................................................... 45
T
ABLE
14 - T
HE
J10 C
ONNECTOR
PIN
ASSIGNMENT
................................................................................................................. 46
T
ABLE
15 - T
HE
J11 C
ONNECTOR
PIN
ASSIGNMENT
................................................................................................................. 46
T
ABLE
16 - T
HE
CN1 C
ONNECTOR
PIN
ASSIGNMENT
............................................................................................................... 47
FIGURES
F
IGURE
1 B
LOCK
D
IAGRAM
OF
THE
BOARD
............................................................................................................................... 7
F
IGURE
2 P
IN
ASSIGNMENT
FOR
J4 (T
ERMINAL
)
CONNECTOR
. ................................................................................................... 10
F
IGURE
3 S
YSTEM
C
ONFIGURATION
........................................................................................................................................ 11
F
IGURE
4 J
UMPER
AND
CONNECTOR
PLACEMENT
...................................................................................................................... 11
F
IGURE
5 F
LOW
D
IAGRAM
OF
dBUG O
PERATIONAL
M
ODE
. .................................................................................................... 15
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
..
