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MC9S12ZVM Family Reference Manual Rev. 1.3

Freescale Semiconductor

117

Chapter 3
Memory Mapping Control (S12ZMMCV1)

Table 3-1. Revision History

3.1

Introduction

The S12ZMMC module controls the access to all internal memories and peripherals for the S12ZCPU, and
the S12ZBDC module. It also provides access to the RAM for ADCs and the PTU module. The
S12ZMMC determines the address mapping of the on-chip resources, regulates access priorities and
enforces memory protection.

Figure 3-1

 shows a block diagram of the S12ZMMC module.

Revision

Number

Revision Date

Sections

Affected

Description of Changes

V01.03

27 Jul 2012

Corrected

Table 3-9

V01.04

27 Jul 2012

Added feature tags

V01.05

6 Aug 2012

Fixed wording

V01.06

12 Feb 2013

Figure 3-8

3.3.2.2/3-122

 • Changed “KByte:to “KB”
 • Corrected the description of the MMCECH/L register
 •

Summary of Contents for MC9S12ZVM series

Page 1: ...HCS12 Microcontrollers freescale com MC9S12ZVM Family Reference Manual Rev 1 3 20 JAN 2014 MC9S12ZVMRMV1 ...

Page 2: ...pplication in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claim...

Page 3: ...ule SCI 25 1 4 10 Multi Scalable Controller Area Network MSCAN 25 1 4 11 Serial Peripheral Interface Module SPI 25 1 4 12 Analog to Digital Converter Module ADC 25 1 4 13 Supply Voltage Sensor BATS 26 1 4 14 On Chip Voltage Regulator system VREG 26 1 4 15 Gate Drive Unit GDU 26 1 4 16 Current Sense 27 1 5 Block Diagram 28 1 6 Device Memory Map 29 1 6 1 Part ID Assignments 32 1 7 Signal Description...

Page 4: ... 59 1 13 3 Motor Control Application Overview 59 1 13 4 BDCM Complementary Mode Operation 68 1 13 5 BLDC Six Step Commutation 72 1 13 6 PMSM Control 74 1 13 7 Power Domain Considerations 78 Chapter 2 Port Integration Module S12ZVMPIMV1 2 1 Introduction 83 2 1 1 Overview 83 2 1 2 Features 84 2 2 External Signal Description 84 2 3 Memory Map and Register Definition 89 2 3 1 Register Map 90 2 3 2 PIM...

Page 5: ...2ZINTV0 4 1 Introduction 129 4 1 1 Glossary 130 4 1 2 Features 130 4 1 3 Modes of Operation 131 4 1 4 Block Diagram 131 4 2 External Signal Description 132 4 3 Memory Map and Register Definition 132 4 3 1 Module Memory Map 132 4 3 2 Register Descriptions 133 4 4 Functional Description 138 4 4 1 S12Z Exception Requests 138 4 4 2 Interrupt Prioritization 138 4 4 3 Priority Decoder 139 4 4 4 Reset Ex...

Page 6: ...e 177 5 4 9 Hardware Handshake Disabled ACK Pulse Disabled 178 5 4 10 Single Stepping 179 5 4 11 Serial Communication Timeout 180 5 5 Application Information 180 5 5 1 Clock Frequency Considerations 180 Chapter 6 S12Z Debug S12ZDBGV2 Module 6 1 Introduction 181 6 1 1 Glossary 181 6 1 2 Overview 182 6 1 3 Features 182 6 1 4 Modes of Operation 183 6 1 5 Block Diagram 183 6 2 External Signal Descript...

Page 7: ... 3 7 ECC Debug Behavior 240 Chapter 8 S12 Clock Reset and Power Management Unit S12CPMU_UHV_V6 8 1 Introduction 243 8 1 1 Features 244 8 1 2 Modes of Operation 246 8 1 3 S12CPMU_UHV_V6 Block Diagram 249 8 2 Signal Description 251 8 2 1 RESET 251 8 2 2 EXTAL and XTAL 251 8 2 3 VSUP Regulator Power Input Pin 251 8 2 4 VDDA VSSA Regulator Reference Supply Pins 251 8 2 5 VDDX VSSX Pad Supply Pins 251 ...

Page 8: ...ion for COP and API usage 305 8 7 3 Application Information for PLL and Oscillator Startup 305 Chapter 9 Analog to Digital Converter ADC12B_LBA_V1 9 1 Introduction 307 9 2 Key Features 309 9 2 1 Modes of Operation 310 9 2 2 Block Diagram 313 9 3 Signal Description 314 9 3 1 Detailed Signal Descriptions 314 9 4 Memory Map and Register Definition 315 9 4 1 Module Memory Map 315 9 4 2 Register Descri...

Page 9: ...External Signal Description 376 10 2 1 VSUP Voltage Supply Pin 376 10 3 Memory Map and Register Definition 377 10 3 1 Register Summary 377 10 3 2 Register Descriptions 377 10 4 Functional Description 381 10 4 1 General 381 10 4 2 Interrupts 381 Chapter 11 Timer Module TIM16B4CV3 Block Description 11 1 Introduction 385 11 1 1 Features 385 11 1 2 Modes of Operation 385 11 1 3 Block Diagrams 386 11 2...

Page 10: ...ral 439 12 4 2 Message Storage 439 12 4 3 Identifier Acceptance Filter 442 12 4 4 Modes of Operation 448 12 4 5 Low Power Options 450 12 4 6 Reset Initialization 454 12 4 7 Interrupts 454 12 5 Initialization Application Information 456 12 5 1 MSCAN initialization 456 12 5 2 Bus Off Recovery 456 Chapter 13 Programmable Trigger Unit PTUV2 13 1 Introduction 457 13 1 1 Features 457 13 1 2 Modes of Ope...

Page 11: ... Signals pmf_reloada b c 490 14 2 8 PWM Reload Is Asynchronous Signal pmf_reload_is_async 490 14 3 Memory Map and Registers 491 14 3 1 Module Memory Map 491 14 3 2 Register Descriptions 496 14 4 Functional Description 523 14 4 1 Block Diagram 523 14 4 2 Prescaler 524 14 4 3 PWM Generator 524 14 4 4 Independent or Complementary Channel Operation 528 14 4 5 Deadtime Generators 529 14 4 6 Top Bottom ...

Page 12: ...ate Generation 577 15 4 5 Transmitter 578 15 4 6 Receiver 583 15 4 7 Single Wire Operation 591 15 4 8 Loop Operation 592 15 5 Initialization Application Information 592 15 5 1 Reset Initialization 592 15 5 2 Modes of Operation 593 15 5 3 Interrupt Operation 593 15 5 4 Recovery from Wait Mode 596 15 5 5 Recovery from Stop Mode 596 Chapter 16 Serial Peripheral Interface S12SPIV5 16 1 Introduction 59...

Page 13: ...ns 626 17 2 4 HS 2 0 High Side Source Pins 626 17 2 5 VLS 2 0 Voltage Supply for Low Side Pre Drivers 626 17 3 Memory Map and Register Definition 628 17 3 1 Register Summary 628 17 3 2 Register Descriptions 629 17 4 Functional Description 647 17 4 1 General 647 17 4 2 Low Side FET Pre Drivers 647 17 4 3 High Side FET Pre Driver 648 17 4 4 Charge Pump 650 17 4 5 Desaturation Error 651 17 4 6 Phase ...

Page 14: ...rrupt Service Routine ISR 682 Chapter 19 128 KB Flash Module S12ZFTMRZ128K512V2 19 1 Introduction 686 19 1 1 Glossary 686 19 1 2 Features 687 19 1 3 Block Diagram 688 19 2 External Signal Description 688 19 3 Memory Map and Registers 689 19 3 1 Module Memory Map 689 19 3 2 Register Descriptions 693 19 4 Functional Description 713 19 4 1 Modes of Operation 713 19 4 2 IFR Version ID Word 713 19 4 3 ...

Page 15: ...ecifications C 1 ADC Operating Characteristics 763 Appendix D LINPHY Electrical Specifications D 1 Static Electrical Characteristics 769 D 2 Dynamic Electrical Characteristics 770 Appendix E GDU Electrical Specifications Appendix F NVM Electrical Parameters F 1 NVM Timing Parameters 777 F 2 NVM Reliability Parameters 780 F 3 NVM Factory Shipping Condition 780 Appendix G BATS Electrical Specificati...

Page 16: ...MC 794 L 4 0x0100 0x017F S12ZDBG 795 L 5 0x0200 0x02FF PIM 799 L 6 0x0380 0x039F FTMRZ128K512 803 L 7 0x03C0 0x03CF SRAM_ECC_32D7P 804 L 8 0x0500 x053F PMF15B6C 805 L 9 0x0580 0x059F PTU 809 L 10 0x05C0 0x05FF TIM0 811 L 11 0x0600 0x063F ADC0 813 L 12 0x0640 0x067F ADC1 815 L 13 0x06A0 0x06BF GDU 817 L 14 0x06C0 0x06DF CPMU 818 L 15 0x06F0 0x06F7 BATS 820 L 16 0x0700 0x0707 SCI0 820 L 17 0x0710 0x...

Page 17: ...n of several key system components into a single device optimizing system architecture and achieving significant space savings The MC9S12ZVM Family delivers all the advantages and efficiencies of a 16 bit MCU while retaining the low cost power consumption EMC and code size efficiency advantages currently enjoyed by users of existing S12 X families The MC9S12ZVM Family is available in two different...

Page 18: ...er features are common to all MC9S12ZVM Family members 1 2 2 Functional Differences Between N06E and 0N95G Masksets NOTE N95G also includes bug fixes that are not listed here because they do not constitute Table 1 2 S12ZVM Family Differences Feature S12ZVML32 S12ZVM32 S12ZVML64 S12ZVMC64 S12ZVML128 S12ZVMC128 Flash ECC 32 KB 32 KB 64 KB 64 KB 128 KB 128 KB EEPROM ECC 512 Bytes 512 Bytes 512 Bytes ...

Page 19: ...ced baud rate options LINPHY Direct Power Injection DPI robustness improvements TX dominant timeout feature Internal pull up adjusted to stay in 27KOhm to 40KOhm range OSC CPMU Added full swing Pierce mode Added a configuration bit OMRE Oscillator Monitor Reset Enable that will enable the Monitor Reset By default clock monitor reset disabled OMRE 0 PTU Allow swapping the trigger list at every relo...

Page 20: ...e pre regulator LDO Low Dropout Voltage Regulator typically 11V High side gate supply generated using bootstrap circuit with external diode and capacitor Sustaining charge pump with two external capacitors and diodes High side drain HD monitoring on internal ADC channel using HD 5 voltage Two parallel analog to digital converters ADC with 12 bit resolution and up to 9 channels available on externa...

Page 21: ...on and databus 32 Bit ALU 24 bit addressing of 16MB linear address space Instructions and Addressing modes optimized for C Programming Compiler Optimized address path so it is capable to run at 50MHz without Flash wait states MAC unit 32bit 32bit 32bit Hardware divider Single cycle multi bit shifts Barrel shifter Special instructions for fixed point math Unimplemented opcode traps Unprogrammed byt...

Page 22: ...NVM and system RAM 1 4 2 2 Flash On chip flash memory on the MC9S12ZVM family on the features the following Up to128 KB of program flash memory 32 data bits plus 7 syndrome ECC error correction code bits allow single bit fault correction and double fault detection Erase sector size 512 bytes Automated program and erase algorithm User margin level setting for reads Protection scheme to prevent acci...

Page 23: ... can be enabled STOP the oscillator is stopped in this mode all clocks are switched off and all counters and dividers remain frozen with the exception of the COP and API which can optionally run from ACLK 1 4 3 1 Internal Phase Locked Loop IPLL Phase locked loop clock frequency multiplier No external components required Reference divider and multiplier allow large variety of clock rates Automatic ...

Page 24: ... Center aligned or edge aligned outputs Programmable clock select logic with a wide range of frequencies Programmable fault detection 1 4 7 Programmable Trigger Unit PTU Enables synchronization between PMF and ADC 2 trigger input sources and software trigger source 2 trigger outputs One 16 bit delay register pre trigger output Operation in One Shot or Continuous modes 1 4 8 LIN physical layer tran...

Page 25: ...work MSCAN Implementation of the CAN protocol Version 2 0A B Five receive buffers with FIFO storage scheme Three transmit buffers with internal prioritization using a local priority concept Flexible maskable identifier filter supports two full size 32 bit extended identifier filters or four 16 bit filters or either 8 bit filters Programmable wake up functionality with integrated low pass filter 1 ...

Page 26: ...UP Power on reset POR Low voltage reset LVR for VDDX domain External ballast device support to reduce internal power dissipation Capable of supplying both the MCU internally plus external components Over temperature interrupt Internal voltage regulator Linear voltage regulator with bandgap reference Low voltage detect on VDDA Power on reset POR circuit Low voltage reset for VDD domain Package opti...

Page 27: ...Chapter 1 Device Overview MC9S12ZVM Family MC9S12ZVM Family Reference Manual Rev 1 3 Freescale Semiconductor 27 1 4 16 Current Sense 2 channel integrated op amp functionality ...

Page 28: ...0_2 VSS1 Low Power Pierce Oscillator SCI0 Asynchronous Serial IF RXD0 TXD0 MOSI0 SS0 SCK0 MISO0 SPI0 Synchronous Serial IF PS2 PS3 PS4 PS5 Voltage Regulator Nominal 12V Block Diagram shows the maximum configuration Not all pins or all peripherals are available on all devices and packages Rerouting options are not shown PE0 PTE PE1 PTAD KWAD Analog Digital Converter Internal RC Oscillator PWM0 LIN0...

Page 29: ...0 0x001F INT 16 0x0020 0x006F Reserved 80 0x0070 0x008F MMC 32 0x0090 0x00FF MMC Reserved 112 0x0100 0x017F DBG 128 0x0180 0x01FF Reserved 128 0x0200 0x02FF PIM 256 0x0300 0x037F Reserved 128 0x0380 0x039F FTMRZ 32 0x03A0 0x03BF Reserved 32 0x03C0 0x03CF RAM ECC 16 0x03D0 0x04FF Reserved 304 0x0500 0x053F PMF 64 0x0540 0x057F Reserved 64 0x0580 0x059F PTU 32 0x05A0 0x05BF Reserved 32 0x05C0 0x05EF...

Page 30: ...ce is reserved for future use Writing to these locations has no effect Read access to these locations returns zero 0x0718 0x077F Reserved 104 0x0780 0x0787 SPI0 8 0x0788 0x07FF Reserved 120 0x0800 0x083F CAN0 64 0x0840 0x097F Reserved 320 0x0980 0x0987 LINPHY 8 0x0988 0x0FFF Reserved 1656 1 Address range 0x0690 0x069F on Maskset N06E Table 1 3 Module Register Address Ranges Address Module Size Byt...

Page 31: ...See Table 1 2 for individual device details 0x00_1000 0x00_0000 0x10_0000 0x1F_4000 0x80_0000 0xFF_FFFF RAM EEPROM Unmapped Program NVM Register Space 4 KB max 1 MByte 4 KB max 1 MByte 48 KB max 8 MB 6 MByte High address aligned Low address aligned 0x1F_8000 Unmapped address range 0x1F_C000 Reserved read only 6 KB NVM IFR 256 Byte Reserved 512 Byte 0x20_0000 ...

Page 32: ...ing at device level is described in 1 8 Internal Signal Mapping 1 7 1 Pin Assignment Overview Table 1 5 provides a summary of which ports are available Table 1 4 Assigned Part ID Numbers Device Mask Set Number Part ID Bonding Option MC9S12ZVM128 N06E 0x00170000 LIN MC9S12ZVM128 N06E 0x00170001 CAN VREG MC9S12ZVM128 N56G 0x00171000 LIN MC9S12ZVM128 1 1 This version for Freescale internal engineerin...

Page 33: ... reserved for factory test This pin has an internal pull down device NOTE The TEST pin must be tied to ground in all applications 1 7 2 3 MODC Mode C Signal The MODC signal is used as an MCU operating mode select during reset The state of this signal is latched to the MODC bit at the rising edge of RESET The signal has an internal pull up device 1 7 2 4 PAD 8 0 KWAD 8 0 Port AD Input Pins of ADC P...

Page 34: ...ins ADC1 has 4 analog input channels connected to PAD port pins 1 7 2 10 VRH VRL ADC Reference Signals VRH and VRL are the reference voltage input pins for the analog to digital converter 1 7 2 11 SPI0 Signals 1 7 2 11 1 SS0 Signal This signal is associated with the slave select SS functionality of the serial peripheral interface SPI0 1 7 2 11 2 SCK0 Signal This signal is associated with the seria...

Page 35: ...ut compare functionality of the timer TIM0 module 1 7 2 15 PWM 5 0 Signals The signals PWM 5 0 are associated with the PMF module digital channel outputs 1 7 2 16 PTU Signals 1 7 2 16 1 PTUT 1 0 Signals These signals are the PTU trigger output signals These signals are routed to pins for debugging purposes 1 7 2 16 2 PTURE Signal This signal is the PTU reload enable output signal This signal is ro...

Page 36: ...k signal used when the DBG module profiling feature is enabled This signal is output only During code profiling this is the clock signal that can be used by external development tools to sample the PDO signal 1 7 2 19 4 DBGEEV External Event Input This signal is the DBG external event input It is input only Within the DBG module it allows an external event to force a state sequencer transition or ...

Page 37: ...d current to drive the external FET 1 7 2 22 3 HG 2 0 High Side Gate signals The pins are the gate drives for the three high side power FETs The drivers provide a high current with low impedance to turn on and off the high side power FETs 1 7 2 22 4 HS 2 0 High Side Source signals The pins are the source connection for the high side power FETs and the drain connection for the low side power FETs T...

Page 38: ...nected if not used 1 7 2 22 11 VSSB Boost Ground signal This pin is a separate ground pin for the on chip boost converter switching device 1 7 2 22 12 VLS_OUT 11V Voltage Regulator Output This pin is the output of the integrated voltage regulator The output voltage is typically VVLS 11V The input voltage to the voltage regulator is the VSUP pin 1 7 2 22 13 AMPP 1 0 Current Sense Amplifier Non Inve...

Page 39: ...on current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible NOTE All ground pins must be connected together in the application 1 7 3 1 VDDX1 VDDX2 VSSX1 Digital I O Power and Ground Pins VDDX1 VDDX2 are voltage regulator outputs to supply the digital I O drivers The VSSX1 pin is the ground pin for the digital I O d...

Page 40: ...ltage regulator generates the on chip voltage supplies It must be protected externally against a reverse battery connection 1 7 4 Package and Pinouts The following package options are offered 64LQFP EP exposed pad with internal LIN PHY 64LQFP EP exposed pad without internal LIN PHY but with CAN VREG to support the addition of a low cost external CAN PHY The exposed pad must be connected to a groun...

Page 41: ... RXD1 KWS0 PS0 PTUT1 LP0TXD TXCAN0 TXD1 KWS1 PS1 MISO0 RXD1 KWS2 PS2 MOSI0 TXD1 DBGEEV KWS3 PS3 PDOCLK SCK0 KWS4 PS4 PDO SS0 KWS5 PS5 BCTL HD VCP BST VSSB CP VLS_OUT VSUP LGND VSSX1 VDDX1 PP0 EVDD1 KWP0 PWM0 ECLK FAULT5 XIRQ PP1 KWP1 PWM1 IRQ PP2 KWP2 PWM2 VDDF VSS1 PE0 EXTAL PE1 XTAL RESET PT3 IOC0_3 SS0 PT2 IOC0_2 PWM5 SCK0 PT1 IOC0_1 PWM4 MOSI0 TXD0 LP0DR1 PTURE PT0 IOC0_0 PWM3 MISO0 RXD0 HS1 1...

Page 42: ...XD1 KWS0 PS0 PTUT1 TXCAN0 TXD1 KWS1 PS1 MISO0 RXD1 KWS2 PS2 MOSI0 TXD1 DBGEEV KWS3 PS3 PDOCLK SCK0 KWS4 PS4 PDO SS0 KWS5 PS5 BCTL HD VCP BST VSSB CP VLS_OUT VSUP VDDC VSSX1 VDDX1 PP0 EVDD1 KWP0 PWM0 ECLK FAULT5 XIRQ PP1 KWP1 PWM1 IRQ PP2 KWP2 PWM2 VDDF VSS1 PE0 EXTAL PE1 XTAL RESET PT3 IOC0_3 SS0 PT2 IOC0_2 PWM5 SCK0 PT1 IOC0_1 PWM4 MOSI0 TXD0 PTURE PT0 IOC0_0 PWM3 MISO0 RXD0 HS1 VDDX2 TEST VSS2 V...

Page 43: ...PTUT1 TXD1 KWS1 PS1 MISO0 RXD1 KWS2 PS2 MOSI0 TXD1 DBGEEV KWS3 PS3 PDOCLK SCK0 KWS4 PS4 PDO SS0 KWS5 PS5 BCTL HD VCP BST VSSB CP VLS_OUT VSUP N C connect to ground on board VSSX1 VDDX1 PP0 EVDD1 KWP0 PWM0 ECLK FAULT5 XIRQ PP1 KWP1 PWM1 IRQ PP2 KWP2 PWM2 VDDF VSS1 PE0 EXTAL PE1 XTAL RESET PT3 IOC0_3 SS0 PT2 IOC0_2 PWM5 SCK0 PT1 IOC0_1 PWM4 MOSI0 PTURE PT0 IOC0_0 PWM3 MISO0 HS1 1 2 3 4 5 6 7 8 9 10 ...

Page 44: ...0 RXD1 RXCAN0 LP0RXD PTUT0 VDDX PERS PPSS Up 4 4 PS1 KWS1 TXD1 TXCAN0 LP0TXD PTUT1 VDDX PERS PPSS Up 5 5 PS2 KWS2 RXD1 MISO0 VDDX PERS PPSS Up 6 6 PS3 KWS3 DBGEEV TXD1 MOSI0 VDDX PERS PPSS Up 7 7 PS4 KWS4 SCK0 PDOCLK VDDX PERS PPSS Up 8 8 PS5 KWS5 SS0 PDO VDDX PERS PPSS Up 9 9 BCTL 10 10 HD 11 11 VCP 12 12 BST 13 13 VSSB 14 14 CP 15 15 VLS_OUT 16 16 VSUP VSUP 17 17 VDDX2 VDDX 18 18 TEST RESET Down...

Page 45: ... KWAD6 AN1_1 AMPM1 SS0 VDDA PERADL PPSADL Off 28 28 PAD7 KWAD7 AN1_2 AMPP1 VDDA PERADL PPSADL Off 29 29 PAD8 KWAD8 AN1_3 VRH VDDA PERADH PPSADH Off 30 30 VDDA VDDA 31 31 VSSA 32 32 LS0 33 33 LG0 34 34 VLS0 35 35 VBS0 36 36 HG0 37 37 HS0 38 38 HS2 39 39 HG2 40 40 VBS2 41 41 VLS2 42 42 LG2 43 43 LS2 44 44 LS1 45 45 LG1 46 46 VLS1 47 47 VBS1 48 48 HG1 Table 1 6 Pin Summary Sheet 2 of 3 LQFP Option Fu...

Page 46: ...3 MISO0 RXD0 VDDX PERT PPST Off 51 51 PT1 IOC0_1 PWM4 MOSI0 TXD0 LP0DR1 PTURE VDDX PERT PPST Off 52 52 PT2 IOC0_2 PWM5 SCK0 VDDX PERT PPST Off 53 53 PT3 IOC0_3 SS0 VDDX PERT PPST Off 54 54 RESET VDDX TEST pin Up 55 55 PE1 XTAL VDDX PERE PPSE Down 56 56 PE0 EXTAL VDDX PERE PPSE Down 57 57 VSS1 58 58 VDDF VDDF 59 59 PP2 KWP2 PWM2 VDDX PERP PPSP Off 60 60 PP1 KWP1 PWM1 IRQ VDDX PERP PPSP Off 61 61 PP...

Page 47: ... Control Loop Overview Table 1 7 Usage of ADC0 Internal Channels ADCCMD_1 CH_SEL 5 0 ADC Channel Usage 0 0 1 0 0 0 Internal_0 ADC0 temperature sensor 0 0 1 0 0 1 Internal_1 VREG temperature sensor or bandgap VBG 1 1 Selectable in CPMU 0 0 1 0 1 0 Internal_2 GDU phase multiplexer voltage 0 0 1 0 1 1 Internal_3 GDU DC link voltage monitor 0 0 1 1 0 0 Internal_4 BATS VSUP sense voltage 0 0 1 1 0 1 In...

Page 48: ... frequency on leaving reset The bus frequency must not be changed before launching the ERASE_FLASH command 1 8 7 CPMU Connectivity The API clock generated in the CPMU is not mapped to a device pin in the MC9S12ZVM Family Table 1 9 Mapping of PMF signals PMF Connection Usage Channel0 High Side Gate and Source Pins HG 0 HS 0 Channel1 Low Side Gate and Source Pins LG 0 LS 0 Channel2 High Side Gate an...

Page 49: ...ed into this bit on the rising edge of RESET 1 9 1 1 Normal Single Chip Mode This mode is intended for normal device operation The opcode from the on chip memory is being executed after reset requires the reset vector to be programmed correctly The processor program is executed from internal memory 1 9 1 2 Special Single Chip Mode This mode is used for debugging operation boot strapping or securit...

Page 50: ...t that is not masked either locally or globally by a CCR bit ends system wait mode Static power modes Static power Stop modes are entered following the CPU STOP instruction unless an NVM command is active When no NVM commands are active the Stop request is acknowledged and the device enters either Stop or Pseudo Stop mode Further to the general system aspects of Stop mode discussed here the motor ...

Page 51: ...on could be enhanced by requiring a response authentication before any code can be downloaded Device security details are also described in the flash block description 1 10 1 Features The security features of the S12Z chip family are Prevent external access of the non volatile memories Flash EEPROM content Restrict execution of NVM commands 1 10 2 Securing the Microcontroller The chip can be secur...

Page 52: ...e BDC access to memory mapped resources is disabled The BDC can only be used to erase the EEPROM and Flash memory without giving access to their contents 1 10 4 Unsecuring the Microcontroller Unsecuring the microcontroller can be done using three different methods 1 Backdoor key access 2 Reprogramming the security bits 3 Complete memory erase 1 10 4 1 Unsecuring the MCU Using the Backdoor Key Acce...

Page 53: ...owing the programming of the security bits to the unsecured value This method requires that The application software previously programmed into the microcontroller has been designed to have the capability to erase and program the Flash options security byte The Flash sector containing the Flash options security byte is not protected 1 10 6 Complete Memory Erase The microcontroller can be unsecured...

Page 54: ...n None None Vector base 0x1E4 Reserved Vector base 0x1E0 Reserved Vector base 0x1DC Spurious interrupt None Vector base 0x1D8 XIRQ interrupt request X bit None Yes Yes Vector base 0x1D4 IRQ interrupt request I bit IRQCR IRQEN Yes Yes Vector base 0x1D0 RTI time out interrupt I bit CPMUINT RTIE See CPMU section Yes Vector base 0x1CC TIM0 timer channel 0 I bit TIM0TIE C0I No Yes Vector base 0x1C8 TIM...

Page 55: ... 0x160 FLASH command I bit FCNFG CCIE No Yes Vector base 0x15C CAN0 wake up I bit CAN0RIER WUPIE Yes Yes Vector base 0x158 CAN0 errors I bit CAN0RIER CSCIE OVRIE No Yes Vector base 0x154 CAN0 receive I bit CAN0RIER RXFIE No Yes Vector base 0x150 CAN0 transmit I bit CAN0TIER TXEIE 2 0 No Yes Vector base 0x14C to Vector base 0x148 Reserved Vector base 0x144 LINPHY over current interrupt I bit LPIE L...

Page 56: ...e 0xF4 Port AD interrupt I bit PIEADH PIEADH0 PIEADL PIEADL 7 0 Yes Yes Vector base 0xF0 PTU Reload Overrun I bit PTUIEH PTUROIE No Yes Vector base 0xEC PTU Trigger0 Error I bit PTUIEL TG0AEIE TG0REIE TG0TEIE No Yes Vector base 0xE8 PTU Trigger1 Error I bit PTUIEL TG1AEIE TG1REIE TG1TEIE No Yes Vector base 0xE4 PTU Trigger0 Done I bit PTUIEL TG0DIE No Yes Vector base 0xE0 PTU Trigger1 Done I bit P...

Page 57: ...e description 1 11 3 2 Reset While Flash Command Active If a reset occurs while any Flash command is in progress that command will be immediately aborted The state of the word being programmed or the sector block being erased is not guaranteed 1 11 3 3 I O Pins Refer to the PIM section for reset configurations of all peripheral module ports 1 11 3 4 RAM The system RAM arrays including their ECC sy...

Page 58: ...e the VDDA must be connected to VDDX at board level in the application the accuracy of the VDDA reference is limited by the internal voltage regulator accuracy In order to compensate for VDDA reference voltage variation in this case the reference voltage Table 1 14 Initial COP Rate Configuration NV 2 0 in FOPT Register CR 2 0 in CPMUCOP Register 000 111 001 110 010 101 011 100 100 011 101 010 110 ...

Page 59: ...rtedReference Result of internal channel conversion StoredReference Value in IFR location n ADC resolution 12 bit NOTE The ADC reference voltage VRH must remain at a constant level throughout the conversion process 1 13 2 SCI Baud Rate Detection The baud rate for SCI0 and SCI1 is achieved by using a timer channel to measure the data rate on the RXD signal 1 Establish the link For SCI0 Set T0IC3RR1...

Page 60: ...is available in application notes The applications described are as follows 1 BDCM wiper pumps fans 2 BLDCM pumps fans and blowers based on Hall sensors sensorless based on back EMF zero crossing comparators sensorless based on back EMF ADC measurements 3 PMSM high end wiper pumps fans and blowers simple sinewave commutation with position sensor Hall effect sine cos FOC with sine cos position sens...

Page 61: ...amic or asynchronous timing In the following text the event names given in bold type correspond to those shown in Figure 1 7 The PTU and ADC operate using lists stored in memory These lists define trigger points for the PTU commands for the ADC and results from the ADC If the PTU is enabled the reload and async_reload events are immediately passed through to the ADC and GDU modules PMF PTU ADC0 M ...

Page 62: ...g PTU trigger generates the trigger_x event for the associated ADC For simultaneous sampling the PTU generates simultaneous trigger_x events for both ADCs At the trigger_x event the ADC starts the first conversion of the next conversion sequence in the CSL the first ADC command is already downloaded A commutation event is used by the PMF to generate an async_reload event The async_reload is used b...

Page 63: ... control cycle defined by reload frequency and is relative to start of the control cycle The only settings modified from one control cycle to the next one are the PWM duty cycle registers The main control cycle synchronization event is the PMF reload event The PMF reload event can be generated every n PWM periods This mode can optionally be extended by a timer channel trigger to PMF to change the ...

Page 64: ... application dependent and may range from a further reload attempt to a total shut down PTU trigger generator reload error PTU trigger generator error Since all timing is static this error should only occur during application debugging This type of error occurring in a static timing configuration indicates possible data corruption This can be serviced by a control loop shutdown PTU memory access e...

Page 65: ...able the operation first the GDU fault and then PWM fault must be cleared to automatically re enable the FET driving at the next PWM boundary PTU reload overrun error This is an application run time error caused by the CPU not setting PTULDOK on time Servicing this type of error is application dependent and may range from a further reload attempt to a total shut down PTU trigger generator reload e...

Page 66: ...b_ldok state 4 fetch first trigger time from updated TGxList 5 passes the async_reload event immediately to the ADC if the PTU is enabled 6 generates the reload event for the ADC the ADC actions are 1 the conversion in progress is completed 2 the ADC conversion sequence is aborted and the SEQA flag is set to indicate that the final conversion occurred during the abortion process potentially coinci...

Page 67: ...configured earlier but the GDU output is always enabled last The recommended startup sequence is summarized as follows Configure TIM and PMF to establish the link between TIM OC0 commutation event and PMF Configure PTU to establish the PMF to PTU link and ensure correct sampling within PMF cycle Configure the ADC Configure the GDU 1 13 3 9 Control Loop Shutdown Guidelines 1 Remove energy stored in...

Page 68: ... motor control applications TIM OC0 is used internally to indicate commutation events To switch off OC0 visibility at port pin PT0 Disable output compare signal on pin PT0 in TIM OCPD OCPD0 0b1 1 13 3 12 Debug Signal Visibility Depending on required visibility of internal signals on port pins enable the following registers Set PWMPRR 0b1 in PIM if monitoring of internal PWM waveforms is needed PWM...

Page 69: ...rent torque control loop The inner loop controls DC voltage applied onto the motor winding The control loop is calculated regularly within a given period In most cases this period matches the PWM reload period Driving the DC motor from a DC voltage source the motor can work in all four quadrants The complementary mode of operation with deadtime insertion is needed for smooth reversal of the motor ...

Page 70: ...tching losses The BDCM control loop goal is to provide a controlled DC voltage to the motor winding whereby it is controlled cycle by cycle using a speed current or torque feedback loop The center aligned PWM waveforms generated by the PMF module are applied to the bridge as shown in Figure 1 11 whereby the base waveform for PWM0 and PWM1 is depicted at the top and the complementary PWM0 and PWM1 ...

Page 71: ...d voltage at node B Figure 1 9 Thus the PWM0 duty cycle must exceed the PWM2 duty cycle The PWM duty cycle of PWM0 defines the voltage at the first power stage branch The PWM duty cycle of PWM2 defines the voltage at the second power stage branch Modulating the PWM duty cycle every period using the function FPWM then the duty cycle is expressed as PWM0 duty cycle 0 5 0 5 FPWM For 1 FPWM 1 PWM2 dut...

Page 72: ...r to input pins PT3 1 2 Set T0IC1RR 1 in the register MODRR2 to establish the link from Hall sensor input pins to TIM input capture channel 1 3 Setup TIM IC1 for speed measurement of XORed Hall sensor signals Enable interrupt on both edges 4 Enable TIM OC0 and select toggle action on output compare event TCTL2 OM0 OL0 01 5 Configure PMF for edge aligned PWM mode with or without restart at commutat...

Page 73: ...13 5 2 Sensorless Commutation Figure 1 13 Sensorless BLDC Configuration To calculate the commutation time in a sensorless motor system the back EMF zero crossing event of the currently non fed phase within an electrical rotation cycle must be determined For fast motor rotation the ADC is used to measure the back EMF voltage and the DC bus voltage to determine the zero crossing time For slow motor ...

Page 74: ...phases simultaneously with sinusoidal waveforms Both sensorless and Sine Cosine position sensor control loop operation are supported 1 13 6 1 PMSM Sensorless Operation In this configuration the PMSM stator winding currents are driven sinusoidally and the back EMF waveform is also sinusoidal Thus all 3 phases are active simultaneously The rotor position and speed are determined by the current and c...

Page 75: ...termined by a sine cosine sensor which generates sinusoidal sine cosine signals indicating the angle of the rotor in relation to sensor windings The sensor is supplied by the EVDD1 pin 1 Configure PMF for complementary mode operation 2 Configure PMF for center aligned or phase shifted operation 3 Select correct PMF deadtime insertion based on external FET switches 4 Enable GDU current sense opamps...

Page 76: ...d motor speed parameter from external source e g SCI 10 Configure PMF period and duty cycle 11 Start motor by applying startup algorithm 12 Sample the sine cosine voltages periodically based on PWM cycle to determine motor position 13 Use FOC algorithm to determine back EMF and motor speed Figure 1 15 PMSM Sine Cosine Control Loop Configuration PMF PTU ADC0 GDU M ADC1 reload glb_ldok reload dc_bus...

Page 77: ...g information of phase currents to determine the point in time to change sign of deadtime compensation value to be added to duty cycles The GDU phase comparator signals are connected internally to the PMF ISx inputs This allows the dead time distortion correction to be applied directly based on the phase status 1 Align rotor to stator field 2 Await phase comparator status change 3 Switch to altern...

Page 78: ...d VDDF The VDDX domain supplies the device I O pins VDDA supplies the ADC and internal bias current generators The VDDA and VDDX pins must be connected at board level they are not connected directly internally ESD protection diodes exist between VDDX and VDDA therefore forcing a common operating range The VDD domain supplies the internal device logic The VDDF domain supplies sections of the intern...

Page 79: ...elow the specified assert level The VDDX LVR monitor is disabled when the VREG is in reduced power mode A low voltage interrupt circuit monitors the VDDA domain The GDU high side drain voltage pin HD is monitored within the GDU and mapped to an interrupt A connection to the ADC is provided for accurate measurement of a scaled HD level 1 13 7 2 FET Predriver GDU Supplies A dedicated low drop regula...

Page 80: ...high side gates are attempted to be turned on This can cause bootstrap charge to decay In order to speed up the high side gate voltage level directly after commutation the software should drive the first PWM cycle with a duty cycle meeting an on time of at least tminpulse for the low side drivers and then switch back to 100 again The recommended procedure is to use the manual correction method PMF...

Page 81: ...amily Reference Manual Rev 1 3 Freescale Semiconductor 81 Figure 1 17 High Side Supply and Charge Pump Concept GCPE VLS_OUT 11V CP VCP VBSx HGx 0V 11V 1000µF Motor Dependent S D 1nF N1 HSx HD HIGH SIDE LOW SIDE VBAT CBS 10nF Diode voltage drop Vdiode GCPCD ...

Page 82: ...Chapter 1 Device Overview MC9S12ZVM Family MC9S12ZVM Family Reference Manual Rev 1 3 82 Freescale Semiconductor ...

Page 83: ...TIM channels 3 PWM channels of PMF 1 SPI and 1 SCI 6 pin port S with pin interrupts and key wakeup function associated with 1 MSCAN 1 SCI and 1 SPI modules 3 pin port P with pin interrupts and key wakeup function associated with IRQ XIRQ interrupt inputs 3 PWM channels of PMF ECLK output 9 pin port AD associated with 9 ADC channels shared among two ADC and two GDU AMP modules inputs can be used as...

Page 84: ...eup KWU on port S P and AD Control register to configure IRQ pin operation Control register to enable ECLK output Routing registers to support signal relocation on external pins and control internal routings SPI0 to alternative pins Various SCI0 LINPHY0 routing options supporting standalone use and conformance testing Optional RXD0 to TIM0 link Optional RXD1 to TIM0 link PWM channels to GDU and or...

Page 85: ...ted by the position in the table from top highest priority to bottom lowest priority Table 2 1 Pin Functions and Priorities Port Pin Name Pin Function Priority 1 I O Description Routing Register Bit Pin Function after Reset BKGD MODC 2 I MODC input during RESET BKGD BKGD I O S12ZBDC communication E PE1 XTAL CPMU OSC signal GPIO PTE 1 I O General purpose PE0 EXTAL CPMU OSC signal PTE 0 I O General ...

Page 86: ...ose with interrupt and wakeup PAD5 AMP1 O GDU AMP1 output AN1_0 I ADC1 analog input PTADL 5 KWADL 5 I O General purpose with interrupt and wakeup PAD4 3 AN0_4 AN0_3 I ADC0 analog input PTADL 4 3 KWADL 4 3 I O General purpose with interrupt and wakeup PAD2 AMPP0 I GDU AMP0 non inverting input AN0_2 I ADC0 analog input PTADL 2 KWADL 2 I O General purpose with interrupt and wakeup PAD1 AMPM0 I GDU AM...

Page 87: ... PTT 2 I O General purpose PT1 PTURE O PTU reload event TXD0 LPDC0 O SCI0 transmit LPTXD0 direct control by LP0DR LP0DR1 S0L0RR2 0 MOSI0 I O SPI0 master out slave in SPI0RR PWM4 O PWM channel 4 PWM54RR PWMPRR IOC0_1 3 I O TIM0 channel 1 T0IC1RR PTT 1 I O General purpose PT0 RXD0 I SCI0 receive S0L0RR2 0 MISO0 I O SPI0 master in slave out SPI0RR PWM3 O PWM channel 3 PWM32RR PWMPRR IOC0_0 I O TIM0 c...

Page 88: ...I DBG external event PTS 3 KWS 3 I O General purpose with interrupt and wakeup PS2 MISO0 I O SPI0 master in slave out SPI0RR RXD1 I SCI1 receive SCI1RR PTS 2 KWS 2 I O General purpose with interrupt and wakeup PS1 PTUT1 O PTU trigger 1 LPTXD0 I LINPHY0 transmit input S0L0RR2 0 TXCAN0 O MSCAN0 transmit TXD1 O SCI1 transmit SCI1RR PTS 1 KWS 1 I O General purpose with interrupt and wakeup PS0 PTUT0 O...

Page 89: ...ECLK O Free running clock PWM0 O PWM channel 0 with over current interrupt high current capable 20 mA PWM10RR PWMPRR PTP 0 KWP 0 EVDD1 I O General purpose with interrupt and wakeup Switchable external power supply output with over current interrupt high current capable 20 mA 1 Signals in parentheses denote alternative module routing pins 2 Function active when RESET asserted 3 Routable input captu...

Page 90: ...served R 0 0 0 0 0 0 0 0 W 0x0208 ECLKCTL R NECLK 0 0 0 0 0 0 0 W 0x0209 IRQCR R IRQE IRQEN 0 0 0 0 0 0 W 0x020A PIMMISC R 0 0 0 0 0 0 OCPE1 0 W 0x020B 0x020D Reserved R 0 0 0 0 0 0 0 0 W 0x020E Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x020F Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x0210 0x025F Reserved R 0 0...

Page 91: ... R PTADL7 PTADL6 PTADL5 PTADL4 PTADL3 PTADL2 PTADL1 PTADL0 W 0x0282 PTIADH R 0 0 0 0 0 0 0 PTIADH0 W 0x0283 PTIADL R PTIADL7 PTIADL6 PTIADL5 PTIADL4 PTIADL3 PTIADL2 PTIADL1 PTIADL0 W 0x0284 DDRADH R 0 0 0 0 0 0 0 DDRADH0 W 0x0285 DDRADL R DDRADL7 DDRADL6 DDRADL5 DDRADL4 DDRADL3 DDRADL2 DDRADL1 DDRADL0 W 0x0286 PERADH R 0 0 0 0 0 0 0 PERADH0 W 0x0287 PERADL R PERADL7 PERADL6 PERADL5 PERADL4 PERADL3...

Page 92: ... PIFADL2 PIFADL1 PIFADL0 W 0x0290 0x0297 Reserved R 0 0 0 0 0 0 0 0 W 0x0298 DIENADH R 0 0 0 0 0 0 0 DIENADH0 W 0x0299 DIENADL R DIENADL7 DIENADL6 DIENADL5 DIENADL4 DIENADL3 DIENADL2 DIENADL1 DIENADL0 W 0x029A 0x02BF Reserved R 0 0 0 0 0 0 0 0 W 0x02C0 PTT R 0 0 0 0 PTT3 PTT2 PTT1 PTT0 W 0x02C1 PTIT R 0 0 0 0 PTIT3 PTIT2 PTIT1 PTIT0 W 0x02C2 DDRT R 0 0 0 0 DDRT3 DDRT2 DDRT1 DDRT0 W 0x02C3 PERT R 0...

Page 93: ...2 PPSS1 PPSS0 W 0x02D5 Reserved R 0 0 0 0 0 0 0 0 W 0x02D6 PIES R 0 0 PIES5 PIES4 PIES3 PIES2 PIES1 PIES0 W 0x02D7 PIFS R 0 0 PIFS5 PIFS4 PIFS3 PIFS2 PIFS1 PIFS0 W 0x02D8 0x02DE Reserved R 0 0 0 0 0 0 0 0 W 0x02DF WOMS R 0 0 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 W 0x02E0 0x02EF Reserved R 0 0 0 0 0 0 0 0 W 0x02F0 PTP R 0 0 0 0 0 PTP2 PTP1 PTP0 W 0x02F1 PTIP R 0 0 0 0 0 PTIP2 PTIP1 PTIP0 W 0x02F2 DDR...

Page 94: ...ocks Register bits can be written at any time if not stated differently 2 3 2 1 Module Routing Register 0 MODRR0 0x02F5 Reserved R 0 0 0 0 0 0 0 0 W 0x02F6 PIEP R OCIE1 0 0 0 0 PIEP2 PIEP1 PIEP0 W 0x02F7 PIFP R OCIF1 0 0 0 0 PIFP2 PIFP1 PIFP0 W 0x02F8 0x02FC Reserved R 0 0 0 0 0 0 0 0 W 0x02FD RDRP R 0 0 0 0 0 0 0 RDRP0 W 0x02FE 0x02FF Reserved R 0 0 0 0 0 0 0 0 W Address 0x0200 Access User read w...

Page 95: ...S5 3 SCI1RR Module Routing Register SCI1 routing 1 TXD1 on PS3 RXD1 on PS2 0 TXD1 on PS1 RXD1 on PS0 2 0 S0L0RR2 0 Module Routing Register SCI0 LINPHY0 routing Selection of SCI0 LINPHY0 interface routing options to support probing and conformance testing Refer to Figure 2 2 for an illustration and Table 2 3 for preferred settings SCI0 must be enabled for TXD0 routing to take effect on pins LINPHY0...

Page 96: ... associated functions and maintains TXD0 and RXD0 signals on PT1 and PT0 respectively if no other function with higher priority takes precedence S0L0RR 2 0 Signal Routing Description 000 Default setting SCI0 connects to LINPHY0 interface internal only 001 Direct control setting LP0DR LPDR1 register bit controls LPTXD0 interface internal only 100 Probe setting SCI0 connects to LINPHY0 interface acc...

Page 97: ...pins 2 PWM54RR Module Routing Register PWM4 and PWM5 routing The PWM channel pair can be configured for internal use with the GDU or with its related external pins only If set the signal routing to the pins is established and the related GDU inputs are forced low 1 PWM4 to PT1 PWM5 to PT2 0 PWM4 to GDU PWM5 to GDU 1 PWM32RR Module Routing Register PWM2 and PWM3 routing The PWM channel pair can be ...

Page 98: ...ting One out of four different sources can be selected as input to timer channel 3 11 TIM0 input capture channel 3 is connected to ACLK 10 TIM0 input capture channel 3 is connected to RXD1 01 TIM0 input capture channel 3 is connected to RXD0 00 TIM0 input capture channel 3 is connected to PT3 1 T0IC1RR Module Routing Register TIM0 IC1 routing Timer input capture channel 1 can be used to determine ...

Page 99: ...5 ECLK Control Register ECLKCTL Table 2 6 ECLKCTL Register Field Descriptions Field Description 7 NECLK No ECLK Disable ECLK output This bit controls the availability of a free running clock on the ECLK pin This clock has a fixed rate equivalent to the internal bus clock 1 ECLK disabled 0 ECLK enabled Address 0x0209 Access User read write 1 1 Read Anytime Write IRQE Once in normal mode anytime in ...

Page 100: ...nable 1 IRQ pin is connected to interrupt logic 0 IRQ pin is disconnected from interrupt logic Address 0x020A Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 OCPE1 0 W Reset 0 0 0 0 0 0 0 0 Figure 2 7 PIM Miscellaneous Register PIMMISC Table 2 8 PIM Miscellaneous Register Field Descriptions Field Description 1 OCPE1 Over Current Protection Enable Activate over c...

Page 101: ...active while the port is used as a push pull output General purpose data output availability depends on prioritization input data registers always reflect the pin status independent of the use Pull device availability pull device polarity wired or mode key wake up functionality are independent of the prioritization unless noted differently For availability of individual bits refer to Section 2 3 1...

Page 102: ...a direction value Write Anytime 7 6 5 4 3 2 1 0 R PTx7 PTx6 PTx5 PTx4 PTx3 PTx2 PTx1 PTx0 W Reset 0 0 0 0 0 0 0 0 Figure 2 10 Port Data Register Table 2 9 Port Data Register Field Descriptions Field Description 7 0 PTx7 0 Port General purpose input output data This register holds the value driven out to the pin if the pin is used as a general purpose output When not used with the alternative funct...

Page 103: ...1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R DDRx7 DDRx6 DDRx5 DDRx4 DDRx3 DDRx2 DDRx1 DDRx0 W Reset 0 0 0 0 0 0 0 0 Figure 2 12 Data Direction Register Table 2 11 Data Direction Register Field Descriptions Field Description 7 0 DDRx7 0 Data Direction Select general purpose data direction This bit determines whether the pin is a general purpose input or output If a peripheral module controls t...

Page 104: ... Anytime 7 6 5 4 3 2 1 0 R PERx7 PERx6 PERx5 PERx4 PERx3 PERx2 PERx1 PERx0 W Reset Ports E 0 0 0 0 0 0 1 1 Ports S 0 0 1 1 1 1 1 1 Others 0 0 0 0 0 0 0 0 Figure 2 13 Pull Device Enable Register Table 2 12 Pull Device Enable Register Field Descriptions Field Description 7 0 PERx7 0 Pull Enable Activate pull device on input pin This bit controls whether a pull device on the associated port input or ...

Page 105: ...14 Polarity Select Register Table 2 13 Polarity Select Register Field Descriptions Field Description 7 0 PPSx7 0 Pull Polarity Select Configure pull device and pin interrupt edge polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin If a port has interrupt functionality this bit also selects the polarity of the active edge If MSCAN is acti...

Page 106: ...e pin is operating in input or output mode when in use with the general purpose or related peripheral function 1 Interrupt is enabled 0 Interrupt is disabled interrupt flag masked Address 0x028E PIFADH 0x028F PIFADL 0x02D7 PIFS Access User read write 1 1 Read Anytime Write Anytime write 1 to clear 7 6 5 4 3 2 1 0 R PIFx7 PIFx6 PIFx5 PIFx4 PIFx3 PIFx2 PIFx1 PIFx0 W Reset 0 0 0 0 0 0 0 0 Figure 2 16...

Page 107: ...DIENx3 DIENx2 DIENx1 DIENx0 W Reset 0 0 0 0 0 0 0 0 Figure 2 17 Digital Input Enable Register Table 2 16 Digital Input Enable Register Field Descriptions Field Description 7 0 DIENx7 0 Digital Input Enable Input buffer control This bit controls the digital input function If set to 1 the input buffers are enabled and the pin can be used with the digital function If a peripheral module is enabled wh...

Page 108: ...particular pin 1 Reduced drive selected approx 1 10 of the full drive strength 0 Full drive strength enabled Address 0x02DF WOMS Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R WOMx7 WOMx6 WOMx5 WOMx4 WOMx3 WOMx2 WOMx1 WOMx0 W Reset 0 0 0 0 0 0 0 0 Figure 2 19 Wired Or Mode Register Table 2 18 Wired Or Mode Register Field Descriptions Field Description 7 0 WOMx7 0 Wired Or ...

Page 109: ...rity Select Register Field Descriptions Field Description 2 1 PPSP See Section 2 3 3 5 Polarity Select Register 0 PPSP Pull Polarity Select Configure pull device and pin interrupt edge polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin This bit also selects the polarity of the active interrupt edge This bit selects if a high or a low le...

Page 110: ... 0 PP0 over current interrupt disabled interrupt flag masked 2 0 PIEP2 0 See Section 2 3 3 6 Port Interrupt Enable Register Address 0x02F7 PIFP Access User read write 1 1 Read Anytime Write Anytime write 1 to clear 7 6 5 4 3 2 1 0 R OCIF1 0 0 0 0 PIFP2 PIFP1 PIFP0 W Reset 0 0 0 0 0 0 0 0 Figure 2 23 Port P Interrupt Flag Register Table 2 21 Port P Interrupt Flag Register Field Descriptions Field D...

Page 111: ...pt Flag Register Digital Input Enable Register Reduced Drive Register Wired Or Mode Register Port PT PTI DDR PER PPS PIE PIF DIE RDR WOM E 1 0 1 0 1 0 1 0 1 0 ADH 0 0 0 0 0 0 0 0 ADL 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 T 3 0 3 0 3 0 3 0 3 0 S 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 P 2 0 2 0 2 0 2 0 2 0 2 0 2 0 0 Table 2 23 Effect of Enabled Features Enabled Feature 1 Related Signal s Effect on I O state Effe...

Page 112: ...nabled peripheral function shared on the same pin Table 2 23 If more than one peripheral function is available and enabled at the same time the highest ranked module according the predefined priority scheme in Table 2 1 will take precedence on the pin ADCx ANx_y None2 4 None3 VRH VRL AMPx AMPx AMPPx AMPMx None2 4 None3 IRQ IRQ Forced input None3 XIRQ XIRQ Forced input None3 LINPHY0 LPTXD0 Forced i...

Page 113: ...enables them The IRQ pin allows requesting asynchronous interrupts The interrupt input is disabled out of reset To enable the interrupt the IRQCR IRQEN bit must be set and the I bit cleared in the condition code register The interrupt can be configured for level sensitive or falling edge sensitive triggering If IRQCR IRQEN is cleared while an interrupt is pending the request will deassert Table 2 ...

Page 114: ... detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level Else the sampling logic is restarted In run and wait mode the filters are continuously clocked by the bus clock Pulses with a duration of tPULSE nP_MASK fbus are assuredly filtered out while pulses with a duration of tPULSE nP_PASS fbus guarantee a pin interrupt In stop mode the filter cl...

Page 115: ...put mode as a switchable external power supply pin EVDD1 for external devices like Hall sensors EVDD1 is supplied by the digital pad supply VDDX An over current monitor is implemented to protect the controller from short circuits or excess currents on the output which can only arise if the pin is configured for full drive Although the full drive current is available on the high and low side the pr...

Page 116: ...Chapter 2 Port Integration Module S12ZVMPIMV1 MC9S12ZVM Family Reference Manual Rev 1 3 116 Freescale Semiconductor ...

Page 117: ...RAM for ADCs and the PTU module The S12ZMMC determines the address mapping of the on chip resources regulates access priorities and enforces memory protection Figure 3 1 shows a block diagram of the S12ZMMC module Revision Number Revision Date Sections Affected Description of Changes V01 03 27 Jul 2012 Corrected Table 3 9 V01 04 27 Jul 2012 Added feature tags V01 05 6 Aug 2012 Fixed wording V01 06...

Page 118: ...us accesses to different on chip resources NVM RAM and peripherals Access violation detection and logging Triggers S12ZCPU machine exceptions upon detection of illegal memory accesses and uncorrectable ECC errors Logs the state of the S12ZCPU and the cause of the access error Table 3 2 Glossary Of Terms Term Definition MCU Microcontroller Unit CPU S12Z Central Processing Unit BDC S12Z Background D...

Page 119: ...re is no bus activity in stop mode 3 1 5 Block Diagram e Figure 3 1 S12ZMMC Block Diagram 3 2 External Signal Description The S12ZMMC uses two external pins to determine the devices operating mode RESET and MODC Table 3 3 See device overview for the mapping of these signals to device pins Table 3 3 External System Pins Associated With S12ZMMC Pin Name Description RESET External reset signal The RE...

Page 120: ...tion consists of the S12ZMMC control and status register descriptions in address order Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x0070 MODE R MODC 0 0 0 0 0 0 0 W 0x0071 0x007F Reserved R 0 0 0 0 0 0 0 0 W 0x0080 MMCECH R ITR 3 0 TGT 3 0 W 0x0081 MMCECL R ACC 3 0 ERR 3 0 W 0x0082 MMCCCRH R CPUU 0 0 0 0 0 0 0 W 0x0083 MMCCCRL R 0 CPUX 0 CPUI 0 0 0 0 W 0x0084 Reserved R 0 0 0 0 0 0 0 0 W 0x0085 MMCPCH R...

Page 121: ...et MODC1 0 0 0 0 0 0 0 1 External signal see Table 3 3 Unimplemented or Reserved Figure 3 3 Mode Register MODE Table 3 4 MODE Field Descriptions Field Description 7 MODC Mode Select Bit This bit determines the current operating mode of the MCU Its reset value is captured from the MODC pin at the rising edge of the RESET pin Figure 3 4 illustrates the only valid mode transition from special single ...

Page 122: ...s 0x0081 MMCECL 7 6 5 4 3 2 1 0 R ACC 3 0 ERR 3 0 W Reset 0 0 0 0 0 0 0 0 Field Description 7 4 MMCECH ITR 3 0 Initiator Field The ITR 3 0 bits capture the initiator which caused the access violation The initiator is captured in form of a 4 bit value which is assigned as follows 0 none no error condition detected 1 S12ZCPU 2 reserved 3 ADC0 4 ADC1 5 PTU 6 15 reserved 3 0 MMCECH TGT 3 0 Target Fiel...

Page 123: ...e 3 6 Captured S12ZCPU Condition Code Register MMCCCRH MMCCCRL Read Anytime Write Never 7 4 MMCECL ACC 3 0 Access Type Field The ACC 3 0 bits capture the type of memory access which caused the access violation The access type is captured in form of a 4 bit value which is assigned as follows 0 none no error condition detected 1 opcode fetch 2 vector fetch 3 data load 4 data store 5 15 reserved 3 0 ...

Page 124: ... Interrupt Mask This bit shows the state of the X interrupt mask in the S12ZCPU s CCR at the time the access violation has occurred The S12ZCPU X interrupt mask is read only it will be automatically updated when the next error condition is flagged through the MMCEC register This bit is undefined if the error code registers MMCECn are cleared 4 MMCCCRL CPUI S12ZCPU I Interrupt Mask This bit shows t...

Page 125: ...p resources into an 16MB address space the global memory map The exact resource mapping is shown in Figure 3 8 The global address space is used by the S12ZCPU ADCs PTU and the S12ZBDC module Field Description 7 0 MMCPCH 7 0 MMCPCM 7 0 MMCPCL CPUPC 23 0 S12ZCPU Program Counter Value The CPUPC 23 0 stores the CPU s program counter value at the time the access violation occurred CPUPC 23 0 always poi...

Page 126: ...Memory Map 0x00_1000 0x00_0000 0x10_0000 0x1F_4000 0x80_0000 0xFF_FFFF RAM EEPROM Unmapped Program NVM Register Space 4 KB max 1 MByte 4 KB max 1 MByte 48 KB max 8 MByte 6 MByte High address aligned Low address aligned 0x1F_8000 Unmapped address range 0x1F_C000 Reserved read only 6 KBKB NVM IFR 256 Byte Reserved 512 Byte 0x20_0000 ...

Page 127: ...k ok Code execution ok EEPROM Read access ok 1 1 Unsupported NVM accesses during NVM command execution collisions are treated as illegal accesses ok1 ok1 Write access illegal access illegal access illegal access Code execution ok1 Reserved Space Read access ok ok illegal access Write access only permitted in SS mode ok illegal access Code execution illegal access Reserved Read only Space Read acce...

Page 128: ...t not be executed in the program flow To avoid these machine exceptions S12ZCPU instructions must not be executed from the last high addresses 8 bytes of RAM EEPROM and Flash 3 4 3 Uncorrectable ECC Faults RAM and flash use error correction codes ECC to detect and correct memory corruption Each uncorrectable memory corruption which is detected during a S12ZCPU ADC or PTU access triggers a machine ...

Page 129: ...placed mentions of CCR old name from S12X with CCW new name V00 05 12 Jan 2011 all Corrected wrong IRQ vector address in some descriptions V00 06 22 Mar 2011 all Added vectors for RAM ECC and NVM ECC machine exceptions And moved position to 1E0 1E8 Moved XGATE error interrupt to vector 1DC Remaining vectors accordingly Removed illegal address reset as a potential reset source V00 07 15 Apr 2011 al...

Page 130: ...tor at address vector base1 0x0001F8 One non maskable unimplemented page2 op code trap TRAP vector at address vector base1 0x0001F4 One non maskable software interrupt request SWI vector at address vector base1 0x0001F0 One non maskable system call interrupt request SYS vector at address vector base1 0x00001EC One non maskable machine exception vector request at address vector base1 0x0001E8 One s...

Page 131: ...y levels Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or whenever XIRQ is asserted even if X interrupt is masked 4 1 3 Modes of Operation Run mode This is the basic mode of operation Wait mode In wait mode the INT module is capable of waking up the CPU if an eligible CPU exception occurs Please refer to Section 4 5 3 Wake Up from Stop or Wait Mode for det...

Page 132: ... Access 0x000010 0x000011 Interrupt Vector Base Register IVBR R W 0x000012 0x000016 RESERVED 0x000017 Interrupt Request Configuration Address Register INT_CFADDR R W 0x000018 Interrupt Request Configuration Data Register 0 INT_CFDATA0 R W Wake Up Current IVBR One Set Per Channel Interrupt Requests Interrupt Requests CPU Vector Address New IPL IPL Up to 117 Channels PRIOLVLnPriority Level configura...

Page 133: ...T_CFDATA4 R W 0x00001D Interrupt Request Configuration Data Register 5 INT_CFDATA5 R W 0x00001E Interrupt Request Configuration Data Register 6 INT_CFDATA6 R W 0x00001F Interrupt Request Configuration Data Register 7 INT_CFDATA7 R W Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x000010 IVBR R IVB_ADDR 15 8 W 0x000011 R IVB_ADDR 7 1 0 W 0x000017 INT_CFADDR R 0 INT_CFADDR 6 3 0 0 0 W 0x000018 INT_C...

Page 134: ... 4 4 IVBR Field Descriptions Field Description 15 1 IVB_ADDR 15 1 Interrupt Vector Base Address Bits These bits represent the upper 15 bits of all vector addresses Out of reset these bits are set to 0xFFFE i e vectors are located at 0xFFFE00 0xFFFFFF Note A system reset will initialize the interrupt vector base register with 0xFFFE before it is used to determine the reset vector address Therefore ...

Page 135: ...etermine which of the 128 configuration data registers are accessible in the 8 register window at INT_CFDATA0 7 The hexadecimal value written to this register corresponds to the upper 4 bits of the vector number multiply with 4 to get the vector address offset If for example the value 0x70 is written to this register the configuration data register block for the 8 interrupt vector requests startin...

Page 136: ...the notes following the PRIOLVL 2 0 description below Unimplemented or Reserved Figure 4 8 Interrupt Request Configuration Data Register 3 INT_CFDATA3 Address 0x00001C 7 6 5 4 3 2 1 0 R 0 0 0 0 0 PRIOLVL 2 0 W Reset 0 0 0 0 0 0 0 1 1 1 Please refer to the notes following the PRIOLVL 2 0 description below Unimplemented or Reserved Figure 4 9 Interrupt Request Configuration Data Register 4 INT_CFDAT...

Page 137: ...ut of reset all interrupt requests are enabled at the lowest active level 1 Please also refer to Table 4 7 for available interrupt request priority levels Note Write accesses to configuration data registers of unused interrupt channels are ignored and read accesses return all 0s For information about what interrupt channels are used in a specific MCU please refer to the Device Reference Manual for...

Page 138: ...quests and the spurious interrupt vector request at vector base 0x0001DC which cannot be disabled are always handled by the CPU and have a fixed priority levels A priority level of 0 effectively disables the associated I bit maskable interrupt request If more than one interrupt request is configured to the same interrupt priority level the interrupt request with the higher vector address wins the ...

Page 139: ... the relative priority for all interrupt requests pending for the CPU A CPU interrupt vector is not supplied until the CPU requests it Therefore it is possible that a higher priority interrupt request could override the original exception which caused the CPU to request the vector In this case the CPU will receive the highest priority vector and the system will process this exception first instead...

Page 140: ... Table Entry 4 5 Initialization Application Information 4 5 1 Initialization After system reset software should Initialize the interrupt vector base register if the interrupt vector table is not located at the default location 0xFFFE00 0xFFFFFB Table 4 8 Exception Vector Map and Priority Vector Address 1 1 24 bits vector address based Source 0xFFFFFC Pin reset power on reset low voltage reset cloc...

Page 141: ...seven nested I bit maskable interrupt requests at a time refer to Figure 4 14 for an example using up to three nested interrupt requests I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per default In order to make an interrupt service routine ISR interruptible the ISR must explicitly clear the I bit in the CCW CLI After clearing the I bit I bit ma...

Page 142: ...to the current IPL in CCW The X bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime even if the X bit in CCW is set1 If the X bit maskable interrupt request is used to wake up the MCU with the X bit in the CCW set the associated ISR is not called The CPU then resumes program execution with the instruction following the WAI or STOP instruction This feature works fol...

Page 143: ...roved NORESP description and added STEP1 Wait mode dependency V2 06 22 Mar 2013 Section 5 3 2 2 Improved NORESP description of STEP1 Wait mode dependency V2 07 11 Apr 2013 Section 5 1 3 3 1 Improved STOP and BACKGROUND interdepency description V2 08 31 May 2013 Section 5 4 4 4 Section 5 4 7 1 Removed misleading WAIT and BACKGROUND interdepency description Added subsection dedicated to Long ACK V2 ...

Page 144: ... BDC Modes The BDC features module specific modes namely disabled enabled and active These modes are dependent on the device security and operating mode In active BDM the CPU ceases execution to allow BDC system access to all internal resources including CPU internal registers 5 1 3 2 Security and Operating mode Dependency In device run mode the BDC dependency is as follows Normal modes unsecure d...

Page 145: ...cles If no other module delays stop mode entry and exit then these additional clock cycles represent a difference between the debug and not debug cases Furthermore if a BDC internal access is being executed when the device is entering stop mode then the stop mode entry is delayed until the internal access is complete typically for 1 bus clock cycle Accesses to the internal memory map are not possi...

Page 146: ...s classified as Non Intrusive or Always Available are possible in wait mode On entering wait mode the WAIT flag in BDCCSR is set If the ACK handshake protocol is enabled then the first ACK generated after WAIT has been set is a long ACK pulse Thus the host can recognize a wait mode occurrence The WAIT flag remains set and cannot be cleared whilst the device remains in wait mode After the device le...

Page 147: ... to external capacitance plays almost no role in signal rise time The custom protocol provides for brief actively driven speed up pulses to force rapid rise times on this pin without risking harmful drive level conflicts Refer to Section 5 4 6 for more details 5 3 Memory Map and Register Definition 5 3 1 Module Memory Map Table 5 4 shows the BDC memory map Table 5 4 BDC Memory Map Global Address M...

Page 148: ...DCCSR commands Bit 5 can only be written by WRITE_BDCCSR commands when the device is not in stop mode Bits 6 1 and 0 cannot be written They can only be updated by internal hardware Global Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 Not Applicable BDCCSRH R ENBDC BDMACT BDCCIS 0 STEAL CLKSW UNSEC ERASE W Not Applicable BDCCSRL R WAIT STOP RAMWF OVRUN NORESP RDINV ILLACC ILLCMD W Unimplemented Res...

Page 149: ...enabled If ACK handshaking is disabled then BDC accesses steal the next bus cycle 0 If ACK is enabled then BDC accesses await a free cycle with a timeout of 512 cycles 1 If ACK is enabled then BDC accesses are carried out in the next bus cycle 2 CLKSW Clock Switch The CLKSW bit controls the BDCSI clock source This bit is initialized to 0 by each reset and can be written to 1 Once it has been set i...

Page 150: ...set forcing subsequent ACK pulses to be long Unimplemented BDC opcodes causing the ILLCMD bit to be set do not generate a long ACK because this could conflict with further transmission from the host If the ILLCMD is set for another reason then a long ACK is generated for the current command if it is a BDC command with ACK Register Address This register is not in the device memory map It is accessi...

Page 151: ...f a BACKGROUND command is issued whilst the device is in wait mode the NORESP bit is set but the command is not aborted The active BDM request is completed when the device leaves wait mode Furthermore subsequent CPU register access commands during wait mode set the NORESP bit should it have been cleared e If a command is issued whilst awaiting return from Wait mode This can happen when using STEP1...

Page 152: ...or receiving the first command 10 core clock cycles after the deassertion of the internal reset signal This is delayed relative to the external pin reset as specified in the device reset documentation On S12Z devices an NVM initialization phase follows reset During this phase the BDC commands classified as always available are carried out immediately whereas other BDC commands are subject to delay...

Page 153: ...internal clock is named BDCSI clock If BDCSI clock is mapped to the BDCCLK by CLKSW then the serial interface communication is not affected by bus core clock frequency changes If the BDC is mapped to BDCFCLK then the clock is connected to a PLL derived source at device level typically bus clock thus can be subject to frequency changes in application Debugging through frequency changes requires SYN...

Page 154: ...uch accesses occur infrequently For data read commands the external host must wait at least 16 BDCSI clock cycles after sending the address before attempting to obtain the read data This is to be certain that valid data is available in the BDC shift register ready to be shifted out For write commands the external host must wait 16 bdcsi cycles after sending the data to be written before attempting...

Page 155: ...its of read data in the target to host direction rd16 16 bits of read data in the target to host direction rd24 24 bits of read data in the target to host direction rd32 32 bits of read data in the target to host direction rd64 64 bits of read data in the target to host direction rd sz read data size defined by sz in the target to host direction wd8 8 bits of write data in the host to target direc...

Page 156: ...ubsequent FILL_MEM commands write sequential operands FILL_MEM sz_WS Non Intrusive No 0x13 4 x sz wd sz d ss Fill write memory based on operand size sz and report status Used with WRITE_MEM _WS to fill large blocks of memory An initial WRITE_MEM _WS is executed to set up the starting address of the block and to write the first operand Subsequent FILL_MEM _WS commands write sequential operands GO A...

Page 157: ...ds return content of same address READ_SAME sz_WS Non Intrusive No 0x51 4 x sz d ss rd sz Read from location An initial READ_MEM defines the address subsequent READ_SAME reads return content of same address READ_BDCCSR Always Available No 0x2D rd16 Read the BDCCSR register SYNC_PC Non Intrusive Yes 0x01 dack rd24 Read current PC WRITE_MEM sz Non Intrusive Yes 0x10 4 x sz ad24 wd sz dack Write the ...

Page 158: ... speed error If the SYNC request is detected by the target any partially executed command is discarded This is referred to as a soft reset equivalent to a timeout in the serial communication After the SYNC response the target interprets the next negative edge issued by the host as the start of a new BDC command or the start of new SYNC request A SYNC command can also be used to abort a pending ACK...

Page 159: ...allow the target MCU to finish its current CPU instruction and enter active background mode before a new BDC command can be accepted The host debugger must set ENBDC before attempting to send the BACKGROUND command the first time Normally the host sets ENBDC once at the beginning of a debug session or after a target system reset During debugging the host uses GO commands to move from active BDM to...

Page 160: ...ed before the read data This status byte reflects the state after the memory read was performed If enabled an ACK pulse is driven before the data bytes are transmitted The effect of the access size and alignment on the next address to be accessed is explained in more detail in Section 5 4 5 2 host target D A C K target host 0x36 Data 15 8 Data 7 0 host target D A C K target host target host 0x3A D...

Page 161: ...tered The examples show the DUMP_MEM B _WS DUMP_MEM W _WS and DUMP_MEM L _WS commands 5 4 4 6 FILL_MEM sz FILL_MEM sz_WS FILL_MEM sz Write memory specified by debug address register then increment address Non intrusive 0x12 Data 7 0 host target host target D A C K 0x16 Data 15 8 Data 7 0 host target host target host target D A C K 0x1A Data 31 24 Data 23 16 Data 15 8 Data 7 0 host target host targ...

Page 162: ... address to be accessed is explained in more detail in Section 5 4 5 2 NOTE FILL_MEM _WS is a valid command only when preceded by SYNC NOP WRITE_MEM _WS or another FILL_MEM _WS command Otherwise an illegal command response is returned setting the ILLCMD bit NOP can be used for inter command padding without corrupting the address pointer The size field sz is examined each time a FILL_MEM _WS comman...

Page 163: ... If a GO_UNTIL is not acknowledged then a SYNC command must be issued to end the pending GO_UNTIL If a GO_UNTIL command is issued whilst BDM is inactive an illegal command response is returned and the ILLCMD bit is set If ACK handshaking is disabled the GO_UNTIL command is identical to the GO command 5 4 4 9 NOP NOP performs no operation and may be used as a null command where required 5 4 4 10 RE...

Page 164: ...n Section 5 4 5 2 If the with status option is specified the BDCCSR status byte is returned before the read data This status byte reflects the state READ_MEM sz Read memory at the specified address Non intrusive 0x30 Address 23 0 Data 7 0 host target host target D A C K target host 0x34 Address 23 0 Data 15 8 Data 7 0 host target host target D A C K target host target host 0x38 Address 23 0 Data 3...

Page 165: ...ing the second 32 bit longword since this requires separate internal accesses The first 32 bit longword corresponds to trace buffer line bits 31 0 the second to trace buffer line bits 63 32 If ACK handshaking is disabled the host must wait 16 clock cycles DLY after completing the first 32 bit read before starting the second 32 bit read 5 4 4 13 READ_SAME sz READ_SAME sz_WS Read DBG trace buffer No...

Page 166: ...before the data bytes are transmitted The value of 0xEE is returned if a timeout occurs whereby NORESP is set This can occur if the CPU is executing the WAI instruction or the STOP instruction with BDCCIS clear or if a CPU access is delayed by EWAIT If the CPU is executing the STOP instruction and BDCCIS is set then SYNC_PC returns the PC address of the instruction following STOP in the code listi...

Page 167: ...ses to ensure these accesses are on 0 modulo size alignments Byte alignment details are described in Section 5 4 5 2 WRITE_MEM sz Write memory at the specified address Non intrusive 0x10 Address 23 0 Data 7 0 host target host target host target D A C K 0x14 Address 23 0 Data 15 8 Data 7 0 host target host target host target host target D A C K 0x18 Address 23 0 Data 31 24 Data 23 16 Data 15 8 Data...

Page 168: ...er to the register bit descriptions 5 4 4 19 ERASE_FLASH Mass erase the internal flash This command can always be issued On receiving this command twice in succession the BDC sets the ERASE bit in BDCCSR and requests a flash mass erase Any other BDC command following a single ERASE_FLASH initializes the sequence such that thereafter the ERASE_FLASH must be applied twice in succession to request a ...

Page 169: ...his command executes the next CPU instruction in application code If enabled an ACK is driven If a STEP1 command is issued and the CPU is not halted the command is ignored Using STEP1 to step through a CPU WAI instruction is explained in Section 5 1 3 3 2 5 4 5 BDC Access Of Internal Resources Unsuccessful read accesses of internal resources return a value of 0xEE for each data byte This enables a...

Page 170: ... An illegal access does not break a DUMP_MEM sequence After read accesses that cause the RDINV bit to be set DUMP_MEM and READ_SAME commands are valid it is not necessary to restart the access sequence with a READ_MEM The hardware forces low order address bits to zero for longword accesses to ensure these accesses are realigned to 0 modulo size alignments Word accesses map to 2 bytes from within a...

Page 171: ...n attempted misaligned word access across a 4 byte boundary as shown in row 7 The following word access in row 8 continues from the realigned address of row 7 d Address 1 0 Access Size 00 01 10 11 Note 00 32 bit Data 31 24 Data 23 16 Data 15 8 Data 7 0 01 32 bit Data 31 24 Data 23 16 Data 15 8 Data 7 0 Realigned 10 32 bit Data 31 24 Data 23 16 Data 15 8 Data 7 0 Realigned 11 32 bit Data 31 24 Data...

Page 172: ...KSW bit in the BDCCSR register This clock is referred to as the target clock in the following explanation Table 5 12 Consecutive READ_SAME Accesses With Variable Size Row Command Base Address 00 01 10 11 1 READ_MEM 32 0x004003 Accessed Accessed Accessed Accessed 2 READ_SAME 32 Accessed Accessed Accessed Accessed 3 READ_SAME 16 Accessed Accessed 4 READ_SAME 08 Accessed 5 READ_MEM 08 0x004000 Access...

Page 173: ...n take the target up to one full clock cycle to recognize this edge this synchronization uncertainty is illustrated in Figure 5 6 The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle earlier Synchronization between the host and target is established in this manner ...

Page 174: ...Timing Logic 1 Figure 5 8 shows the host receiving a logic 0 from the target The host initiates the bit time but the target finishes it Since the target wants the host to receive a logic 0 it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge The host samples the bit level about 10 target clock cycles after starting the bit time HOST SAMPLES ...

Page 175: ...CSI clock cycles followed by a brief speedup pulse on the BKGD pin generated by the target MCU when a command issued by the host has been successfully executed see Figure 5 9 This pulse is referred to as the ACK pulse After the ACK pulse has finished the host can start the bit retrieval if the last issued command was a read command or start a new command if the last command was a write command or ...

Page 176: ...is set the BDC gains immediate access if necessary stealing an internal bus cycle NOTE If bus steals are disabled then a loop with no free cycles cannot allow access In this case the host must recognize repeated NORESP messages and then issue a BACKGROUND command to stop the target and access the data Figure 5 10 shows the ACK handshake protocol without steal in a command level timing diagram The ...

Page 177: ...is assumed to be the 16th BDCSI clock cycle of the last bit The 32 cycle minimum delay differs from the 16 cycle delay time with ACK disabled If a BDC access request does not gain access within 512 core clock cycles the request is aborted the NORESP flag is set and a Long ACK pulse is transmitted to indicate an error case Following a STOP or WAI instruction if the BDC is enabled the first ACK foll...

Page 178: ...set is hardware handshake protocol disabled It can also be disabled by the ACK_DISABLE BDC command This provides backwards compatibility with the existing host devices which are not able to execute the hardware handshake protocol For host devices that support the hardware handshake protocol true non intrusive debugging and error flagging is offered If the ACK pulse protocol is disabled the host ne...

Page 179: ...ive BDM The STEP1 command can be issued repeatedly to step through the user code one instruction at a time If an interrupt is pending when a STEP1 command is issued the interrupt stacking operation occurs but no user instruction is executed In this case the stacking counts as one instruction The device re enters active BDM with the program counter pointing to the first instruction in the interrupt...

Page 180: ...e operation is pending completion timeouts are also possible if a BDC command is partially issued or data partially retrieved Thus if a time greater than 512 BDCSI clock cycles is observed between two consecutive negative edges a soft reset occurs causing the partially received command or data retrieved to be discarded The next negative edge at the BKGD pin after a soft reset has occurred is consi...

Page 181: ...story Table Revision Number Revision Date Sections Affected Description Of Changes 2 04 19 APR 2012 Section 6 4 5 2 1 Documented DBGTB read dependency on PROFILE bit 2 05 23 MAY 2012 General Formatting changes to support DBGV3 from single source 2 06 10 SEP 2012 Section 6 4 5 3 Added NOTE about PC trace buffer entries for Comp D timestamps 2 07 18 OCT 2012 General Formatting corrections 2 08 16 NO...

Page 182: ...mparator can be configured to monitor PC addresses or addresses of data accesses Each comparator can select either read or write access cycles Comparator matches can force state sequencer state transitions Three comparator modes Simple address data comparator match mode Inside address range mode Addmin Address Addmax Outside address range match mode Address Addmin or Address Addmax State sequencer...

Page 183: ...clock profiling interface Output of code flow information 6 1 4 Modes of Operation The DBG module can be used in all MCU functional modes The DBG module can issue breakpoint requests to force the device to enter active BDM or an SWI ISR The BDC BACKGROUND command is also handled by the DBG to force the device to enter active BDM When the device enters active BDM through a BACKGROUND command with t...

Page 184: ...they occur at the pin Thus an external event occurring less than 2 bus cycles before arming the DBG module is perceived to occur whilst the DBG is armed When the device is in stop mode the synchronizer clocks are disabled and the external events are ignored 6 2 2 Profiling Output The DBG module features a profiling data output signal PDO The mapping of this signal to a device pin is specified in t...

Page 185: ... C3SC0 C2SC1 C2SC0 C1SC1 C1SC0 C0SC1 C0SC0 W 0x0109 DBGSCR3 R C3SC1 C3SC0 C2SC1 C2SC0 C1SC1 C1SC0 C0SC1 C0SC0 W 0x010A DBGEFR R PTBOVF TRIGF 0 EEVF ME3 ME2 ME1 ME0 W 0x010B DBGSR R TBF 0 0 PTACT 0 SSF2 SSF1 SSF0 W 0x010C 0x010F Reserved R 0 0 0 0 0 0 0 0 W 0x0110 DBGACTL R 0 NDB INST 0 RW RWE reserved COMPE W 0x0111 0x0114 Reserved R 0 0 0 0 0 0 0 0 W 0x0115 DBGAAH R DBGAA 23 16 W 0x0116 DBGAAM R ...

Page 186: ...MPE W 0x0121 0x0124 Reserved R 0 0 0 0 0 0 0 0 W 0x0125 DBGBAH R DBGBA 23 16 W 0x0126 DBGBAM R DBGBA 15 8 W 0x0127 DBGBAL R DBGBA 7 0 W 0x0128 0x012F Reserved R 0 0 0 0 0 0 0 0 W 0x0130 DBGCCTL R 0 NDB INST 0 RW RWE reserved COMPE W 0x0131 0x0134 Reserved R 0 0 0 0 0 0 0 0 W 0x0135 DBGCAH R DBGCA 23 16 W 0x0136 DBGCAM R DBGCA 15 8 W 0x0137 DBGCAL R DBGCA 7 0 W 0x0138 DBGCD0 R Bit 31 30 29 28 27 26...

Page 187: ...t 31 30 29 28 27 26 25 Bit 24 W 0x013D DBGCDM1 R Bit 23 22 21 20 19 18 17 Bit 16 W 0x013E DBGCDM2 R Bit 15 14 13 12 11 10 9 Bit 8 W 0x013F DBGCDM3 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0140 DBGDCTL R 0 0 INST 0 RW RWE reserved COMPE W 0x0141 0x0144 Reserved R 0 0 0 0 0 0 0 0 W 0x0145 DBGDAH R DBGDA 23 16 W 0x0146 DBGDAM R DBGDA 15 8 W 0x0147 DBGDAL R DBGDA 7 0 W 0x0148 0x017F Reserved R 0 0 0 0 0 0 0 0 W ...

Page 188: ...bugger armed 6 TRIG Immediate Trigger Request Bit This bit when written to 1 requests an immediate transition to final state independent of comparator status This bit always reads back a 0 Writing a 0 to this bit has no effect 0 No effect 1 Force state sequencer immediately to final state 4 BDMBP Background Debug Mode Enable This bit determines if a CPU breakpoint causes the system to enter Backgr...

Page 189: ...le 6 6 1 0 ABCM 1 0 A and B Comparator Match Control These bits determine the A and B comparator match mapping as described in Table 6 7 Table 6 6 CDCM Encoding CDCM Description 00 Match2 mapped to comparator C match Match3 mapped to comparator D match 01 Match2 mapped to comparator C D inside range Match3 disabled 10 Match2 mapped to comparator C D outside range Match3 disabled 11 Reserved 1 1 Cu...

Page 190: ...have no effect in other tracing modes To use a comparator for range filtering the corresponding COMPE bit must remain cleared If the COMPE bit is set then the comparator is used to generate events and the TRANGE bits have no effect See Table 6 9 for range boundary definition 3 2 TRCMOD Trace Mode Bits See Section 6 4 5 2 for detailed Trace Mode descriptions In Normal Mode change of flow informatio...

Page 191: ... 6 Debug Trace Control Register Low DBGTCRL Table 6 12 DBGTCRL Field Descriptions Field Description 3 DSTAMP Comparator D Timestamp Enable This bit when set enables Comparator D matches to generate timestamps in Detail Normal and Loop1 trace modes 0 Comparator D match does not generate timestamp 1 Comparator D match generates timestamp if timestamp function is enabled 2 PDOE Profile Data Out Enabl...

Page 192: ...7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W POR X X X X X X X X X X X X X X X X Other Resets Figure 6 7 Debug Trace Buffer Register DBGTB Table 6 13 DBGTB Field Descriptions Field Description 15 0 Bit 15 0 Trace Buffer Data Bits The Trace Buffer Register is a window through which the lines of the trace buffer may be read 16 bits at a time Each valid read of DBGTB increments an internal trace buf...

Page 193: ... Thereafter incrementing of CNT continues if configured for end alignment or mid alignment The DBGCNT register is cleared when ARM in DBGC1 is written to a one The DBGCNT register is cleared by power on reset initialization but is not cleared by other system resets If a reset occurs during a debug session the DBGCNT register still indicates after the reset the number of valid trace buffer entries ...

Page 194: ...t the targeted next state whilst in State1 following a match1 5 4 C2SC 1 0 Channel 2 State Control These bits select the targeted next state whilst in State1 following a match2 7 6 C3SC 1 0 Channel 3 State Control If EEVE 10 these bits select the targeted next state whilst in State1 following a match3 If EEVE 10 these bits select the targeted next state whilst in State1 following an external event...

Page 195: ...its select the targeted next state whilst in State2 following a match3 If EEVE 10 these bits select the targeted next state whilst in State2 following an external event Table 6 19 State2 Match State Sequencer Transitions CxSC 1 0 Function 00 Match has no effect 01 Match forces sequencer to State1 10 Match forces sequencer to State3 11 Match forces sequencer to Final State Address 0x0109 7 6 5 4 3 ...

Page 196: ...nnel 3 State Control If EEVE 10 these bits select the targeted next state whilst in State3 following a match3 If EEVE 10 these bits select the targeted next state whilst in State3 following an external event Table 6 21 State3 Match State Sequencer Transitions CxSC 1 0 Function 00 Match has no effect 01 Match forces sequencer to State1 10 Match forces sequencer to State2 11 Match forces sequencer t...

Page 197: ...ystem generated resets have no affect on this bit 4 PTACT Profiling Transmission Active The PTACT bit when set indicates that the profiling transmission is still active When clear PTACT then profiling transmission is not active The PTACT bit is set when profiling begins with the first PTS format entry to the trace buffer The PTACT bit is cleared when the profiling transmission ends 2 0 SSF 2 0 Sta...

Page 198: ...er value This bit is ignored if the INST bit in the same register is set 0 Match on data bus equivalence to comparator register contents 1 Match on data bus difference to comparator register contents 5 INST Instruction Select This bit configures the comparator to compare PC or data access addresses 0 Comparator compares addresses of data accesses 1 Comparator compares PC address 3 RW Read Write Co...

Page 199: ...GAA 15 8 W Reset 0 0 0 0 0 0 0 0 Address 0x0117 DBGAAL 7 6 5 4 3 2 1 0 R DBGAA 7 0 W Reset 0 0 0 0 0 0 0 0 Figure 6 15 Debug Comparator A Address Register Table 6 27 DBGAAH DBGAAM DBGAAL Field Descriptions Field Description 23 16 DBGAA 23 16 Comparator Address Bits 23 16 These comparator address bits control whether the comparator compares the address bus bits 23 16 to a logic one or logic zero 0 ...

Page 200: ...D0 DBGAD1 Comparator Data Bits These bits control whether the comparator compares the data bus bits to a logic one or logic zero The comparator data bits are only used in comparison if the corresponding data mask bit is logic 1 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one 15 0 Bits 15 0 DBGAD2 DBGAD3 Comparator Data Bits These bits control whethe...

Page 201: ...orresponding data bit Address 0x0120 7 6 5 4 3 2 1 0 R 0 0 INST 0 RW RWE reserved COMPE W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 6 18 Debug Comparator B Control Register Table 6 30 DBGBCTL Field Descriptions Field 1 1 If the ABCM field selects range mode comparisons then DBGACTL bits configure the comparison DBGBCTL is ignored Description 5 INST Instruction Select This bit configur...

Page 202: ... 18 17 16 R DBGBA 23 16 W Reset 0 0 0 0 0 0 0 0 Address 0x0126 DBGBAM 15 14 13 12 11 10 9 8 R DBGBA 15 8 W Reset 0 0 0 0 0 0 0 0 Address 0x0127 DBGBAL 7 6 5 4 3 2 1 0 R DBGBA 7 0 W Reset 0 0 0 0 0 0 0 0 Figure 6 19 Debug Comparator B Address Register Table 6 32 DBGBAH DBGBAM DBGBAL Field Descriptions Field Description 23 16 DBGBA 23 16 Comparator Address Bits 23 16 These comparator address bits co...

Page 203: ...tch on data bus equivalence to comparator register contents 1 Match on data bus difference to comparator register contents 5 INST Instruction Select This bit configures the comparator to compare PC or data access addresses 0 Comparator compares addresses of data accesses 1 Comparator compares PC address 3 RW Read Write Comparator Value Bit The RW bit controls whether read or write is used in compa...

Page 204: ... Address Register Table 6 35 DBGCAH DBGCAM DBGCAL Field Descriptions Field Description 23 16 DBGCA 23 16 Comparator Address Bits 23 16 These comparator address bits control whether the comparator compares the address bus bits 23 16 to a logic one or logic zero 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one 15 0 DBGCA 15 0 Comparator Address B...

Page 205: ...s Field Description 31 16 Bits 31 16 DBGCD0 DBGCD1 Comparator Data Bits These bits control whether the comparator compares the data bus bits to a logic one or logic zero The comparator data bits are only used in comparison if the corresponding data mask bit is logic 1 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one 15 0 Bits 15 0 DBGCD2 DBGCD3 Compa...

Page 206: ... the corresponding comparator data compare bits 0 Do not compare corresponding data bit 1 Compare corresponding data bit Address 0x0140 7 6 5 4 3 2 1 0 R 0 0 INST 0 RW RWE reserved COMPE W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 6 24 Debug Comparator D Control Register Table 6 38 DBGDCTL Field Descriptions Field 1 Description 5 INST Instruction Select This bit configures the compara...

Page 207: ...it RW Bit RW Signal Comment 0 x 0 RW not used in comparison 0 x 1 RW not used in comparison 1 0 0 Write match 1 0 1 No match 1 1 0 No match 1 1 1 Read match Address 0x0145 DBGDAH 23 22 21 20 19 18 17 16 R DBGDA 23 16 W Reset 0 0 0 0 0 0 0 0 Address 0x0146 DBGDAM 15 14 13 12 11 10 9 8 R DBGDA 15 8 W Reset 0 0 0 0 0 0 0 0 Address 0x0147 DBGDAL 7 6 5 4 3 2 1 0 R DBGDA 7 0 W Reset 0 0 0 0 0 0 0 0 Figu...

Page 208: ...hat opcode When a match with a comparator register value occurs the associated control logic can force the state sequencer to another state see Figure 6 26 The state sequencer can transition freely between the states 1 2 and 3 On transition to Final State bus tracing can be triggered On completion of tracing the state sequencer enters State0 If tracing is disabled or End aligned tracing is enabled...

Page 209: ... determined by the TRANGE bits in the DBGTCRH register The TRANGE encoding is shown in Table 6 9 If the TRANGE bits select a range definition using comparator D and the COMPE bit is clear then comparator D is configured for trace range definition By setting the COMPE bit the comparator is configured for address bus comparisons the TRANGE bits are ignored and the tracing range function is disabled ...

Page 210: ...hin that field must be masked using the corresponding data mask registers This ensures that any access of that byte 32 bit 16 bit or 8 bit with matching data causes a match If no bytes are masked then the data comparator always compares all 32 bits and can only generate a match on a 32 bit access with correct 32 bit data value In this case 8 bit or 16 bit accesses within the 32 bit field cannot ge...

Page 211: ...be cleared to ignore bit positions A match occurs when any data bus bit with corresponding mask bit set is different Clearing all mask bits causes all bits to be ignored and prevents a match because no difference can be detected In this case address bus equivalence does not cause a match Bytes that are not accessed are ignored Thus when monitoring a multi byte field for a difference partial access...

Page 212: ...onfigured for range comparisons A single match condition on either of the comparators is recognized as valid Outside range mode in combination with opcode address matches can be used to detect if opcodes are from an unexpected range NOTE When configured for data access matches an outside range match would typically occur at any interrupt vector fetch or register access This can be avoided by setti...

Page 213: ...rs 6 4 3 3 Setting The TRIG Bit Independent of comparator matches it is possible to initiate a tracing session and or breakpoint by writing the TRIG bit in DBGC1 to a logic 1 This forces the state sequencer into the Final State If configured for End aligned tracing or for no tracing the transition to Final State is followed immediately by a transition to State0 If configured for Begin or Mid Align...

Page 214: ...tate On entering Final State a trigger may be issued to the trace buffer according to the trigger position control as defined by the TALIGN field see Section 6 3 2 3 If tracing is enabled and either Begin or Mid aligned triggering is selected the state sequencer remains in Final State until completion of the trace On completion of the trace the state sequencer returns to State0 and the debug modul...

Page 215: ...estricted for example to particular register or RAM range accesses The external event pin can be configured to force trace buffer entries in Normal or Loop1 trace modes All tracing modes support trace buffer gating In Pure PC and Detail modes external events do not force trace buffer entries If the external event pin is configured to gate trace buffer entries then any trace mode is valid 6 4 5 1 T...

Page 216: ...ore a trigger event 6 4 5 1 3 Storing with End Alignment Storing with End Alignment data is stored in the trace buffer until the Final State is entered Following this trigger the DBG module immediately transitions to State0 If the trigger is at the address of a COF instruction the trigger event is not stored in the trace buffer 6 4 5 2 Trace Modes The DBG module can operate in four trace modes The...

Page 217: ...BUFFER ENTRY 3 NOP ADDR1 DBNE D0 PART5 Source address TRACE BUFFER ENTRY 4 IRQ_ISR LD D1 F0 IRQ Vector FFF2 TRACE BUFFER ENTRY 2 ST D1 VAR_C1 RTI The execution flow taking into account the IRQ is as follows LD X SUB_1 MARK1 JMP 0 X IRQ_ISR LD D1 F0 ST D1 VAR_C1 RTI SUB_1 NOP NOP ADDR1 DBNE D0 PART5 The Normal Mode trace buffer format is shown in the following tables Whilst tracing in Normal or Loo...

Page 218: ...ss of the trace buffer entry as described in Table 6 50 3 CTI Comparator Timestamp Indicator This bit indicates if the trace buffer entry corresponds to a comparator timestamp 0 Trace buffer entry initiated by trace mode specification conditions or timestamp counter overflow 1 Trace buffer entry initiated by comparator D match 2 EEVI External Event Indicator This bit indicates if the trace buffer ...

Page 219: ...byte indicates the size of access and the type of access read or write ADRH ADRM ADRL denote address high middle and low byte respectively The numerical suffix indicates which tracing step DBGCNT increments by 2 for each line completed If timestamps are enabled then each CPU entry can span 2 trace buffer lines whereby the second line includes the timestamp If a valid PC occurs in the same cycle as...

Page 220: ...d TSINF1 CPCH1 CPCM1 CPCL1 CDATA32 CDATA22 CDATA12 CDATA02 CINF2 CADRH2 CADRM2 CADRL2 CDATA33 CDATA23 CDATA13 CDATA03 CINF3 CADRH3 CADRM3 CADRL3 Timestamp Timestamp Reserved Reserved TSINF3 CPCH3 CPCM3 CPCL3 Access Address Access Size CDATA31 CDATA21 CDATA11 CDATA01 00 32 bit Byte1 Byte2 Byte3 Byte4 01 32 bit Byte4 Byte1 Byte2 Byte3 10 32 bit Byte3 Byte4 Byte1 Byte2 11 32 bit Byte2 Byte3 Byte4 Byt...

Page 221: ... base address used as a reference for the previous entries on the same line Whilst tracing a base address is typically stored Table 6 54 CINF Field Descriptions Field Description 7 6 CSZ Access Type Indicator This field indicates the CPU access size 00 8 bit Access 0116 bit Access 10 24 bit Access 11 32 bit Access 5 CRW Read Write Indicator Indicates if the corresponding stored address corresponds...

Page 222: ... 6 5 4 3 2 1 0 CPU CXINF BASE BASE BASE PLB3 PLB2 PLB1 PLB0 7 6 5 4 3 2 1 0 CXINF MAT PLEC NB3 NB2 NB1 NB0 Figure 6 29 Pure PC Mode CXINF Table 6 57 CXINF Field Descriptions Field Description MAT Mid Aligned Trigger This bit indicates a mid aligned trigger position When a mid aligned trigger occurs the next trace buffer entry is a base address and the counter is incremented to a new line independe...

Page 223: ...ce buffer is that of the previous instruction The comparator must contain the PC address of the instruction s first opcode byte Timestamps are disabled in Pure PC mode 6 4 5 4 Reading Data from Trace Buffer The data stored in the trace buffer can be read using either the background debug controller BDC module or the CPU provided the DBG module is not armed and is configured for tracing by TSOURCE ...

Page 224: ...et during debugging so that it points to the oldest valid data again Debugging occurrences of system resets is best handled using mid or end trigger alignment since the reset may occur before the trace trigger which in the begin trigger alignment case means no information would be stored in the trace buffer 6 4 6 Code Profiling 6 4 6 1 Code Profiling Overview Code profiling supplies encoded COF in...

Page 225: ...tracing then profiling begins as soon as the module is armed If TALIGN is configured for Begin aligned tracing then profiling begins when the state sequencer enters Final State and continues until a software disarm or trace buffer overflow occurs thus profiling does not terminate after 64 line entries have been made Mid Align tracing is not supported whilst profiling if the TALIGN bits are configu...

Page 226: ...o Vector Address 8 1 After the PTS entry the pointer increments and the DBG begins to fill the next line with direct COF information This continues until the direct COF field is full or an indirect COF occurs then the INFO byte and if needed indirect COF information are entered on that line and the pointer increments to the next line If a timestamp overflow occurs indicating a 65536 bus clock cycl...

Page 227: ...top bit field for each line is shaded In line0 the left most asserted bit is Byte4 7 This indicates that all remaining 31 bits in the 4 byte field contain valid direct COF information whereby each 1 represents branch taken and each 0 represents branch not taken The stop bit of line1 indicates that all 30 bits to it s right are valid after the 30th direct COF entry an indirect COF occurred that is ...

Page 228: ...ition to State0 and associated breakpoints are immediate 6 4 7 2 Breakpoints Generated Via The TRIG Bit When TRIG is written to 1 the Final State is entered If a tracing session is selected by TSOURCE State0 is entered and breakpoints are requested only when the tracing session has completed thus if Begin or Mid aligned triggering is selected the breakpoint is requested only on completion of the s...

Page 229: ...f an active breakpoint or trigger still exists at that address this can re trigger disarming the DBG If configured for BDM breakpoints the user must apply the BDC STEP1 command to increment the PC past the current instruction If configured for SWI breakpoints the DBG can be re configured in the SWI routine If a comparator match occurs at an SWI vector address then a code SWI and DBG breakpoint SWI...

Page 230: ... BDC BACKGROUND commands 6 5 4 Code Profiling The code profiling data output pin PDO is mapped to a device pin that can also be used as GPIO in an application If profiling is required and all pins are required in the application it is recommended to use the device pin for a simple output function in the application without feedback to the chip In this way the application can still be profiled sinc...

Page 231: ...ord The ECC algorithm is able to detect and correct single bit ECC errors Double bit ECC errors will be detected but the system is not able to correct these errors This kind of ECC code is called SECDED code This ECC code requires 6 additional parity bits for each 2 byte data word 7 1 1 Features The SRAM_ECC module provides the ECC logic for the system memory based on a SECDED algorithm The SRAM_E...

Page 232: ...ry Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 ECCSTAT R 0 0 0 0 0 0 0 RDY W 0x0001 ECCIE R 0 0 0 0 0 0 0 SBEEIE W 0x0002 ECCIF R 0 0 0 0 0 0 0 SBEEIF W 0x0003 0x0006 Reserved R 0 0 0 0 0 0 0 0 W 0x0007 ECCDPTRH R DPTR 23 16 W 0x0008 ECCDPTRM R DPTR 15 8 W 0x0009 ECCDPTRL R DPTR 7 1 0 W 0x000A 0x000B Reserved R 0 0 0 0 0 0 0 0 W 0x000C ECCDDH R DDATA 15 8 W 0x000D ECCDDL R DDATA 7 ...

Page 233: ...e 7 3 ECC Interrupt Enable Register ECCIE Table 7 3 ECCIE Field Description Module Base 0x00000 Access User read only 1 1 Read Anytime Write Never 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 RDY W Reset 0 0 0 0 0 0 0 0 Field Description 0 RDY ECC Ready Shows the status of the ECC module 0 Internal SRAM initialization is ongoing access to the SRAM is disabled 1 Internal SRAM initialization is done access to th...

Page 234: ...ription Module Base 0x0002 Access User read write 1 1 Read Anytime Write Anytime write 1 to clear 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 SBEEIF W Reset 0 0 0 0 0 0 0 0 Field Description 0 SBEEIF Single bit ECC Error Interrupt Flag The flag is set to 1 when a single bit ECC error occurs 0 No occurrences of single bit ECC error since the last clearing of the flag 1 Single bit ECC error has occured since th...

Page 235: ...0 Unimplemented Figure 7 5 ECC Debug Pointer Register ECCDPTRH ECCDPTRM ECCDPTRL Table 7 5 ECCDPTR Register Field Descriptions Field Description DPTR 23 0 ECC Debug Pointer This register contains the system memory address which will be used for a debug access Address bits not relevant for SRAM address space are not writeable so the software should read back the pointer value to make sure the regis...

Page 236: ... 0 0 0 0 0 0 Unimplemented Figure 7 6 ECC Debug Data ECCDDH ECCDDL Table 7 6 ECCDD Register Field Descriptions Field Description DDATA 23 0 ECC Debug Raw Data This register contains the raw data which will be written into the system memory during a debug write command or the read data from the debug read command Module Base 0x000E Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1...

Page 237: ...n is enabled 1 Automatic single ECC error repair function is disabled 1 ECCDW ECC Debug Write Command Writing one to this register bit will perform a debug write access to the system memory During this access the debug data word DDATA and the debug ECC value DECC will be written to the system memory address defined by DPTR If the debug write access is done this bit is cleared Writing 0 has no effe...

Page 238: ...cycle then the logic generates the new ECC value based on the corrected read and new write read In the next cycle the new data word and the new ECC value are written into the memory If required both 2 byte data words are updated The SBEEIF bit is set Hence the single bit ECC error was corrected by the write access Figure 7 9 shows an example of a 2 byte non aligned memory write access If the modul...

Page 239: ...at allow a read before a first write like the read modify write operation of the unaligned access require that the memory contains valid ECC values before the first read modify write access is performed The ECC module provides logic to initialize the complete memory content with zero during the power up phase During the initialization process the access to the SRAM is disabled and the RDY status b...

Page 240: ...he single bit ECC error is flagged by the SBEEIF but the data inside the system memory are unchanged By writing wrong ECC values into the system memory the debug access can be used to force single and double bit ECC errors to check the software error handling It is not possible to set the ECCDW or ECCDR bit if the previous debug access is ongoing ECCDW or ECCDR bit active This ensures that the ECC...

Page 241: ...he memory address defined by register DPTR If the ECCDR bit is cleared then the register DDATA contains the uncorrected read data from the memory The register DECC contains the ECC value read from the memory Independent of the ECCDRR register bit setting the debug read access will not perform an automatic ECC repair during read access During the debug read access no ECC check is performed so that ...

Page 242: ...Chapter 7 ECC Generation Module SRAM_ECCV1 MC9S12ZVM Family Reference Manual Rev 1 3 242 Freescale Semiconductor ...

Page 243: ...op PLL provides a highly accurate frequency multiplier with internal filter The Internal Reference Clock IRC1M provides a 1MHz internal clock Rev No Item No Date Submitted By Sections Affected Substantial Change s V06 02 20 Dec 2012 Format and font corrections Table 8 31 CPMUOSC2 Field Descriptions removed Bit6 and Bit4 0 description as these bits no longer exist V06 03 18 June 2013 EXTCON registe...

Page 244: ...er consumption and increased emission The Voltage Regulator VREGAUTO has the following features Input voltage range from 6 to 18V nominal operating range Low voltage detect LVD with low voltage interrupt LVI Power on reset POR Low voltage reset LVR On Chip Temperature Sensor and Bandgap Voltage measurement via internal ADC channel Voltage Regulator providing Full Performance Mode FPM and Reduced P...

Page 245: ...ter to turn off TC trimming after reset Application can trim the TC if required by overwriting the IRCTRIM register Other features of the S12CPMU_UHV_V6 include Oscillator clock monitor to detect loss of crystal Autonomous periodical interrupt API Bus Clock Generator Clock switch to select either PLLCLK or external crystal resonator based Bus Clock PLLCLK divider to adjust system speed System Rese...

Page 246: ... for 50MHz VCOCLK operation Post divider is 0x03 so PLLCLK is VCOCLK divided by 4 that is 12 5MHz and Bus Clock is 6 25MHz The PLL can be re configured for other bus frequencies The reference clock for the PLL REFCLK is based on internal reference clock IRC1M PLL Engaged External PEE The Bus Clock is based on the PLLCLK This mode can be entered from default mode PEI by performing the following ste...

Page 247: ...w Voltage Reset LVR are disabled The API is available The Phase Locked Loop PLL is off The Internal Reference Clock IRC1M is off Core Clock and Bus Clock are stopped Depending on the setting of the PSTP and the OSCE bit Stop Mode can be differentiated between Full Stop Mode PSTP 0 or OSCE 0 and Pseudo Stop Mode PSTP 1 and OSCE 1 In addition the behavior of the COP in each mode will change based on...

Page 248: ...the ACLK for the COP can be stopped COP static or running COP active depending on the setting of bit CSAD When bit CSAD is set the ACLK for the COP is stopped during Pseudo Stop Mode and COP continues to operate after exit from Pseudo Stop Mode For this COP configuration ACLK clock source CSAD set a latency time please refer to CSAD bit description for details occurs when entering or exiting Pseud...

Page 249: ...ous Periodic Interrupt API API Interrupt VSS1 2 PLLSEL VSSX VDDA VDDX Low Voltage Detect LVRF PLLCLK Reference Clock IRC1M OSCCLK Monitor osc monitor fail Real Time Interrupt RTI RTI Interrupt PSTP CPMURTI Oscillator status Interrupt XOSCLCP High Temperature Sense HT Interrupt Low Voltage Interrupt APICLK RTICLK IRCCLK OSCCLK RTIOSCSEL COP time out PRE UPOSC 0 sets PLLSEL bit API_EXTCLK RC Osc UPO...

Page 250: ...y Reference Manual Rev 1 3 250 Freescale Semiconductor Figure 8 2 shows a block diagram of the XOSCLCP Figure 8 2 XOSCLCP Block Diagram EXTAL XTAL Gain Control VDD 1 8V Rf OSCCLK Peak Detector VSS VSS VSS C1 C2 Quartz Crystals Ceramic Resonators or Clock Monitor monitor fail OSCMOD _ ...

Page 251: ...200 kΩ and the XTAL pin is pulled down by an internal resistor of approximately 700 kΩ NOTE Freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier The loop controlled circuit XOSCLCP is not suited for overtone resonators and crystals 8 2 3 VSUP Regulator Power Input Pin Pin VSUP is the power input of VREGAUTO All currents so...

Page 252: ...quired and can improve the quality of this supply This supply domain is monitored by the Low Voltage Reset circuit and The Power On Reset circuit 8 2 9 VDDF NVM Logic Supply Pin VDDF is the supply domain for the NVM logic An off chip decoupling capacitor 220 nF X7R ceramic between VDDF and VSS is required and can improve the quality of this supply This supply domain is monitored by the Low Voltage...

Page 253: ...D02 R 0 0 0 0 0 0 0 0 W 0x0003 CPMURFLG R 0 PORF LVRF 0 COPRF 0 OMRF PMRF W 0x0004 CPMU SYNR R VCOFRQ 1 0 SYNDIV 5 0 W 0x0005 CPMU REFDIV R REFFRQ 1 0 0 0 REFDIV 3 0 W 0x0006 CPMU POSTDIV R 0 0 0 POSTDIV 4 0 W 0x0007 CPMUIFLG R RTIF 0 0 LOCKIF LOCK 0 OSCIF UPOSC W 0x0008 CPMUINT R RTIE 0 0 LOCKIE 0 0 OSCIE 0 W 0x0009 CPMUCLKS R PLLSEL PSTP CSAD COP OSCSEL1 PRE PCE RTI OSCSEL COP OSCSEL0 W 0x000A C...

Page 254: ...PIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 W 0x0015 CPMUAPIRL R APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0 W 0x0016 RESERVED CPMUTEST3 R 0 0 0 0 0 0 0 0 W 0x0017 CPMUHTTR R HTOE 0 0 0 HTTR3 HTTR2 HTTR1 HTTR0 W 0x0018 CPMU IRCTRIMH R TCTRIM 4 0 0 IRCTRIM 9 8 W 0x0019 CPMU IRCTRIML R IRCTRIM 7 0 W 0x001A CPMUOSC R OSCE 0 Reserved 0 0 0 0 0 W 0x001B CPMUPROT R 0 0 0 0 0 0 0 PROT W 0x001C RESE...

Page 255: ... monitor reset occurs Unaffected by System Reset Cleared by power on reset 5 PMRF is set to 1 when a PLL clock monitor reset occurs Unaffected by System Reset Cleared by power on reset Unimplemented or Reserved Figure 8 4 S12CPMU_UHV_V6 Flags Register CPMURFLG Table 8 1 CPMURFLG Field Descriptions Field Description 6 PORF Power on Reset Flag PORF is set to 1 when a power on reset occurs This flag ...

Page 256: ...LL operation the VCOFRQ 1 0 bits have to be selected according to the actual target VCOCLK 1 OMRF Oscillator Clock Monitor Reset Flag OMRF is set to 1 when a loss of oscillator crystal clock occurs Refer to8 5 3 Oscillator Clock Monitor Reset for details This flag can only be cleared by writing a 1 Writing a 0 has no effect 0 Loss of oscillator clock reset has not occurred 1 Loss of oscillator clo...

Page 257: ...nfigure the internal PLL filter for optimal stability and lock time For correct PLL operation the REFFRQ 1 0 bits have to be selected according to the actual REFCLK frequency as shown in Table 8 3 If IRC1M is selected as REFCLK OSCE 0 the PLL filter is fixed configured for the 1MHz fREF 2MHz range The bits can still be written but will have no effect on the PLL filter configuration For OSCE 1 sett...

Page 258: ...MU_UHV_V6 MC9S12ZVM Family Reference Manual Rev 1 3 258 Freescale Semiconductor Table 8 3 Reference Clock Frequency Selection if OSC_LCP is enabled REFCLK Frequency Ranges OSCE 1 REFFRQ 1 0 1MHz fREF 2MHz 00 2MHz fREF 6MHz 01 6MHz fREF 12MHz 10 fREF 12MHz 11 ...

Page 259: ...up to 32 Bus Clock cycles until fPLL is at the desired target frequency This is because the post divider gradually changes increases or decreases fPLL in order to avoid sudden load changes for the on chip voltage regulator 8 3 2 5 S12CPMU_UHV_V6 Interrupt Flags Register CPMUIFLG This register provides S12CPMU_UHV_V6 status bits and interrupt flags Module Base 0x0006 7 6 5 4 3 2 1 0 R 0 0 0 POSTDIV...

Page 260: ...ting a 0 has no effect If enabled LOCKIE 1 LOCKIF causes an interrupt request 0 No change in LOCK bit 1 LOCK bit has changed 3 LOCK Lock Status Bit LOCK reflects the current state of PLL lock condition Writes have no effect While PLL is unlocked LOCK 0 fPLL is fVCO 4 to protect the system from high core clock frequencies during the PLL stabilization time tlock 0 VCOCLK is not within the desired to...

Page 261: ...0 0 Unimplemented or Reserved Figure 8 9 S12CPMU_UHV_V6 Interrupt Enable Register CPMUINT Table 8 5 CPMUINT Field Descriptions Field Description 7 RTIE Real Time Interrupt Enable Bit 0 Interrupt requests from RTI are disabled 1 Interrupt will be requested whenever RTIF is set 4 LOCKIE PLL Lock Interrupt Enable Bit 0 PLL LOCK interrupt requests are disabled 1 Interrupt will be requested whenever LO...

Page 262: ...cleared by UPOSC 0 entering Full Stop Mode with COPOSCSEL1 1 or insufficient OSCCLK quality if OSCCLK is used as clock source for other clock domains for instance core clock etc NOTE After writing CPMUCLKS register it is strongly recommended to read back CPMUCLKS register to make sure that write of PLLSEL RTIOSCSEL and COPOSCSEL was successful This is because under certain circumstances writes hav...

Page 263: ...tion there is a latency time of 2 ACLK cycles to enter Stop Mode After exit from STOP mode when interrupt service routine is entered the software has to wait for 2 ACLK cycles before it is allowed to enter Stop mode again STOP instruction It is absolutely forbidden to enter Stop Mode before this time of 2 ACLK cycles has elapsed 0 COP running in Stop Mode ACLK for COP enabled in Stop Mode 1 COP st...

Page 264: ...SCCLK 0 COP OSCSEL0 COP Clock Select 0 COPOSCSEL0 and COPOSCSEL1 combined determine the clock source to the COP see also Table 8 7 If COPOSCSEL1 1 COPOSCSEL0 has no effect regarding clock select and changing the COPOSCSEL0 bit does not re start the COP time out period When COPOSCSEL1 0 COPOSCSEL0 selects the clock source to the COP to be either IRCCLK or OSCCLK Changing the COPOSCSEL0 bit re start...

Page 265: ... should be taken to ensure that the bus frequency does not exceed the specified maximum when frequency modulation is enabled Module Base 0x000A 7 6 5 4 3 2 1 0 R 0 0 FM1 FM0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Figure 8 11 S12CPMU_UHV_V6 PLL Control Register CPMUPLL Table 8 8 CPMUPLL Field Descriptions Field Description 5 4 FM1 FM0 PLL Frequency Modulation Enable Bits FM1 and FM0 enable frequency modul...

Page 266: ... loosing UPOSC status re starts the RTI time out period Module Base 0x000B 7 6 5 4 3 2 1 0 R RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 W Reset 0 0 0 0 0 0 0 0 Figure 8 12 S12CPMU_UHV_V6 RTI Control Register CPMURTI Table 8 10 CPMURTI Field Descriptions Field Description 7 RTDEC Decimal or Binary Divider Select Bit RTDEC selects decimal or binary based prescaler values 0 Binary based divider value S...

Page 267: ...011 4 OFF 4x210 4x211 4x212 4x213 4x214 4x215 4x216 0100 5 OFF 5x210 5x211 5x212 5x213 5x214 5x215 5x216 0101 6 OFF 6x210 6x211 6x212 6x213 6x214 6x215 6x216 0110 7 OFF 7x210 7x211 7x212 7x213 7x214 7x215 7x216 0111 8 OFF 8x210 8x211 8x212 8x213 8x214 8x215 8x216 1000 9 OFF 9x210 9x211 9x212 9x213 9x214 9x215 9x216 1001 10 OFF 10x210 10x211 10x212 10x213 10x214 10x215 10x216 1010 11 OFF 11x210 11x...

Page 268: ...103 100x103 250x103 500x103 1x106 0101 6 6x103 12x103 30x103 60x103 120x103 300x103 600x103 1 2x106 0110 7 7x103 14x103 35x103 70x103 140x103 350x103 700x103 1 4x106 0111 8 8x103 16x103 40x103 80x103 160x103 400x103 800x103 1 6x106 1000 9 9x103 18x103 45x103 90x103 180x103 450x103 900x103 1 8x106 1001 10 10 x103 20x103 50x103 100x103 200x103 500x103 1x106 2x106 1010 11 11 x103 22x103 55x103 110x10...

Page 269: ...ting CR 2 0 to 000 has no effect but counts for the write once condition Writing WCOP to 0 has no effect but counts for the write once condition When a non zero value is loaded from Flash to CR 2 0 the COP time out period is started A change of the COPOSCSEL0 or COPOSCSEL1 bit writing a different value or loosing UPOSC status while COPOSCSEL1 is clear and COPOSCSEL0 is set re starts the COP time o...

Page 270: ...and CR 2 0 bits while writing the CPMUCOP register It is intended for BDM writing the RSBCK without changing the content of WCOP and CR 2 0 0 Write of WCOP and CR 2 0 has an effect with this write of CPMUCOP 1 Write of WCOP and CR 2 0 has no effect with this write of CPMUCOP Does not count for write once 2 0 CR 2 0 COP Watchdog Timer Rate Select These bits select the COP time out rate see Table 8 ...

Page 271: ...S12ZVM Family Reference Manual Rev 1 3 Freescale Semiconductor 271 Table 8 15 COP Watchdog Rates if COPOSCSEL1 1 CR2 CR1 CR0 COPCLK Cycles to time out COPCLK is ACLK divided by 2 0 0 0 COP disabled 0 0 1 2 7 0 1 0 2 9 0 1 1 2 11 1 0 0 2 13 1 0 1 2 15 1 1 0 2 16 1 1 1 2 17 ...

Page 272: ...Write Only in Special Mode 8 3 2 12 Reserved Register CPMUTEST1 NOTE This reserved register is designed for factory test purposes only and is not intended for general user access Writing to this register when in Special Mode can alter the S12CPMU_UHV_V6 s functionality Read Anytime Write Only in Special Mode Module Base 0x000D 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented...

Page 273: ...o COP end of time out period to avoid a COP reset Sequences of 55 writes are allowed When the WCOP bit is set 55 and AA writes must be done in the last 25 of the selected time out period writing any value in the first 75 of the selected period will cause a COP reset 8 3 2 14 High Temperature Control Register CPMUHTCTL The CPMUHTCTL register configures the temperature sense features Read Anytime Wr...

Page 274: ...ed internally 3 HTE High Temperature Sensor Bandgap Voltage Enable Bit This bit enables the high temperature sensor and bandgap voltage amplifier 0 The temperature sensor and bandgap voltage amplifier is disabled 1 The temperature sensor and bandgap voltage amplifier is enabled 2 HTDS High Temperature Detect Status Bit This read only status bit reflects the temperature status Writes have no effect...

Page 275: ...d or Reserved Figure 8 19 Low Voltage Control Register CPMULVCTL Table 8 17 CPMULVCTL Field Descriptions Field Description 2 LVDS Low Voltage Detect Status Bit This read only status bit reflects the voltage level on VDDA Writes have no effect 0 Input voltage VDDA is above level VLVID or RPM 1 Input voltage VDDA is below level VLVIA and FPM 1 LVIE Low Voltage Interrupt Enable Bit 0 Interrupt reques...

Page 276: ...t at the external pin API_EXTCLK periodic high pulses are visible at the end of every selected period with the size of half of the minimum period APIR 0x0000 in Table 8 22 1 If APIEA and APIFE are set at the external pin API_EXTCLK a clock is visible with 2 times the selected API Period 3 APIEA Autonomous Periodical Interrupt External Access Enable Bit If set the waveform selected by bit APIES can...

Page 277: ...eset and Power Management Unit S12CPMU_UHV_V6 MC9S12ZVM Family Reference Manual Rev 1 3 Freescale Semiconductor 277 Figure 8 21 Waveform selected on API_EXTCLK pin APIEA 1 APIFE 1 APIES 0 APIES 1 API period API min period 2 ...

Page 278: ...0 0 After de assert of System Reset a value is automatically loaded from the Flash memory Figure 8 22 Autonomous Clock Trimming Register CPMUACLKTR Table 8 19 CPMUACLKTR Field Descriptions Field Description 7 2 ACLKTR 5 0 Autonomous Clock Period Trimming Bits See Table 8 20 for trimming effects The ACLKTR 5 0 value represents a signed number influencing the ACLK period time Table 8 20 Trimming Eff...

Page 279: ...t period of the API will show a latency time between two to three fACLK cycles due to synchronous clock gate release when the API feature gets enabled APIFE bit set Module Base 0x0014 7 6 5 4 3 2 1 0 R APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 8 23 Autonomous Periodical Interrupt Rate High Register CPMUAPIRH Module Base 0x0015 7 ...

Page 280: ...0 0000 0 2 ms1 1 When fACLK is trimmed to 20KHz 0 0001 0 4 ms1 0 0002 0 6 ms1 0 0003 0 8 ms1 0 0004 1 0 ms1 0 0005 1 2 ms1 0 0 FFFD 13106 8 ms1 0 FFFE 13107 0 ms1 0 FFFF 13107 2 ms1 1 0000 2 Bus Clock period 1 0001 4 Bus Clock period 1 0002 6 Bus Clock period 1 0003 8 Bus Clock period 1 0004 10 Bus Clock period 1 0005 12 Bus Clock period 1 1 FFFD 131068 Bus Clock period 1 FFFE 131070 Bus Clock per...

Page 281: ...his reserved register is designed for factory test purposes only and is not intended for general user access Writing to this register when in Special Mode can alter the S12CPMU_UHV_V6 s functionality Read Anytime Write Only in Special Mode Module Base 0x0016 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 8 25 Reserved Register CPMUTEST3 ...

Page 282: ...specification for details Unimplemented or Reserved Figure 8 26 High Temperature Trimming Register CPMUHTTR Table 8 24 CPMUHTTR Field Descriptions Field Description 7 HTOE High Temperature Offset Enable Bit If set the temperature sense offset is enabled 0 The temperature sense offset is disabled HTTR 3 0 bits don t care 1 The temperature sense offset is enabled HTTR 3 0 select the temperature offs...

Page 283: ...CTRIML Table 8 26 CPMUIRCTRIMH L Field Descriptions Field Description 15 11 TCTRIM 4 0 IRC1M temperature coefficient Trim Bits Trim bits for the Temperature Coefficient TC of the IRC1M frequency Table 8 27 shows the influence of the bits TCTRIM 4 0 on the relationship between frequency and temperature Figure 8 30 shows an approximate TC variation relative to the nominal TC of the IRC1M i e for TCT...

Page 284: ...er Management Unit S12CPMU_UHV_V6 MC9S12ZVM Family Reference Manual Rev 1 3 284 Freescale Semiconductor Figure 8 29 IRC1M Frequency Trimming Diagram IRCTRIM 9 0 000 IRCTRIM 9 6 IRCTRIM 5 0 IRC1M frequency IRCCLK 600KHz 1 5MHz 1MHz 3FF ...

Page 285: ...e the direction positive or negative of the variation of the TC relative to the nominal TC Setting TCTRIM 4 0 at 0x00000 or 0x10000 does not mean that the temperature coefficient will be zero These two combinations basically switch off the TC compensation module which results in the nominal TC of the IRC1M frequency temperature TCTRIM 4 0 0x11111 TCTRIM 4 0 0x01111 40C 150C TCTRIM 4 0 0x10000 or 0...

Page 286: ... IRC1M Indicative relative TC variation IRC1M indicative frequency drift for relative TC variation 00000 0 nominal TC of the IRC 0 00001 0 27 0 5 00010 0 54 0 9 00011 0 81 1 3 00100 1 08 1 7 00101 1 35 2 0 00110 1 63 2 2 00111 1 9 2 5 01000 2 20 3 0 01001 2 47 3 4 01010 2 77 3 9 01011 3 04 4 3 01100 3 33 4 7 01101 3 6 5 1 01110 3 91 5 6 01111 4 18 5 9 10000 0 nominal TC of the IRC 0 10001 0 27 0 5...

Page 287: ... ambient temperature which can vary from device to device 8 3 2 22 S12CPMU_UHV_V6 Oscillator Register CPMUOSC This registers configures the external oscillator XOSCLCP Read Anytime Write Anytime if PROT 0 CPMUPROT register and PLLSEL 1 CPMUCLKS register Else write has no effect NOTE Write to this register clears the LOCK and UPOSC status bits Module Base 0x001A 7 6 5 4 3 2 1 0 R OSCE 0 Reserved 0 ...

Page 288: ...cillator is disabled REFCLK for PLL is IRCCLK 1 External oscillator is enabled Oscillator clock monitor is enabled External oscillator is qualified by PLLCLK REFCLK for PLL is the external oscillator clock divided by REFDIV If OSCE bit has been set write 1 the EXTAL and XTAL pins are exclusively reserved for the oscillator and they can not be used anymore as general purpose I O until the next syst...

Page 289: ...me Module Base 0x001B 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 PROT W Reset 0 0 0 0 0 0 0 0 Figure 8 32 S12CPMU_UHV_V6 Protection Register CPMUPROT Field Description PROT Clock Configuration Registers Protection Bit This bit protects the clock configuration registers from accidental overwrite see list of protected registers above Writing 0x26 to the CPMUPROT register clears the PROT bit other write accesse...

Page 290: ...his reserved register is designed for factory test purposes only and is not intended for general user access Writing to this register when in Special Mode can alter the S12CPMU_UHV_V6 s functionality Read Anytime Write Only in Special Mode Module Base 0x001C 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 8 33 Reserved Register CPMUTEST2 ...

Page 291: ...N to be written value of INTXON to be written Write Access 0 0 blocked no effect 0 1 legal access 1 0 legal access 1 1 blocked no effect Table 8 30 CPMUVREGCTL Field Descriptions Field Description 2 EXTCON External voltage regulator Enable Bit for VDDC domain Should be disabled after system startup if VDDC domain is not used 0 VDDC domain disabled 1 VDDC domain enabled 1 EXTXON External voltage re...

Page 292: ... Register 2 CPMUOSC2 Table 8 31 CPMUOSC2 Field Descriptions Field Description 1 OMRE This bit enables the oscillator clock monitor reset If OSCE bit in CPMUOSC register is 1 then the OMRE bit can not be changed writes will have no effect 0 Oscillator clock monitor reset is disabled 1 Oscillator clock monitor reset is enabled 0 OSCMOD This bit selects the mode of the external oscillator XOSCLCP If ...

Page 293: ...f 1 to 16 to generate the reference frequency REFCLK using the REFDIV 3 0 bits Based on the SYNDIV 5 0 bits the PLL generates the VCOCLK by multiplying the reference clock by a 2 4 6 126 128 Based on the POSTDIV 4 0 bits the VCOCLK can be divided in a range of 1 2 3 4 5 6 to 32 to generate the PLLCLK NOTE Although it is possible to set the dividers to command a very high clock frequency do not exc...

Page 294: ...e lock detector compares the frequencies of the FBCLK and the REFCLK Therefore the speed of the lock detector is directly proportional to the reference clock frequency The circuit determines the lock condition based on this comparison If PLL LOCK interrupt requests are enabled the software can wait for an interrupt request and for instance check the LOCK bit If interrupt requests are disabled soft...

Page 295: ...de Figure 8 37 Stop Mode using PLLCLK as source of the Bus Clock Depending on the COP configuration there might be an additional significant latency time until COP is active again after exit from Stop Mode due to clock domain crossing synchronization This latency time occurs if COP clock source is ACLK and the CSAD bit is set please refer to CSAD bit description for details System PLLCLK Reset fVC...

Page 296: ...ing into Full Stop Mode Figure 8 38 Full Stop Mode using Oscillator Clock as source of the Bus Clock Depending on the COP configuration there might be a significant latency time until COP is active again after exit from Stop Mode due to clock domain crossing synchronization This latency time occurs if COP clock source is ACLK and the CSAD bit is set please refer to CSAD bit description for details...

Page 297: ...ample of how to use the oscillator as source of the Bus Clock is shown in Figure 8 39 Figure 8 39 Enabling the external oscillator PLLSEL OSCE EXTAL OSCCLK Core enable external oscillator by writing OSCE bit to one crystal resonator starts oscillating UPOSC UPOSC flag is set upon successful start of oscillation select OSCCLK as Core Bus Clock by writing PLLSEL to zero Clock based on PLL Clock base...

Page 298: ...ference clock for the PLL is based on the external oscillator The clock sources for COP and RTI can be based on the internal reference clock generator or on the external oscillator clock or the RC Oscillator ACLK This mode can be entered from default mode PEI by performing the following steps 1 Configure the PLL for desired bus frequency 2 Enable the external Oscillator OSCE bit 3 Wait for oscilla...

Page 299: ... enabled CPMUINT register 6 Select the Oscillator clock as source of the Bus clock PLLSEL 0 Loosing PLL lock status LOCK 0 means loosing the oscillator status information as well UPOSC 0 The impact of loosing the oscillator status UPOSC 0 in PBE mode is as follows PLLSEL is set automatically and the Bus clock source is switched back to the PLL clock The PLLCLK is derived from the VCO clock with it...

Page 300: ...8 5 3 Oscillator Clock Monitor Reset If the external oscillator is enabled OSCE 1 and the oscillator clock monitor reset is enabled OMRE 1 then in case of loss of oscillation or the oscillator frequency drops below the failure assert frequency fCMFA see device electrical characteristics for values the S12CPMU_UHV_V6 generates an Oscillator Clock Monitor Reset In Full Stop Mode the external oscilla...

Page 301: ...to CSAD bit description for details Table 8 34 gives an overview of the COP condition run static in Stop Mode depending on legal configuration and status bit settings Table 8 34 COP condition run static in Stop Mode Three control bits in the CPMUCOP register allow selection of seven COP time out periods When COP is enabled the program must write 55 and AA in this order to the CPMUARMCOP register d...

Page 302: ...ter write once has taken place Therefore these control bits should be modified before the final COP time out period and window COP setting is written The CPMUCOP register access to modify the COP time out period and window COP setting in MCU Normal Mode after reset release must be done with the WRTMASK bit cleared otherwise the update is ignored and this access does not count as the write once 8 5...

Page 303: ...tatus bit of the PLL changes either from a locked state to an unlocked state or vice versa Lock interrupts are locally disabled by setting the LOCKIE bit to zero The PLL Lock interrupt flag LOCKIF is set to1 when the lock condition has changed and is cleared to 0 by writing a 1 to the LOCKIF bit 8 6 1 3 Oscillator Status Interrupt When the OSCE bit is 0 then UPOSC stays 0 When OSCE 1 the UPOSC bit...

Page 304: ...eeds to be set The API timer is either clocked by the Autonomous Clock ACLK trimmable internal RC oscillator or the Bus Clock Timer operation will freeze when MCU clock source is selected and Bus Clock is turned off The clock source can be selected with bit APICLK APICLK can only be written when APIFE is not set The APIR 15 0 bits determine the interrupt period APIR 15 0 can only be written when A...

Page 305: ...e ACLK as clock source for both COP and API This guarantees lowest possible IDD current during Stop Mode Additionally it eases software implementation using the same clock source for both COP and API The Interrupt Service Routine ISR of the Autonomous Periodic Interrupt API should contain the write instruction to the CPMUARMCOP register The value byte written is derived from the main routine alter...

Page 306: ... loop and wait for the LOCKIF and OSCIF or poll CPMUIFLG register until both UPOSC and LOCK status are 1 that is CPMIFLG 0x1B continue to your main code execution here in case later in your code you want to disable the Oscillator and use the 1MHz IRCCLK as PLL reference clock Generally Whenever changing PLL reference clock REFCLK frequency to a higher value it is recommended to write CPMUSYNR 0x00...

Page 307: ...erface Signal is associated with one conversion flow control bit For information regarding internal interface connectivity related to the conversion flow control please refer to the device overview of the reference manual The ADCFLWCTL register can be controlled via internal interface only or via data bus only or by both depending on the register access configuration bits ACC_CFG 1 0 The four bits...

Page 308: ... 4 The two conversion flow control Mode Configurations for more information regarding conversion flow control Because internal components of the ADC are turned on off with bit ADC_EN the ADC requires a recovery time period tREC after ADC is enabled until the first conversion can be launched via a trigger When bit ADC_EN gets cleared transition from 1 b1 to 1 b0 any ongoing conversion sequence will...

Page 309: ...acy Left right justified result data Individual selectable VRH_0 1 and VRL_0 1 inputs on a conversion command basis please see Figure 9 2 Special conversions for selected VRH_0 1 VRL_0 1 VRL_0 1 VRH_0 1 2 15 conversion interrupts with flexible interrupt organization per conversion result One dedicated interrupt for End Of List type commands Command Sequence List CSL with a maximum number of 64 com...

Page 310: ... software before an MCU Stop Mode request As soon as flag SEQAD_IF is set the MCU Stop Mode request can be is issued With the occurrence of the MCU Stop Mode Request until exit from Stop Mode all flow control signals RSTA SEQA LDOK TRIG are cleared After exiting MCU Stop Mode the following happens in the order given with expected event s depending on the conversion flow control mode In ADC convers...

Page 311: ...ored and the corresponding flags are not set Alternatively the Sequence Abort Event can be issued by software before MCU Wait Mode request As soon as flag SEQAD_IF is set the MCU Wait Mode request can be issued With the occurrence of the MCU Wait Mode request until exit from Wait Mode all flow control signals RSTA SEQA LDOK TRIG are cleared After exiting MCU Wait Mode the following happens in the ...

Page 312: ...etect when the Restart Event can be issued without latency time in processing the event see also Figure 9 1 Figure 9 1 Conversion Flow Control Diagram Wait Mode SWAI 1 b1 AUT_RSTA 1 b0 MCU Freeze Mode Depending on the ADC Freeze Mode configuration bit FRZ_MOD the ADC either continues conversion in Freeze Mode or freezes conversion at next conversion boundary before the MCU Freeze Mode is entered A...

Page 313: ...ger Restart Result 63 AN2 AN1 AN0 Conversion RAM DMA access Command Comm_0 Comm_1 Comm 63 Sequence RAM DMA access List Error handler active Active Alternative Sequence Command List Idle LoadOK FlowCtrl Issue Error see reference manual for connectivity ADC Temperature Sense VREG_sense Internal_7 Internal_6 Internal_5 Internal_4 Internal_3 Internal_2 Channel int MUX Channel Conversion Flow Timing In...

Page 314: ...annel x The maximum input channel number is n Please refer to the device reference manual for the maximum number of input channels 9 3 1 2 VRH_0 VRH_1 VRL_0 VRL_1 VRH_0 1 are the high reference voltages VRL0 1 are the low reference voltages for a ADC conversion selectable on a conversion command basis Please refer to the device reference manual for availability and connectivity of these pins 9 3 1...

Page 315: ...L_1 R CSL_BMOD RVL_BMOD SMOD_ACC AUT_RSTA 0 0 0 0 W 0x0002 ADCSTS R CSL_SEL RVL_SEL DBECC_ERR Reserved READY 0 0 0 W 0x0003 ADCTIM R 0 PRS 6 0 W 0x0004 ADCFMT R DJM 0 0 0 0 SRES 2 0 W 0x0005 ADCFLWCTL R SEQA TRIG RSTA LDOK 0 0 0 0 W 0x0006 ADCEIE R IA_EIE CMD_EIE EOL_EIE Reserved TRIG_EIE RSTAR_EIE LDOK_EIE 0 W 0x0007 ADCIE R SEQAD_IE CONIF_OIE Reserved 0 0 0 0 0 W 0x0008 ADCEiF R IA_EIF CMD_EIF E...

Page 316: ...eserved Reserved W 0x0018 Reserved R Reserved W 0x0019 Reserved R Reserved W 0x001A Reserved R Reserved W 0x001B Reserved R Reserved W 0x001C ADCCIDX R 0 0 CMD_IDX 5 0 W 0x001D ADCCBP_0 R CMD_PTR 23 16 W 0x001E ADCCBP_1 R CMD_PTR 15 8 W 0x001F ADCCBP_2 R CMD_PTR 7 2 0 0 W 0x0020 ADCRIDX R 0 0 RES_IDX 5 0 W 0x0021 ADCRBP_0 R 0 0 0 0 RES_PTR 19 16 W 0x0022 ADCRBP_1 R RES_PTR 15 8 W 0x0023 ADCRBP_2 R...

Page 317: ...1 3 Freescale Semiconductor 317 0x0027 Reserved R Reserved W 0x0028 Reserved R Reserved 0 0 W 0x0029 Reserved R Reserved 0 Reserved W 0x002A 0x003F Reserved R 0 0 0 0 0 0 0 0 W Address Name Bit 7 6 5 4 3 2 1 Bit 0 Unimplemented or Reserved Figure 9 3 ADC12B_LBA Register Summary Sheet 3 of 3 ...

Page 318: ...his bit the ADC requires a recovery time period tREC after ADC is enabled until the first conversion can be launched via a trigger 0 ADC disabled 1 ADC enabled 14 ADC_SR ADC Soft Reset This bit causes an ADC Soft Reset if set after a severe error occurred see list of severe errors in Section 9 4 2 9 ADC Error Interrupt Flag Register ADCEIF that causes the ADC to cease operation It clears all overr...

Page 319: ...t by hardware If STR_SEQA 1 b1 and if a Sequence Abort Event or Restart Event is issued during a conversion the data of this conversion is stored and the respective conversion complete flag is set and Intermediate Result Information Register is updated Restart Event only occurs during the last conversion of a CSL and no Sequence Abort Event is in process SEQA clear does not set the RSTA_EIF error ...

Page 320: ...rols register access rights in MCU Special Mode This bit is automatically cleared when leaving MCU Special Mode Note When this bit is set also the ADCCMD register is writeable via the data bus to allow modification of the current command for debugging purpose But this is only possible if the current command is not already processed conversion not started Please see access details given for each re...

Page 321: ... Value List Select Bit This bit controls and indicates which ADC Result List is active This bit can only be written if bit ADC_EN is clear After storage of the initial Result Value List this bit toggles in RVL double buffer mode whenever the conversion result of the first conversion of the current CSL is stored or a CSL got aborted In RVL single buffer mode this bit is forced to 1 b0 by bit RVL_BM...

Page 322: ...MOD_ACC is set Module Base 0x0003 7 6 5 4 3 2 1 0 R 0 PRS 6 0 W Reset 0 0 0 0 0 1 0 1 Unimplemented or Reserved Figure 9 7 ADC Timing Register ADCTIM Table 9 6 ADCTIM Field Descriptions Field Description 6 0 PRS 6 0 ADC Clock Prescaler These 7bits are the binary prescaler value PRS The ADC conversion clock frequency is calculated as follows Refer to Device Specification for allowed frequency range...

Page 323: ...a Justification Conversion result data format is always unsigned This bit controls justification of conversion result data in the conversion result list 0 Left justified data in the conversion result list 1 Right justified data in the conversion result list 2 0 SRES 2 0 ADC Resolution Select These bits select the resolution of conversion results See Table 9 8 for coding Table 9 8 Selectable Conver...

Page 324: ...conversion sequence back to back conversions it takes five Bus Clock cycles plus two ADC conversion clock cycles pump phase from current conversion period end until the newly selected channel is sampled in the following conversion period Trigger Mode When a Restart Event occurs a Trigger Event is issued simultaneously The time required to process the Restart Event is mainly defined by the internal...

Page 325: ...l modes Restart Mode and Trigger Mode when bit RSTA gets set automatically bit SEQA gets set when the ADC has not reached one of the following scenarios A Sequence Abort request is about to be executed or has been executed End Of List command type has been executed or is about to be executed In case bit SEQA is set automatically the Restart error flag RSTA_EIF is set to indicate an unexpected Rest...

Page 326: ...nce Command List 1 Restart from top of active Sequence Command List 4 LDOK Load OK for alternative Command Sequence List This bit indicates if the preparation of the alternative Sequence Command List is done and Command Sequence List must be swapped with the Restart Event This bit is cleared when bit RSTA is set Restart Event executed and the Command Sequence List got swapped This bit can only be ...

Page 327: ...Can Not Occur 0 0 1 0 Both Modes Valid 5 0 0 1 1 Both Modes Can Not Occur 0 1 0 0 Both Modes Valid 2 0 1 0 1 Both Modes Can Not Occur 0 1 1 0 Both Modes Can Not Occur 0 1 1 1 Both Modes Can Not Occur 1 0 0 0 Both Modes Valid 4 1 0 0 1 Both Modes Valid 1 4 1 0 1 0 Both Modes Valid 3 4 5 1 0 1 1 Both Modes Valid 1 3 4 5 1 1 0 0 Restart Mode Error flag TRIG_EIF set Trigger Mode Valid 2 4 6 1 1 0 1 Re...

Page 328: ... Bit This bit enables the command value error interrupt 0 Command value interrupt disabled 1 Command value interrupt enabled 5 EOL_EIE End Of List Error Interrupt Enable Bit This bit enables the End Of List error interrupt 0 End Of List error interrupt disabled 1 End Of List error interrupt enabled 3 TRIG_EIE Conversion Sequence Trigger Error Interrupt Enable Bit This bit enables the conversion se...

Page 329: ... 9 12 ADCIE Field Descriptions Field Description 7 SEQAD_IE Conversion Sequence Abort Done Interrupt Enable Bit This bit enables the conversion sequence abort event done interrupt 0 Conversion sequence abort event done interrupt disabled 1 Conversion sequence abort event done interrupt enabled 6 CONIF_OIE ADCCONIF Register Flags Overrun Interrupt Enable This bit enables the flag which indicates if...

Page 330: ...IF Reserved TRIG_EIF RSTAR_EIF LDOK_EIF 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 9 12 ADC Error Interrupt Flag Register ADCEIF Table 9 13 ADCEIF Field Descriptions Field Description 7 IA_EIF Illegal Access Error Interrupt Flag This flag indicates that storing the conversion result caused an illegal access error or conversion command loading from outside system RAM or NVM area occ...

Page 331: ...of type severe 0 No trigger error occurred 1 A trigger error occurred 2 RSTAR_EIF Restart Request Error Interrupt Flag This flag indicates a flow control issue It is set when a Restart Request occurs after a Trigger Event and before one of the following conditions was reached The End Of List command type has been executed Depending on bit STR_SEQA if the End Of List command type is about to be exe...

Page 332: ...on from top of CSL is stored Module Base 0x0009 7 6 5 4 3 2 1 0 R SEQAD_IF CONIF_OIF Reserved 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 9 13 ADC Interrupt Flag Register ADCIF Table 9 14 ADCIF Field Descriptions Field Description 7 SEQAD_IF Conversion Sequence Abort Done Interrupt Flag This flag is set when the Sequence Abort Event has been executed except the Sequence Abor...

Page 333: ...mplemented or Reserved Figure 9 14 ADC Conversion Interrupt Enable Register ADCCONIE Table 9 15 ADCCONIE Field Descriptions Field Description 15 1 CON_IE 15 1 Conversion Interrupt Enable Bits These bits enable the individual interrupts which can be triggered via interrupt flags CON_IF 15 1 0 ADC conversion interrupt disabled 1 ADC conversion interrupt enabled 0 EOL_IE End Of List Interrupt Enable ...

Page 334: ...L double buffer mode and related registers ADCIMDRI and ADCEOLRI NOTE Overrun situation of a flag CON_IF 15 1 and EOL_IF are indicated by flag CONIF_OIF Module Base 0x000C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CON_IF 15 1 EOL_IF W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 9 15 ADC Conversion Interrupt Flag Register ADCCONIF Table 9 16 ADCCONIF Field Descriptions Fiel...

Page 335: ...ive used RVL buffer at the occurrence of a conversion interrupt flag CON_IF 15 1 occurrence of an intermediate result buffer fill event or when a Sequence Abort Event gets executed 0 RVL_0 active used when a conversion interrupt flag CON_IF 15 1 got set 1 RVL_1 active used when a conversion interrupt flag CON_IF 15 1 got set 5 0 RIDX_IMD 5 0 RES_IDX Value At Intermediate Event These bits indicate ...

Page 336: ... 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 9 17 ADC End Of List Result Information Register ADCEOLRI Table 9 18 ADCEOLRI Field Descriptions Field Description 7 CSL_EOL Active CSL When End Of List Command Type Executed This bit indicates the active used CSL when a End Of List command type has been executed and related data has been stored to RAM 0 CSL_0 active when End Of List command type exe...

Page 337: ...Field Descriptions Field Description 31 30 CMD_SEL 1 0 Conversion Command Select Bits These bits define the type of current conversion described in Table 9 20 27 24 INTFLG_SEL 3 0 Conversion Interrupt Flag Select Bits These bits define which interrupt flag is set in the ADCIFH L register at the end of current conversion The interrupt flags ADCIF 15 1 are selected via binary coded bits INTFLG_SEL 3...

Page 338: ...or Table 9 21 Conversion Interrupt Flag Select CON_IF 15 1 INTFLG_SEL 3 INTFLG_SEL 2 INTFLG_SEL 1 INTFLG_SEL 0 Comment 0x0000 0 0 0 0 No flag set 0x0001 0 0 0 1 Only one flag can be set one hot coding 0x0002 0 0 1 0 0x0004 0 0 1 1 0x0008 0 1 0 0 0x0010 0 1 0 1 0x0800 1 1 0 0 0x1000 1 1 0 1 0x2000 1 1 1 0 0x4000 1 1 1 1 ...

Page 339: ...egister 1 ADCCMD_1 Table 9 22 ADCCMD_1 Field Descriptions Field Description 23 VRH_SEL Reference High Voltage Select Bit This bit selects the high voltage reference for current conversion 0 VRH_0 input selected as high voltage reference 1 VRH_1 input selected as high voltage reference 22 VRL_SEL Reference Low Voltage Select Bit This bit selects the voltage reference for current conversion 0 VRL_0 ...

Page 340: ...umber of analog input channels 0 0 0 1 1 1 Reserved 0 0 1 0 0 0 Internal_0 ADC temperature sense 0 0 1 0 0 1 Internal_1 Vreg_3v3 sense 0 0 1 0 1 0 Internal_2 0 0 1 0 1 1 Internal_3 0 0 1 1 0 0 Internal_4 0 0 1 1 0 1 Internal_5 0 0 1 1 1 0 Internal_6 0 0 1 1 1 1 Internal_7 0 1 0 0 0 0 AN0 0 1 0 0 0 1 AN1 0 1 0 0 1 0 AN2 0 1 0 0 1 1 AN3 0 1 0 1 0 0 AN4 0 1 x x x x ANx 1 x x x x x Reserved Table 9 23...

Page 341: ...n sequence is ongoing Module Base 0x0016 15 14 13 12 11 10 9 8 R SMP 4 0 0 0 Reserved W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 9 20 ADC Command Register 2 ADCCMD_2 Table 9 24 ADCCMD_2 Field Descriptions Field Description 15 11 SMP 4 0 Sample Time Select Bits These four bits select the length of the sample time in units of ADC conversion clock cycles Note that the ADC conversion clo...

Page 342: ...r 0 1 0 1 0 14 0 1 0 1 1 15 0 1 1 0 0 16 0 1 1 0 1 17 0 1 1 1 0 18 0 1 1 1 1 19 1 0 0 0 0 20 1 0 0 0 1 21 1 0 0 1 0 22 1 0 0 1 1 23 1 0 1 0 0 24 1 0 1 0 1 Reserved 1 0 1 1 0 Reserved 1 0 1 1 1 Reserved 1 1 x x x Reserved Table 9 25 Sample Time Select SMP 4 SMP 3 SMP 2 SMP 1 SMP 0 Sample Time in Number of ADC Clock Cycles ...

Page 343: ...VM Family Reference Manual Rev 1 3 Freescale Semiconductor 343 9 4 2 18 ADC Command Register 3 ADCCMD_3 Module Base 0x0017 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 9 21 ADC Command Register 3 ADCCMD_3 ...

Page 344: ... 3 2 1 0 R 0 0 CMD_IDX 5 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 9 22 ADC Command Index Register ADCCIDX Table 9 26 ADCCIDX Field Descriptions Field Description 5 0 CMD_IDX 5 0 ADC Command Index Bits These bits represent the command index value for the conversion commands relative to the two CSL start addresses in the memory map These bits do not represent absolute addresses ins...

Page 345: ... 0 0 0 0 Module Base 0x001F 7 6 5 4 3 2 1 0 R CMD_PTR 7 2 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 9 23 ADC Command Base Pointer Registers ADCCBP_0 ADCCBP_1 ADCCBP_2 Table 9 27 ADCCBP Field Descriptions Field Description 23 2 CMD_PTR 23 2 ADC Command Base Pointer Address These bits define the base address of the two CSL areas inside the system RAM or NVM of the memory map They ...

Page 346: ... 4 3 2 1 0 R 0 0 RES_IDX 5 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 9 24 ADC Result Index Register ADCRIDX Table 9 28 ADCRIDX Field Descriptions Field Description 5 0 RES_IDX 5 0 ADC Result Index Bits These read only bits represent the index value for the conversion results relative to the two RVL start addresses in the memory map These bits do not represent absolute addresses in...

Page 347: ...5 8 W Reset 0 0 0 0 0 0 0 0 Module Base 0x0023 7 6 5 4 3 2 1 0 R RES_PTR 7 2 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 9 25 ADC Result Base Pointer Registers ADCRBP_0 ADCRBP_1 ADCRBP_2 Table 9 29 ADCRBP Field Descriptions Field Description 19 2 RES_PTR 19 2 ADC Result Base Pointer Address These bits define the base address of the list areas inside the system RAM of the memory ma...

Page 348: ...sion command and result offset value relative to the conversion command base pointer address and result base pointer address in the memory map to refer to CSL_0 and RVL_0 It is used to calculate the address inside the system RAM to which the result at the end of the current conversion is stored to and the area RAM or NVM from which the conversion commands are loaded from This is a zero offset null...

Page 349: ...ons Field Description 6 0 CMDRES_OFF1 6 0 ADC Result Address Offset Value These bits represent the conversion command and result offset value relative to the conversion command base pointer address and result base pointer address in the memory map to refer to CSL_1 and RVL_1 It is used to calculate the address inside the system RAM to which the result at the end of the current conversion is stored...

Page 350: ...nd charge of the storage node sample capacitor to the voltage level of the analog signal at the selected ADC input channel This architecture employs the advantage of reduced crosstalk between channels The sample buffer amplifier is used to raise the effective input impedance of the A D machine so that external components higher bandwidth or higher impedance connected as specified are less signific...

Page 351: ...g the sampled and stored analog voltage with a series of binary coded discrete voltages By following a binary search algorithm the A D machine identifies the discrete voltage that is nearest to the sampled and stored voltage Only analog input signals within the potential range of VRL_0 1 to VRH_0 1 A D reference potentials will result in a non railed digital output code 9 5 3 2 Introduction of the...

Page 352: ... must contain at least one conversion command and one end of list command type identifier The minimum number of command sequences inside a CSL is zero and the maximum number of command sequences is 63 A command sequence is defined with bits CMD_SEL 1 0 in the register ADCCMD_M by defining the end of a conversion sequence The Figure 9 29 and Figure 9 30 provides examples of a CSL Figure 9 29 Exampl...

Page 353: ...ommand_9 Command_10 Command_11 Command_12 Command_13 CSL_0 normal conversion normal conversion Command coding information normal conversion normal conversion normal conversion normal conversion normal conversion 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 CMD_SEL 1 0 done by bits normal conversion normal conversion normal conversion End Of List wrap to top continue normal conversion normal...

Page 354: ...L alternative CSL becomes active CSL CSL swapping Which list is actively used for ADC command loading is indicated by bit CSL_SEL The register to define the CSL start addresses ADCCBP can be set to any even location of the system RAM or NVM area It is the user s responsibility to make sure that the different ADC lists do not overlap or exceed the system RAM or the NVM area respectively The error f...

Page 355: ...e CSL can be modified to prepare the ADC for new conversion sequences in CSL double buffered mode When the ADC is enabled the command address registers ADCCBP ADCCROFF_0 2 ADCCIDX are read only and register ADCCIDX is under control of the ADC Memory Map 0x00_0000 Register Space RAM or NVM Space RAM or NVM start address RAM or NVM end address CSL_0 active ADCCBP ADCCROFF_0 ADCCBP ADCCROFF_0 CSL_SEL...

Page 356: ...before entry of Stop or Wait Mode with bit SWAI set is overwritten after exit from the MCU Operating Mode see also Section 9 2 1 2 MCU Operating Modes Which list is actively used for the ADC conversion result storage is indicated by bit RVL_SEL The register to define the RVL start addresses ADCRBP can be set to any even location of the system RAM area It is the user s responsibility to make sure t...

Page 357: ...ned data representation Left and right justification inside the entity is selected via the DJM control bit Unused bits inside an entity are stored zero Table 9 32 Conversion Result Justification Overview Conversion Resolution SRES 1 0 Left Justified Result DJM 1 b0 Right Justified Result DJM 1 b1 8 bit Result 7 0 8 b00000000 8 b00000000 Result 7 0 10 bit Result 9 0 6 b000000 6 b000000 Result 9 0 1...

Page 358: ... top of current CSL is done automatically Therefore the current CSL can be executed again after the End Of List command type is executed by a Trigger Event only In Restart Mode configuration the execution of a CSL is controlled via Trigger Events and Restart Events After execution of the End Of List command the conversion flow must be continued by a Restart Event followed by a Trigger Event and th...

Page 359: ... TRIG is set when no conversion or conversion sequence is ongoing ADC idle and the RVL done condition is reached by one of the following A End Of List command type has been executed A Sequence Abort Event is in progress or has been executed The ADC executes the Restart Event followed by the Trigger Event In ADC conversion flow control mode Trigger Mode a Restart Event and a simultaneous Trigger Ev...

Page 360: ...n or conversion sequence is ongoing ADC idle and the RVL done condition is reached by one of the following A End Of List command type has been executed A Sequence Abort Event is in progress or has been executed The ADC executes the Restart Event followed by the Trigger Event In ADC conversion flow control mode Trigger Mode a Restart Event and a simultaneous Trigger Event via internal interface or ...

Page 361: ...one condition not reached The RVL done condition is not reached if An End Of List command type has not been executed A Sequence Abort Event has not been executed bit SEQA not already set In all ADC conversion flow control modes a Sequence Abort Event can be issued at any time In ADC conversion flow control mode Restart Mode after a conversion sequence abort request has been executed it is mandator...

Page 362: ...cessed and RSTA is set again one cycle later LoadOK Overrun Simultaneously at any Restart Request overrun situation the LoadOK input is evaluated and the status is captured in a background register which is alternated anytime a Restart Request Overrun occurs while Load OK Request is asserted The Load OK background register is cleared as soon as the pending Restart Request gets processed Trigger Ov...

Page 363: ... Load conversion command to background conversion command register 1 The control bit s RSTA and LDOK if set are cleared Wait for Trigger Event to start conversion Generic flow for ADC register load during conversion The index registers ADCCIDX is incremented The inactive background command register is loaded with a new conversion command Generic flow for ADC result storage at end of conversion Ind...

Page 364: ...s 9 7 1 ADC Conversion Interrupt The ADC provides one conversion interrupt associated to 16 interrupt enable bits with dedicated interrupt flags The 16 interrupt flags consist of 15 conversion interrupt flags which can be associated to any conversion completion One additional interrupt flag which is fixed to the End Of List conversion command type within the active CSL The association of the conve...

Page 365: ...issues which cause an error interrupt if enabled and cease ADC operation IA_EIF CMD_EIF EOL_EIF TRIG_EIF In order to make the ADC operational again an ADC Soft Reset must be issued which clears the above listed error interrupt flags NOTE It is important to note that if flag DBECC_ERR is set the ADC ceases operation as well but does not cause an ADC error interrupt Instead a machine exception is is...

Page 366: ...ndary After an aborted conversion or conversion sequence Figure 9 35 CSL Single Buffer Mode RVL Single Buffer Mode Diagram 9 8 2 List Usage CSL single buffer mode and RVL double buffer mode In this use case the CSL is configured for single buffer mode CSL_BMOD 1 b0 and the RVL is configured for double buffer mode RVL_BMOD 1 b1 In this buffer configuration only the result list RVL is switched when ...

Page 367: ...use case can be used if the channel order or CSL length varies very frequently in an application 9 8 4 List Usage CSL double buffer mode and RVL single buffer mode In this use case the CSL is configured for double buffer mode CSL_BMOD 1 b1 and the RVL is configured for single buffer mode RVL_BMOD 1 b0 The two command lists can be different sizes and the allocated result list memory area in the RAM...

Page 368: ...er mode the registers ADCIMDRI and ADCEOLRI can be used by the application software to identify which RVL holds relevant and latest data and which CSL is related to this data These registers are updated at the setting of one of the CON_IF 15 1 or the EOL_IF interrupt flags As described in the register description Section 9 4 2 13 ADC Intermediate Result Information Register ADCIMDRI and Section 9 ...

Page 369: ... 1 b1 set by hardware cleared by software 1 b1 before next EOL should be cleared by software before Stop Mode entry return to execute from top of CSL followed by next CSL to store first result of ongoing and before EOL RVL_IMD 1 b0 1 b1 CSL_IMD 1 b0 1 b1 CON_IF 15 1 0x0001 INT_1 0x0000 0x0000 Flag should be cleared by software before it is set again bits are valid bits not valid until first INT EO...

Page 370: ...ccur one after the other or simultaneously which causes the ADC to start conversion with commands loaded from CSL_0 If CSL_1 should be executed at the initial conversion start after device reset Bit LDOK must be set simultaneously with the Restart Event followed by a Trigger Event depending on the selected conversion flow control mode the Trigger events must occur simultaneously or after the Resta...

Page 371: ...art conversion command list execution it is mandatory that the ADC is idle no conversion or conversion sequence is ongoing If necessary a possible ongoing conversion sequence can be aborted by the Sequence Abort Event setting bit SEQA As soon as bit SEQA is cleared by the ADC the current conversion sequence has been aborted and the ADC is idle no conversion sequence or conversion ongoing After a c...

Page 372: ...g on data transfer rate either use single or double buffer RVL configuration Define a list of conversion commands which only contains the End Of List command with automatic wrap to top of CSL After finishing the configuration and enabling the ADC an initial Restart Event is sufficient to launch the continuous conversion until next device reset or low power mode In case a Low Power Mode is used If ...

Page 373: ...fter execution of the End Of List command Figure 9 42 Conversion Flow Control Diagram Triggered Conversion CSL Repetition Figure 9 43 Conversion Flow Control Diagram Triggered Conversion with Stop Mode In case a Low Power Mode is used If bit AUT_RSTA is set before Low Power Mode is entered the conversion continues automatically as soon as a low power mode Stop Mode or Wait Mode with bit SWAI set i...

Page 374: ...e a Restart Event is finished this causes the TRIG_EIF flag being set This allows detection of false flow control sequences Figure 9 44 Conversion Flow Control Diagram Fully Timing Controlled Conversion with Stop Mode Unlike the Stop Mode entry shown in Figure 9 43 and Figure 9 44 it is recommended to issue the Stop Mode at sequence boundaries when ADC is idle and no conversion conversion sequence...

Page 375: ...m power modes 1 Run mode The activation of the VSUP Level Sense Enable BSUSE 1 or ADC connection Enable BSUAE 1 closes the path from VSUP pin through the resistor chain to ground and enables the associated features if selected 2 Stop mode During stop mode operation the path from the VSUP pin through the resistor chain to ground is opened and the low and high voltage sense features are disabled The...

Page 376: ...al Signal Description This section lists the name and description of all external ports 10 2 1 VSUP Voltage Supply Pin This pin is the chip supply It can be internally connected for voltage measurement The voltage present at this input is scaled down by an internal voltage divider and can be routed to the internal ADC or to a comparator VSUP to ADC BVLC BVHC BSUAE BSUSE BVHS BVLS 1 0 Comparator 1 ...

Page 377: ...vel 10 3 2 Register Descriptions This section consists of register descriptions in address order Each description includes a standard register diagram with an associated figure number Details of register bit and field function follow the register diagrams in bit order Unused bits read back zero Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 BATE R 0 BVHS BVLS 1 0 BSUAE BSUSE 0 0 W 0x0...

Page 378: ...6 BVHS BATS Voltage High Select This bit selects the trigger level for the Voltage Level High Condition BVHC 0 Voltage level VHBI1 is selected 1 Voltage level VHBI2 is selected 5 4 BVLS 1 0 BATS Voltage Low Select This bit selects the trigger level for the Voltage Level Low Condition BVLC 00 Voltage level VLBI1 is selected 01 Voltage level VLBI2 is selected 10 Voltage level VLBI3 is selected 11 Vo...

Page 379: ... Register Field Descriptions Field Description 1 BVHC BATS Voltage Sense High Condition Bit This status bit indicates that a high voltage at VSUP depending on selection is present 0 Vmeasured VHBI_A rising edge or Vmeasured VHBI_D falling edge 1 Vmeasured VHBI_A rising edge or Vmeasured VHBI_D falling edge 0 BVLC BATS Voltage Sense Low Condition Bit This status bit indicates that a low voltage at ...

Page 380: ...ister Field Descriptions Field Description 1 BVHIE BATS Interrupt Enable High Enables High Voltage Interrupt 0 No interrupt will be requested whenever BVHIF flag is set 1 Interrupt will be requested whenever BVHIF flag is set 0 BVLIE BATS Interrupt Enable Low Enables Low Voltage Interrupt 0 No interrupt will be requested whenever BVLIF flag is set 1 Interrupt will be requested whenever BVLIF flag ...

Page 381: ...t is only available in CPU run mode Entering and exiting CPU stop mode has no effect on the interrupt flags To make sure the interrupt generation works properly the bus clock frequency must be higher than the Voltage Warning Low Pass Filter frequency fVWLP_filter Table 10 5 BATIF Register Field Descriptions Field Description 1 BVHIF BATS Interrupt Flag High Detect The flag is set to 1 when BVHC st...

Page 382: ...e VLBI1_A falling edge or Vmeasure VLBI1_D rising edge or when b VLBI2 selected with BVLS 1 0 0x1 at pin VSUP Vmeasure VLBI2_A falling edge or Vmeasure VLBI2_D rising edge or when c VLBI3 selected with BVLS 1 0 0x2 Vmeasure VLBI3_A falling edge or Vmeasure VLBI3_D rising edge or when d VLBI4 selected with BVLS 1 0 0x3 Vmeasure VLBI4_A falling edge or Vmeasure VLBI4_D rising edge then BVLC is set B...

Page 383: ...en a VHBI2 selected with BVHS 1 Vmeasure VHBI2_A rising edge or Vmeasure VHBI2_D falling edge then BVHC is set BVHC status bit indicates that a high voltage at pin VSUP is present The High Voltage Interrupt flag BVHIF is set to 1 when a Voltage High Condition BVHC changes state The Interrupt flag BVHIF can only be cleared by writing a 1 If the interrupt is enabled by bit BVHIE the module requests ...

Page 384: ...Chapter 10 Supply Voltage Sensor BATSV3 MC9S12ZVM Family Reference Manual Rev 1 3 384 Freescale Semiconductor ...

Page 385: ...A full access for the counter registers or the input capture output compare registers should take place in one clock cycle Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word 11 1 1 Features The TIM16B4CV3 includes these distinctive features Up to 4 channels available refer to device specification for exact number All c...

Page 386: ...er of external pins Refer to device specification for exact number Prescaler 16 bit Counter Input capture Output compare IOC0 IOC2 IOC1 IOC3 Timer overflow interrupt Timer channel 0 interrupt Timer channel 2 interrupt Registers Bus clock Input capture Output compare Input capture Output compare Input capture Output compare Channel 0 Channel 1 Channel 2 Channel 3 Timer channel 1 interrupt Timer cha...

Page 387: ...n includes a standard register diagram with an associated figure number Details of register bit and field function follow the register diagrams in bit order Only bits related to implemented channels are valid Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 TIOS R RESERVE D RESERVE D RESERVE D RESERVE D IOS3 IOS2 IOS1 IOS0 W 0x0001 CFORC R 0 0 0 0 0 0 0 0 W RESERVE D RESERVE D RESERVE D RESERVE D FOC3...

Page 388: ...xL 1 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0024 0x002B Reserved R W 0x002C OCPD R RESERVE D RESERVE D RESERVE D RESERVE D OCPD3 OCPD2 OCPD1 OCPD0 W 0x002D Reserved R 0x002E PTPSR R PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 W 0x002F Reserved R W 1 The register is available only if corresponding channel exists Module Bas...

Page 389: ... FOC1 FOC0 Reset 0 0 0 0 0 0 0 0 Figure 11 5 Timer Compare Force Register CFORC Table 11 3 CFORC Field Descriptions Note Writing to unavailable bits has no effect Reading from unavailable bits return a zero Field Description 3 0 FOC 3 0 Note Force Output Compare Action for Channel 3 0 A write to this register with the corresponding data bit s set causes the action which is programmed for output co...

Page 390: ... 3 2 1 0 R TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 W Reset 0 0 0 0 0 0 0 0 Figure 11 7 Timer Count Register Low TCNTL Module Base 0x0006 7 6 5 4 3 2 1 0 R TEN TSWAI TSFRZ TFFCA PRNT 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 11 8 Timer System Control Register 1 TSCR1 Table 11 4 TSCR1 Field Descriptions Field Description 7 TEN Timer Enable 0 Disables the main timer inclu...

Page 391: ...a care is required to avoid accidental flag clearing due to unintended accesses 3 PRNT Precision Timer 0 Enables legacy timer PR0 PR1 and PR2 bits of the TSCR2 register are used for timer counter prescaler selection 1 Enables precision timer All bits of the PTPSR register are used for Precision Timer Prescaler Selection and all bits This bit is writable only once out of reset Module Base 0x0007 7 ...

Page 392: ... bits return a zero Field Description 3 0 OMx Output Mode These four pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare When either OMx or OLx is 1 the pin associated with OCx becomes an output tied to OCx Note For an output line to be driven by an OCx the OCPDx must be cleared 3 0 OLx Output Level These fourpairs of control bits are ...

Page 393: ...00B 7 6 5 4 3 2 1 0 R EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A W Reset 0 0 0 0 0 0 0 0 Figure 11 13 Timer Control Register 4 TCTL4 Table 11 8 TCTL3 TCTL4 Field Descriptions Note Writing to unavailable bits has no effect Reading from unavailable bits return a zero Field Description 3 0 EDGnB EDGnA Input Capture Edge Control These four pairs of control bits configure the input capture edge de...

Page 394: ...ion 3 0 C3I C0I Input Capture Output Compare x Interrupt Enable The bits in TIE correspond bit for bit with the bits in the TFLG1 status register If cleared the corresponding flag is disabled from causing a hardware interrupt If set the corresponding flag is enabled to cause a interrupt Module Base 0x000D 7 6 5 4 3 2 1 0 R TOI 0 0 0 RESERVED PR2 PR1 PR0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Res...

Page 395: ... 8 1 0 0 Bus Clock 16 1 0 1 Bus Clock 32 1 1 0 Bus Clock 64 1 1 1 Bus Clock 128 Module Base 0x000E 7 6 5 4 3 2 1 0 R RESERVED RESERVED RESERVED RESERVED C3F C2F C1F C0F W Reset 0 0 0 0 0 0 0 0 Figure 11 16 Main Timer Interrupt Flag 1 TFLG1 Table 11 13 TRLG1 Field Descriptions Note Writing to unavailable bits has no effect Reading from unavailable bits return a zero Field Description 3 0 C 3 0 F In...

Page 396: ...corresponding bits to be cleared Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set Module Base 0x000F 7 6 5 4 3 2 1 0 R TOF 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 11 17 Main Timer Interrupt Flag 2 TFLG2 Table 11 14 TRLG2 Field Descriptions Field Description 7 TOF Timer Overflow Flag Set when 16 bit free running timer overflows fro...

Page 397: ... Read Anytime Write Anytime for output compare function Writes to these registers have no meaning or effect during input capture All timer input capture output compare registers are reset to 0x0000 NOTE Read Write access in byte mode for high byte should take place before low byte otherwise it will give a different result Module Base 0x0010 TC0H 0x0012 TC1H 0x0014 TC2H 0x0016 TC3H 0x0018 RESERVD 0...

Page 398: ... Pin Disconnect Register OCPD Table 11 15 OCPD Field Description Note Writing to unavailable bits has no effect Reading from unavailable bits return a zero Field Description 3 0 OCPD 3 0 Output Compare Pin Disconnect Bits 0 Enables the timer channel port Output Compare action will occur on the channel pin These bits do not affect the input capture or pulse accumulator functions 1 Disables the time...

Page 399: ...sary Table 11 16 PTPSR Field Descriptions Field Description 7 0 PTPS 7 0 Precision Timer Prescaler Select Bits These eight bits specify the division rate of the main Timer prescaler These are effective only when the PRNT bit of TSCR1 is set to 1 Table 11 17 shows some selection examples in this case The newly selected prescale factor will not take effect until the next synchronized edge where all ...

Page 400: ...ue that generates a divide by 1 2 4 8 16 32 64 and 128 when the PRNT bit in TSCR1 is disabled PRESCALER CHANNEL 0 IOC0 PIN 16 BIT COUNTER LOGIC PR 2 1 0 TC0 16 BIT COMPARATOR TCNT hi TCNT lo CHANNEL 1 TC1 16 BIT COMPARATOR INTERRUPT LOGIC TOF TOI C0F C1F EDGE DETECT IOC1 PIN LOGIC EDGE DETECT CxF CHANNELn 1 TCn 1 16 BIT COMPARATOR Cn 1F IOCn 1 PIN LOGIC EDGE DETECT OM OL0 TOV0 OM OL1 TOV1 OM OL7 T...

Page 401: ...periodic pulse with a programmable polarity duration and frequency When the timer counter reaches the value in the channel registers of an output compare channel the timer can set clear or toggle the channel pin if the corresponding OCPDx bit is set to zero An output compare on channel x sets the CxF flag The CxI bit enables the CxF flag to generate interrupt requests Timer module must stay enable...

Page 402: ...erated by the TIM16B4CV3 to communicate with the MCU The TIM16B4CV3 could use up to 5 interrupt vectors The interrupt vector offsets and interrupt numbers are chip dependent 11 6 1 Channel 3 0 Interrupt C 3 0 F This active high outputs will be asserted by the module to request a timer channel 7 0 interrupt The TIM block only generates the interrupt and does not service it Only bits related to impl...

Page 403: ...oncepts contained within this document Though not exclusively intended for automotive applications CAN protocol is designed to meet the specific requirements of a vehicle serial data bus real time processing reliable operation in the EMI environment of a vehicle cost effectiveness and required bandwidth MSCAN uses an advanced buffer arrangement resulting in predictable real time behavior and simpl...

Page 404: ...n First Out Memory IFS Inter Frame Sequence SOF Start of Frame CPU bus CPU related read write data bus CAN bus CAN protocol related serial bus oscillator clock Direct clock from external oscillator bus clock CPU bus related clock CAN clock CAN protocol related clock RXCAN TXCAN Receive Transmit Engine Message Filtering and Buffering Control and Status Wake Up Interrupt Req Errors Interrupt Req Rec...

Page 405: ...ers Programmable wake up functionality with integrated low pass filter Programmable loopback mode supports self test operation Programmable listen only mode for monitoring of CAN bus Programmable bus off recovery functionality Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states warning error passive bus off Programmable MSCAN clock source either bus clo...

Page 406: ...in RXCAN is the MSCAN receiver input pin 12 2 2 TXCAN CAN Transmitter Output Pin TXCAN is the MSCAN transmitter output pin The TXCAN output pin represents the logic level on the CAN bus 0 Dominant state 1 Recessive state 12 2 3 CAN System A typical CAN system with MSCAN is shown in Figure 12 2 Each CAN station is connected physically to the CAN bus lines through a transceiver device The transceive...

Page 407: ... MSCAN memory map The register address results from the addition of base address and address offset The base address is determined at the MCU level and can be found in the MCU memory map description The address offset is defined at the module level The MSCAN occupies 64 bytes in the memory space The base address of the MSCAN module is determined at the MCU level when the MCU is defined The registe...

Page 408: ...04 CANRFLG R WUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF W 0x0005 CANRIER R WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE W 0x0006 CANTFLG R 0 0 0 0 0 TXE2 TXE1 TXE0 W 0x0007 CANTIER R 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 W 0x0008 CANTARQ R 0 0 0 0 0 ABTRQ2 ABTRQ1 ABTRQ0 W 0x0009 CANTAAK R 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 W 0x000A CANTBSEL R 0 0 0 0 0 TX2 TX1 TX0 W 0x000B CANIDAC R 0 0 IDA...

Page 409: ...its of the MSCAN module as described below 0x000F CANTXERR R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 W 0x0010 0x0013 CANIDAR0 3 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W 0x0014 0x0017 CANIDMRx R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x0018 0x001B CANIDAR4 7 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W 0x001C 0x001F CANIDMR4 7 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x0020 0x002F CANRXFG R See Section 12 ...

Page 410: ...Stops in Wait Mode Enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the CPU bus interface to the MSCAN module 0 The module is not affected during wait mode 1 The module ceases to be clocked during wait mode 4 SYNCH Synchronized Status This read only flag indicates whether the MSCAN is synchronized to the CAN bus and able to participate in the communi...

Page 411: ...in initialization mode INITRQ 1 and INITAK 1 The values of the error counters are not affected by initialization mode When this bit is cleared by the CPU the MSCAN restarts and then tries to synchronize to the CAN bus If the MSCAN is not in bus off state it synchronizes after 11 consecutive recessive bits on the CAN bus if the MSCAN is in bus off state it continues to wait for 128 occurrences of 1...

Page 412: ...he MSCAN behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node In this state the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message Both transmit and receive interrupts are generated 0 Loopback self test disabled 1 Loopback self test enabled 4 LISTEN ...

Page 413: ...nd INITAK 1 The registers CANCTL1 CANBTR0 CANBTR1 CANIDAC CANIDAR0 CANIDAR7 and CANIDMR0 CANIDMR7 can be written only by the CPU when the MSCAN is in initialization mode 0 Running The MSCAN operates normally 1 Initialization mode active The MSCAN has entered initialization mode Module Base 0x0002 Access User read write 1 1 Read Anytime Write Anytime in initialization mode INITRQ 1 and INITAK 1 7 6...

Page 414: ...on 7 SAMP Sampling This bit determines the number of CAN bus samples taken per bit time 0 One sample per bit 1 Three samples per bit 1 If SAMP 0 the resulting bit value is equal to the value of the single bit positioned at the sample point If SAMP 1 the resulting bit value is determined by using majority rule on the three total samples For higher bit rates it is recommended that only one sample is...

Page 415: ...longer valid Every flag has an associated interrupt enable bit in the CANRIER register Table 12 8 Time Segment 2 Values TSEG22 TSEG21 TSEG20 Time Segment 2 0 0 0 1 Tq clock cycle 1 1 This setting is not valid Please refer to Table 12 36 for valid settings 0 0 1 2 Tq clock cycles 1 1 0 7 Tq clock cycles 1 1 1 8 Tq clock cycles Table 12 9 Time Segment 1 Values TSEG13 TSEG12 TSEG11 TSEG10 Time segmen...

Page 416: ...nd requested wake up 6 CSCIF CAN Status Change Interrupt Flag This flag is set when the MSCAN changes its current CAN bus status due to the actual value of the transmit error counter TEC and the receive error counter REC An additional 4 bit RSTAT 1 0 TSTAT 1 0 status register which is split into separate sections for TEC REC informs the system on the actual CAN bus status see Section 12 3 2 6 MSCA...

Page 417: ...e is shifted in the receiver FIFO This flag indicates whether the shifted buffer is loaded with a correctly received message matching identifier matching cyclic redundancy code CRC and no other errors detected After the CPU has read that message from the RxFG buffer in the receiver FIFO the RXF flag must be cleared to release the buffer A set RXF flag prohibits the shifting of the next FIFO entry ...

Page 418: ...off 2 state Discard other receiver state changes for generating CSCIF interrupt 11 Generate CSCIF interrupt on all state changes 2 Bus off state is only defined for transmitters by the CAN standard see Bosch CAN 2 0A B protocol specification Because the only possible state change for the transmitter from bus off to TxOK also forces the receiver to skip its current state to RxOK the coding of the R...

Page 419: ...for transmission The CPU must clear the flag after a message is set up in the transmit buffer and is due for transmission The MSCAN sets the flag after the message is sent successfully The flag is also set by the MSCAN when the transmission request is successfully aborted due to a pending abort request see Section 12 3 2 9 MSCAN Transmitter Message Abort Request Register CANTARQ If not masked a tr...

Page 420: ...lization mode INITRQ 0 and INITAK 0 Module Base 0x0007 Access User read write 1 1 Read Anytime Write Anytime when not in initialization mode 7 6 5 4 3 2 1 0 R 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 12 11 MSCAN Transmitter Interrupt Enable Register CANTIER Table 12 13 CANTIER Register Field Descriptions Field Description 2 0 TXEIE 2 0 Transmitter Empty Interrupt...

Page 421: ...ost arbitration or error When a message is aborted the associated TXE see Section 12 3 2 7 MSCAN Transmitter Flag Register CANTFLG and abort acknowledge flags ABTAK see Section 12 3 2 10 MSCAN Transmitter Message Abort Acknowledge Register CANTAAK are set and a transmit interrupt occurs if enabled The CPU cannot reset ABTRQx ABTRQx is reset whenever the associated TXE flag is set 0 No abort reques...

Page 422: ... is 0b0000_0110 STAA CANTBSEL value written is 0b0000_0110 LDAA CANTBSEL value read is 0b0000_0010 If all transmit message buffers are deselected no accesses are allowed to the CANTXFG registers 12 3 2 12 MSCAN Identifier Acceptance Control Register CANIDAC The CANIDAC register is used for identifier acceptance control as described below Module Base 0x000A Access User read write 1 1 Read Find the ...

Page 423: ...tance Mode The CPU sets these flags to define the identifier acceptance filter organization see Section 12 4 3 Identifier Acceptance Filter Table 12 18 summarizes the different settings In filter closed mode no message is accepted such that the foreground buffer is never reloaded 2 0 IDHIT 2 0 Identifier Acceptance Hit Indicator The MSCAN sets these flags to indicate an identifier acceptance hit s...

Page 424: ...12 3 2 14 MSCAN Miscellaneous Register CANMISC This register provides additional features Module Base 0x000C Access User read write 1 1 Read Always reads zero in normal system operation modes Write Unimplemented in normal system operation modes 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 12 16 MSCAN Reserved Register Module Base 0x000D Access User read write 1 1 ...

Page 425: ...ff State Hold Until User Request If BORM is set in MSCAN Control Register 1 CANCTL1 this bit indicates whether the module has entered the bus off state Clearing this bit requests the recovery from bus off Refer to Section 12 5 2 Bus Off Recovery for details 0 Module is not bus off or recovery has been requested by user in bus off state 1 Module is bus off and holds this state until user request Mo...

Page 426: ...eptance registers of the MSCAN are applied on the IDR0 IDR3 registers see Section 12 3 3 1 Identifier Registers IDR0 IDR3 of incoming messages in a bit by bit manner see Section 12 4 3 Identifier Acceptance Filter For extended identifiers all four acceptance and mask registers are applied For standard identifiers only the first two CANIDAR0 1 CANIDMR0 1 are applied Module Base 0x000F Access User r...

Page 427: ...rresponding bits of the related identifier register IDRn of the receive message buffer are compared The result of this comparison is then masked with the corresponding identifier mask register Module Base 0x0018 to Module Base 0x001B Access User read write 1 1 Read Anytime Write Anytime in initialization mode INITRQ 1 and INITAK 1 7 6 5 4 3 2 1 0 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W Reset 0 0 0 0 0...

Page 428: ...the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected The message is accepted if all such bits match If a bit is set it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted 0 Match corresponding acceptance code register and identifier bit...

Page 429: ...essage Buffer Organization Offset Address Register Access 0x00X0 IDR0 Identifier Register 0 R W 0x00X1 IDR1 Identifier Register 1 R W 0x00X2 IDR2 Identifier Register 2 R W 0x00X3 IDR3 Identifier Register 3 R W 0x00X4 DSR0 Data Segment Register 0 R W 0x00X5 DSR1 Data Segment Register 1 R W 0x00X6 DSR2 Data Segment Register 2 R W 0x00X7 DSR3 Data Segment Register 3 R W 0x00X8 DSR4 Data Segment Regis...

Page 430: ...DE 1 ID17 ID16 ID15 W 0x00X2 IDR2 R ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 W 0x00X3 IDR3 R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR W 0x00X4 DSR0 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X5 DSR1 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X6 DSR2 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X7 DSR3 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X8 DSR4 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X9 DSR5 R DB7 DB6 DB5 DB4 DB3 DB2...

Page 431: ... buffer is selected in CANTBSEL see Section 12 3 2 11 MSCAN Transmit Buffer Selection Register CANTBSEL Unimplemented for receive buffers Reset Undefined because of RAM based implementation 12 3 3 1 Identifier Registers IDR0 IDR3 The identifier registers for an extended format identifier consist of a total of 32 bits ID 28 0 SRR IDE and RTR The identifier registers for a standard format identifier...

Page 432: ... Extended Format Identifier The identifiers consist of 29 bits ID 28 0 for the extended format ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure The priority of an identifier is defined to be highest for the smallest binary number 4 SRR Substitute Remote Request This fixed recessive bit is used only in extended format It must be set to 1 by t...

Page 433: ...3 7 6 5 4 3 2 1 0 R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR W Reset x x x x x x x x Figure 12 29 Identifier Register 3 IDR3 Extended Identifier Mapping Table 12 29 IDR3 Register Field Descriptions Extended Field Description 7 1 ID 6 0 Extended Format Identifier The identifiers consist of 29 bits ID 28 0 for the extended format ID28 is the most significant bit and is transmitted first on the CAN bus during...

Page 434: ...scriptions Field Description 7 5 ID 2 0 Standard Format Identifier The identifiers consist of 11 bits ID 10 0 for the standard format ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure The priority of an identifier is defined to be highest for the smallest binary number See also ID bits in Table 12 30 4 RTR Remote Transmission Request This fla...

Page 435: ...orresponding DLR register Module Base 0x00X2 7 6 5 4 3 2 1 0 R W Reset x x x x x x x x Unused always read x Figure 12 32 Identifier Register 2 Standard Mapping Module Base 0x00X3 7 6 5 4 3 2 1 0 R W Reset x x x x x x x x Unused always read x Figure 12 33 Identifier Register 3 Standard Mapping Module Base 0x00X4 to Module Base 0x00XB 7 6 5 4 3 2 1 0 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W Reset x x x x...

Page 436: ...zation immediately before the SOF start of frame is sent Module Base 0x00XC 7 6 5 4 3 2 1 0 R DLC3 DLC2 DLC1 DLC0 W Reset x x x x x x x x Unused always read x Figure 12 35 Data Length Register DLR Extended Identifier Mapping Table 12 33 DLR Register Field Descriptions Field Description 3 0 DLC 3 0 Data Length Code Bits The data length code contains the number of bytes data byte count of the respec...

Page 437: ...he time stamp registers Module Base 0x00XD Access User read write 1 1 Read Anytime when TXEx flag is set see Section 12 3 2 7 MSCAN Transmitter Flag Register CANTFLG and the corresponding transmit buffer is selected in CANTBSEL see Section 12 3 2 11 MSCAN Transmit Buffer Selection Register CANTBSEL Write Anytime when TXEx flag is set see Section 12 3 2 7 MSCAN Transmitter Flag Register CANTFLG and...

Page 438: ...ime when TXEx flag is set see Section 12 3 2 7 MSCAN Transmitter Flag Register CANTFLG and the corresponding transmit buffer is selected in CANTBSEL see Section 12 3 2 11 MSCAN Transmit Buffer Selection Register CANTBSEL For receive buffers Anytime when RXF is set Write Unimplemented 7 6 5 4 3 2 1 0 R TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 W Reset x x x x x x x x Figure 12 38 Time Stamp Register ...

Page 439: ...cription 12 4 1 General This section provides a complete functional description of the MSCAN 12 4 2 Message Storage Figure 12 39 User Model for Message Buffer Organization MSCAN Rx0 Rx1 CAN Receive Transmit Engine Memory Mapped I O CPU bus MSCAN Tx2 TXE2 PRIO Receiver Transmitter RxBG TxBG Tx0 TXE0 PRIO TxBG Tx1 PRIO TXE1 TxFG CPU bus Rx2 Rx3 Rx4 RXF RxFG ...

Page 440: ...cond buffer No buffer would then be ready for transmission and the CAN bus would be released At least three transmit buffers are required to meet the first of the above requirements under all circumstances The MSCAN has three transmit buffers The second requirement calls for some sort of internal prioritization which the MSCAN implements with the local priority concept described in Section 12 4 2 ...

Page 441: ...s that are already in transmission cannot be aborted the user must request the abort by setting the corresponding abort request bit ABTRQ see Section 12 3 2 9 MSCAN Transmitter Message Abort Request Register CANTARQ The MSCAN then grants the request if possible by 1 Setting the corresponding abort acknowledge flag ABTAK in the CANTAAK register 2 Setting the associated TXE flag to release the buffe...

Page 442: ...ble to transmit messages while the receiver FIFO is being filled but all incoming messages are discarded As soon as a receive buffer in the FIFO is available again new valid messages will be accepted 12 4 3 Identifier Acceptance Filter The MSCAN identifier acceptance registers see Section 12 3 2 12 MSCAN Identifier Acceptance Control Register CANIDAC define the acceptable patterns of the standard ...

Page 443: ...es filter 2 and 3 hits Eight identifier acceptance filters each to be applied to the first 8 bits of the identifier This mode implements eight independent filters for the first 8 bits of a CAN 2 0A B compliant standard identifier or a CAN 2 0B compliant extended identifier Figure 12 42 shows how the first 32 bit filter bank CANIDAR0 CANIDAR3 CANIDMR0 CANIDMR3 produces filter 0 to 3 hits Similarly ...

Page 444: ... Acceptance Filters ID28 ID21 IDR0 ID10 ID3 IDR0 ID20 ID15 IDR1 ID2 IDE IDR1 ID14 ID7 IDR2 ID10 ID3 IDR2 ID6 RTR IDR3 ID10 ID3 IDR3 AC7 AC0 CANIDAR0 AM7 AM0 CANIDMR0 AC7 AC0 CANIDAR1 AM7 AM0 CANIDMR1 ID Accepted Filter 0 Hit AC7 AC0 CANIDAR2 AM7 AM0 CANIDMR2 AC7 AC0 CANIDAR3 AM7 AM0 CANIDMR3 ID Accepted Filter 1 Hit CAN 2 0B Extended Identifier CAN 2 0A B Standard Identifier ...

Page 445: ...rs CAN 2 0B Extended Identifier CAN 2 0A B Standard Identifier AC7 AC0 CIDAR3 AM7 AM0 CIDMR3 ID Accepted Filter 3 Hit AC7 AC0 CIDAR2 AM7 AM0 CIDMR2 ID Accepted Filter 2 Hit AC7 AC0 CIDAR1 AM7 AM0 CIDMR1 ID Accepted Filter 1 Hit ID28 ID21 IDR0 ID10 ID3 IDR0 ID20 ID15 IDR1 ID2 IDE IDR1 ID14 ID7 IDR2 ID10 ID3 IDR2 ID6 RTR IDR3 ID10 ID3 IDR3 AC7 AC0 CIDAR0 AM7 AM0 CIDMR0 ID Accepted Filter 0 Hit ...

Page 446: ...IDMR7 The TXCAN is immediately forced to a recessive state when the MSCAN goes into the power down mode or initialization mode see Section 12 4 5 6 MSCAN Power Down Mode and Section 12 4 4 5 MSCAN Initialization Mode The MSCAN enable bit CANE is writable only once in normal system operation modes which provides further protection against inadvertently disabling the MSCAN 12 4 3 2 Clock System Figu...

Page 447: ... This segment has a fixed length of one time quantum Signal edges are expected to happen within this section Time Segment 1 This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta Time Segment 2 This segment represents the PHASE_SEG2 of the CAN standard It can be programmed by setting the TSEG2 ...

Page 448: ...in compliance with the CAN standard 12 4 4 Modes of Operation 12 4 4 1 Normal System Operating Modes The MSCAN module behaves as described within this specification in all normal system operating modes Write restrictions exist for some registers Table 12 35 Time Segment Syntax Syntax Description SYNC_SEG System expects transitions to occur on the CAN bus during this period Transmit Point A node in...

Page 449: ... 5 MSCAN Initialization Mode The MSCAN enters initialization mode when it is enabled CANE 1 When entering initialization mode during operation any on going transmission or reception is immediately aborted and synchronization to the CAN bus is lost potentially causing CAN protocol violations To protect the CAN bus system from fatal consequences of violations the MSCAN immediately drives TXCAN into ...

Page 450: ...ation for the request INITRQ to go into initialization mode NOTE The CPU cannot clear INITRQ before initialization mode INITRQ 1 and INITAK 1 is active 12 4 5 Low Power Options If the MSCAN is disabled CANE 0 the MSCAN clocks are stopped for power saving If the MSCAN is enabled CANE 1 the MSCAN has two additional modes with reduced power consumption compared to normal mode sleep and power down mod...

Page 451: ...a background debug mode 12 4 5 3 Operation in Stop Mode The STOP instruction puts the MCU in a low power consumption stand by mode In stop mode the MSCAN is set in power down mode regardless of the value of the SLPRQ SLPAK and CSWAI bits Table 12 37 12 4 5 4 MSCAN Normal Mode This is a non power saving mode Enabling the MSCAN puts the module from disabled mode into normal mode In this mode the mod...

Page 452: ...ing one or more TXEx flag s and immediately request sleep mode by setting SLPRQ Whether the MSCAN starts transmitting or goes into sleep mode directly depends on the exact sequence of operations If sleep mode is active the SLPRQ and SLPAK bits are set Figure 12 46 The application software must use SLPAK as a handshake indication for the request SLPRQ to go into sleep mode When in sleep mode SLPRQ ...

Page 453: ... If the MSCAN remains in bus off state after sleep mode was exited it continues counting the 128 occurrences of 11 consecutive recessive bits 12 4 5 6 MSCAN Power Down Mode The MSCAN is in power down mode Table 12 37 when CPU is in stop mode or CPU is in wait mode and the CSWAI bit is set When entering the power down mode the MSCAN immediately stops all ongoing transmissions and receptions potenti...

Page 454: ...of each individual bit is listed in Section 12 3 2 Register Descriptions which details all the registers and their bit fields 12 4 7 Interrupts This section describes all interrupts originated by the MSCAN It documents the enable bits and generated flags Each interrupt is listed and described separately 12 4 7 1 Description of Interrupt Operation The MSCAN supports four interrupt vectors see Table...

Page 455: ...4 2 3 Receive Structures occurred CAN Status Change The actual value of the transmit and receive error counters control the CAN bus state of the MSCAN As soon as the error counters skip into a critical range Tx Rx warning Tx Rx error bus off the MSCAN flags an error condition The status change which caused the error condition is indicated by the TSTAT and RSTAT flags see Section 12 3 2 5 MSCAN Rec...

Page 456: ... the configuration registers in initialization mode 4 Clear INITRQ to leave initialization mode and continue 12 5 2 Bus Off Recovery The bus off recovery is user configurable The bus off state can either be left automatically or on user request For reasons of backwards compatibility the MSCAN defaults to automatic recovery after reset In this case the MSCAN will become error active again after cou...

Page 457: ... to where the actual acquisitions are to be made 13 1 1 Features The PTU module includes these distinctive features One 16 bit counter as time base for all trigger events Two independent trigger generators TG0 and TG1 Up to 32 trigger events per trigger generator Global Load OK support to guarantee coherent update of all control loop modules Table 13 1 Revision History Table Rev No Item No Data Se...

Page 458: ...ugging 13 1 2 Modes of Operation The PTU module behaves as follows in the system power modes 1 Run mode All PTU features are available 2 Wait mode All PTU features are available 3 Freeze Mode Depends on the PTUFRZ register bit setting the internal counter is stopped and no trigger events will be generated 4 Stop mode The PTU is disabled and the internal counter is stopped no trigger events will be...

Page 459: ...ll external ports 13 2 1 PTUT0 PTU Trigger 0 If enabled PTUT0PE is set this pin shows the internal trigger_0 event 13 2 2 PTUT1 PTU Trigger 1 If enabled PTUT1PE is set this pin shows the internal trigger_1 event Trigger Generator TG0 Trigger Generator TG1 Time Base Bus Clock Global Memory Map PTU Module A PTUT0 PTURE PTUT1 Trigger 1 Trigger 2 Trigger n Trigger 1 Trigger 2 Trigger n Counter Control...

Page 460: ...e Address Address Offset where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 PTUE R 0 PTUFRZ 0 0 0 0 TG1EN TG0EN W 0x0001 PTUC R 0 0 0 0 0 0 0 PTULDOK W 0x0002 PTUIEH R 0 0 0 0 0 0 0 PTUROIE W 0x0003 PTUIEL R TG1AEIE TG1REIE TG1TEIE TG1DIE TG0AEIE TG0REIE TG0TEIE TG0DIE W 0x0004 ...

Page 461: ...D TG1TVL R TG1TV 7 0 W 0x000E PTUCNTH R PTUCNT 15 8 W 0x000F PTUCNTL R PTUCNT 7 0 W 0x0010 Reserved R 0 0 0 0 0 0 0 0 W 0x0011 PTUPTRH R PTUPTR 23 16 W 0x0012 PTUPTRM R PTUPTR 15 8 W 0x0013 PTUPTRL R PTUPTR 7 1 0 W 0x0014 TG0L0IDX R 0 TG0L10DX 6 0 W 0x0015 TG0L1IDX R 0 TG0L1IDX 6 0 W 0x0016 TG1L0IDX R 0 TG1L0IDX 6 0 W 0x0017 TG1L1IDX R 0 TG1L1IDX 6 0 W Address Offset Register Name Bit 7 6 5 4 3 2 ...

Page 462: ... description includes a standard register diagram with an associated figure number Details of register bit and field function follow the register diagrams in bit order Unused bits read back zero 0x0018 0x001E Reserved R 0 0 0 0 0 0 0 0 W 0x001F PTUDEBUG R 0 PTUREPE PTUT1PE PTUT0PE 0 0 0 0 W PTUFRE TG1FTE TG0FTE Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 Unimplemented Figure 13 2 PTU Regi...

Page 463: ...e the input clock to the time base counter is disabled In this way the counters can be stopped while in freeze mode so that once normal program flow is continued the counter is re enabled 0 Allow time base counter to continue while in freeze mode 1 Disable time base counter clock whenever the part is in freeze mode 1 TG1EN Trigger Generator 1 Enable This bit enables trigger generator 1 0 Trigger g...

Page 464: ... generator to switch to the alternative list and load the trigger time values at the next reload event from the new list If the reload event occurs when the PTULDOK bit is not set then the trigger generator generates a reload overrun event and uses the previously used list At the next reload event this bit is cleared by control logic Write 0 is only possible if TG0EN and TG1EN is cleared The PTULD...

Page 465: ... set 1 Interrupt will be requested whenever PTUROIF is set Module Base 0x0003 Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R TG1AEIE TG1REIE TG1TEIE TG1DIE TG0AEIE TG0REIE TG0TEIE TG0DIE W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 13 6 PTU Interrupt Enable Register Low PTUIEL Table 13 6 PTUIEL Register Field Descriptions Field Description 7 TG1AEIE Trigger Generator 1 Mem...

Page 466: ...ccess error interrupt 0 No interrupt will be requested whenever TG0AEIF is set 1 Interrupt will be requested whenever TG0AEIF is set 2 TG0REIE Trigger Generator 0 Reload Error Interrupt Enable Enables trigger generator reload error interrupt 0 No interrupt will be requested whenever TG0REIF is set 1 Interrupt will be requested whenever TG0REIF is set 1 TG0TEIE Trigger Generator 0 Timing Error Inte...

Page 467: ...This bit is set if the read data from the memory contains double bit ECC errors While this bit is set the trigger generation of both trigger generators stops 0 No double bit ECC error occurs 1 Double bit ECC error occurs 0 PTUROIF PTU Reload Overrun Interrupt Flag If reload event occurs when the PTULDOK bit is not set then this bit will be set This bit is not set if the reload event was forced by ...

Page 468: ...s set if the trigger generator receives the end of list symbol or the maximum number of generated trigger events was reached 0 Trigger generator 1 is running 1 Trigger generator 1 is done 3 TG0AEIF Trigger Generator 0 Memory Access Error Interrupt Flag This bit is set if trigger generator 0 uses a read address outside the memory address range see the MMC section for the supported memory area 0 No ...

Page 469: ... Description 0 TG0LIST Trigger Generator 0 List This bit shows the number of the current used list 0 Trigger generator 0 is using list 0 1 Trigger generator 0 is using list 1 Module Base 0x0007 Access User read only 1 1 Read Anytime Write Never 7 6 5 4 3 2 1 0 R 0 0 0 TG0TNUM 4 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 13 10 Trigger Generator 0 Trigger Number Register TG0TNUM Table 13 10 TG0T...

Page 470: ... 13 11 TG0TV Register Field Descriptions Field Description TG0TV 15 0 Trigger Generator 0 Trigger Value This register contains the trigger value to generate the next trigger If the time base counter reach this value the next trigger event is generated If the trigger generator reached the end of list EOL symbol then this value is visible inside this register If the last generated trigger was trigge...

Page 471: ... Manual Rev 1 3 Freescale Semiconductor 471 Table 13 12 TG1LIST Register Field Descriptions Field Description 0 TG1LIST Trigger Generator 1 List This bit shows the number of the current used list 0 Trigger generator 1 is using list 0 1 Trigger generator 1 is using list 1 ...

Page 472: ...r TG1TNUM Table 13 13 TG1TNUM Register Field Descriptions Field Description 4 0 TG1TNUM 4 0 Trigger Generator 1 Trigger Number This register shows the number of generated triggers since the last reload event After the generation of 32 triggers this register shows zero The next reload event clears this register See also Figure 13 22 Module Base 0x000C Access User read only 1 1 Read Anytime Write Ne...

Page 473: ...ger Value This register contains the currently used trigger value to generate the next trigger If the time base counter reach this value the next trigger event is generated If the trigger generator reached the end of list EOL symbol then this value is visible inside this register If the last generated trigger was trigger number 32 then the last used trigger value is visible inside this register Se...

Page 474: ... 0 0 Module Base 0x000F Access User read only 7 6 5 4 3 2 1 0 R PTUCNT 7 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 13 15 PTU Counter Register PTUCNTH PTUCNTL Table 13 15 PTUCNT Register Field Descriptions Field Description PTUCNT 15 0 PTU Time Base Counter value This register contains the current status of the internal time base counter If both TG are done with the execution of the trigger li...

Page 475: ...ss User read write 7 6 5 4 3 2 1 0 R PTUPTR 15 8 W Reset 0 0 0 0 0 0 0 0 Module Base 0x0013 Access User read write 7 6 5 4 3 2 1 0 R PTUPTR 7 1 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 13 16 PTU List Add Register PTUPTRH PTUPTRM PTUPTRL Table 13 16 PTUPTR Register Field Descriptions Field Description PTUPTR 23 0 PTU Pointer This register cannot be modified if TG0EN or TG1EN bit is set This r...

Page 476: ...ger event list 0 used by trigger generator 0 This register is read only so the list 0 for trigger generator 0 will start at the PTUPTR address For more information see Section 13 4 2 Memory based trigger event list Module Base 0x0015 Access User read write 1 1 Read Anytime Write Anytime if TG0EN bit is cleared 7 6 5 4 3 2 1 0 R 0 TG0L1IDX 6 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 13 18 Trig...

Page 477: ... after the TG1EN bit is set This register defines offset of the start point for the trigger event list 0 used by trigger generator 1 For more information see Section 13 4 2 Memory based trigger event list Module Base 0x0017 Access User read write 1 1 Read Anytime Write Anytime if TG1EN bit is cleared 7 6 5 4 3 2 1 0 R 0 TG1L1IDX 6 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 13 20 Trigger Genera...

Page 478: ...t port for pin PTUT1 0 PTUT1 output port are disabled 1 PTUT1 output port are enabled 4 PTUT0PE PTU PTUT0 Pin Enable This bit enables the output port for pin PTUT0 0 PTUT0 output port are disabled 1 PTUT0 output port are enabled 2 PTUFRE Force Reload event generation If one of the TGs is enabled then writing 1 to this bit will generate a reload event The reload event forced by PTUFRE does not set ...

Page 479: ...lue is loaded from the memory and the TG waits for the next match So up to 32 trigger events per control cycle can be generated If the trigger value is 0x0000 or 32 trigger events have been generated during this control cycle the TGxDIF bit is set and the TG waits for the next reload event Figure 13 22 shows an example of the trigger generation using the trigger values shown in Figure 13 23 Figure...

Page 480: ...lue is smaller than the previous value or the loaded trigger value is smaller than the current counter value then the TGxTEIF error indication is generated and the trigger generation of this list is stopped until the next reload event For more information about these error scenario see Section 13 4 5 5 Trigger Generator Timing Error The module is not able to access memory area outside the 256 byte...

Page 481: ...an example The PTULDOK bit can be used by other modules as glb_ldok To reduce the used memory size it is also possible to set TG0L0IDX equal to TG0L1IDX or to set TG1L0IDX equal to TG1L1IDX In this case the trigger generator is using only one physical list of trigger events even if the trigger generator logic is switching between both pointers The SW must make sure that the CPU does not update the...

Page 482: ...U Reload Overrun Error If the PTULDOK bit is not set during the reload event then the PTUROIF bit is set If enabled PTUROIE is set an interrupt is generated For more information see Section 13 4 3 Reload mechanism During an async reload event the PTUROIF interrupt flag is not set 13 4 5 3 Trigger Generator Memory Access Error The trigger generator memory access error flag TGxAEIF is set if the use...

Page 483: ...gger generator timing error flag TGxTEIF is not set If enabled TGxEIE is set an interrupt will be generated 13 4 5 6 Trigger Generator Done The trigger generator done flag TGxDIF is set if the loaded trigger value contains 0x0000 or if the number of maximum trigger events 32 was reached Please note that the time which is required to load the next trigger value defines the delay between the generat...

Page 484: ...Chapter 13 Programmable Trigger Unit PTUV2 MC9S12ZVM Family Reference Manual Rev 1 3 484 Freescale Semiconductor ...

Page 485: ...on Updated note to QSMP table Updated Asymmetric PWM output description Replaced fault clearing with fault recovery to avoid ambiguity with flags Various minor corrections V03 25 03 Dec 2013 14 3 2 18 14 509 Updated note at PMFCINV register Table 14 2 Glossary of Terms Term Definition Set Discrete signal is in active logic state Clear A discrete signal is in inactive logic state Pin External physi...

Page 486: ...s AC induction motors ACIM both brushless BLDC and brush DC motors BDC switched SRM and variable reluctance motors VRM and stepper motors 14 1 1 Features Three complementary PWM signal pairs or six independent PWM signals Edge aligned or center aligned mode Features of complementary channel operation Deadtime insertion Separate top and bottom pulse width correction via current status inputs or sof...

Page 487: ...utput polarity control Software controlled PWM outputs complementary or independent 14 1 2 Modes of Operation Care must be exercised when using this module in the modes listed in Table 14 3 Some applications require regular software updates for proper operation Failure to do so could result in destroying the hardware setup Because of this PWM outputs are placed in their inactive states in STOP mod...

Page 488: ...TER PMFFEN FIF2 FIF1 FIF3 LDFQ OUTCTL2 OUTCTL4 OUTCTL1 OUT1 OUT3 OUT5 OUTCTL3 OUTCTL5 HALF PWMRF INDEP TOPNEG BOTNEG TOP BOTTOM GENERATION IPOL DT 0 5 6 IS0 IS1 IS2 MULTIPLE REGISTERS OR BITS FOR TIMEBASE A B OR C A B C MTG RELOAD B INTERRUPT REQUEST RELOAD C INTERRUPT REQUEST QSMP0 QSMP2 QSMP1 QSMP3 DEADTIME INSERTION PRSC RSTRT Reset Single underline denotes buffered registers taking effect at P...

Page 489: ...gate drive unit GDU either one or more FAULT inputs may be connected internally or and available on an external pin Refer to the device overview section for availability and pin locations 14 2 3 IS0 IS2 Pins IS0 IS2 are current status signals for top bottom pulse width correction in complementary channel operation while deadtime is asserted NOTE Refer to the device overview section for signal avai...

Page 490: ... b c These device internal PMF output signals assert once per control cycle and can serve as triggers for other implemented IP modules Signal pmf_reloadb and pmf_reloadc are related to time base B and C respectively while signal pmf_reloada is off out of reset and can be programmed for time base A B or C Refer to the device overview section to determine the signal connections 14 2 8 PWM Reload Is ...

Page 491: ...dress Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 PMFCFG0 R WP MTG EDGEC EDGEB EDGEA INDEPC INDEPB INDEPA W 0x0001 PMFCFG1 R 0 ENCE BOTNEGC TOPNEGC BOTNEGB TOPNEGB BOTNEGA TOPNEGA W 0x0002 PMFCFG2 R REV1 REV0 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 W 0x0003 PMFCFG3 R PMFWAI PMFFRZ 0 VLMODE PINVC PINVB PINVA W 0x0004 PMFFEN R 0 FEN5 0 FEN4 FEN3 FEN2 FEN1 FEN0 W 0x0005 PMFFMOD R 0 FMOD5 0 FMOD4 FMOD3 ...

Page 492: ...T2 DT1 DT0 W 0x000F PMFCCTL R 0 0 ISENS 0 IPOLC IPOLB IPOLA W 0x0010 PMFVAL0 R PMFVAL0 W 0x0011 PMFVAL0 R PMFVAL0 W 0x0012 PMFVAL1 R PMFVAL1 W 0x0013 PMFVAL1 R PMFVAL1 W 0x0014 PMFVAL2 R PMFVAL2 W 0x0015 PMFVAL2 R PMFVAL2 W 0x0016 PMFVAL3 R PMFVAL3 W 0x0017 PMFVAL3 R PMFVAL3 W 0x0018 PMFVAL4 R PMFVAL4 W 0x0019 PMFVAL4 R PMFVAL4 W 0x001A PMFVAL5 R PMFVAL5 W Address Offset Register Name Bit 7 6 5 4 ...

Page 493: ... CINV5 CINV4 CINV3 CINV2 CINV1 CINV0 W 0x0020 PMFENCA R PWMENA GLDOKA 0 0 0 RSTRTA LDOKA PWMRIEA W 0x0021 PMFFQCA R LDFQA HALFA PRSCA PWMRFA W 0x0022 PMFCNTA R 0 PMFCNTA W 0x0023 PMFCNTA R PMFCNTA W 0x0024 PMFMODA R 0 PMFMODA W 0x0025 PMFMODA R PMFMODA W 0x0026 PMFDTMA R 0 0 0 0 PMFDTMA W 0x0027 PMFDTMA R PMFDTMA W 0x0028 PMFENCB R PWMENB GLDOKB 0 0 0 RSTRTB LDOKB PWMRIEB W 0x0029 PMFFQCB R LDFQB ...

Page 494: ...FCNTB R PMFCNTB W 0x002C PMFMODB R 0 PMFMODB W 0x002D PMFMODB R PMFMODB W 0x002E PMFDTMB R 0 0 0 0 PMFDTMB W 0x002F PMFDTMB R PMFDTMB W 0x0030 PMFENCC R PWMENC GLDOKC 0 0 0 RSTRTC LDOKC PWMRIEC W 0x0031 PMFFQCC R LDFQC HALFC PRSCC PWMRFC W Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 Unimplemented or Reserved Figure 14 2 Quick Reference to PMF Registers Sheet 4 of 5 ...

Page 495: ...P04 DMP03 DMP02 DMP01 DMP00 W 0x0039 PMFDMP1 R DMP15 DMP14 DMP13 DMP12 DMP11 DMP10 W 0x003A PMFDMP2 R DMP25 DMP24 DMP23 DMP22 DMP21 DMP20 W 0x003B PMFDMP3 R DMP35 DMP34 DMP33 DMP32 DMP31 DMP30 W 0x003C PMFDMP4 R DMP45 DMP44 DMP43 DMP42 DMP41 DMP40 W 0x003D PMFDMP5 R DMP55 DMP54 DMP53 DMP52 DMP51 DMP50 W 0x003E PMFOUTF R 0 0 OUTF5 OUTF4 OUTF3 OUTF2 OUTF1 OUTF0 W 0x003F Reserved R 0 0 0 0 0 0 0 0 W ...

Page 496: ...s EDGEC and EDGEB are ignored Pair A Pair B and Pair C PWMs are synchronized to PWM generator A and use registers from 0x0020 0x0027 0 Single timebase generator 1 Multiple timebase generators 5 EDGEC Edge Aligned or Center Aligned PWM for Pair C This bit determines whether PWM4 and PWM5 channels will use edge aligned or center aligned waveforms This bit has no effect if MTG bit is cleared This bit...

Page 497: ...be independent PWMs or complementary PWMs This bit cannot be modified after the WP bit is set 0 PWM0 and PWM1 are complementary PWM pair 1 PWM0 and PWM1 are independent PWMs Address Module Base 0x0001 Access User read write 1 1 Read Anytime Write This register cannot be modified after the WP bit is set 7 6 5 4 3 2 1 0 R 0 ENCE BOTNEGC TOPNEGC BOTNEGB TOPNEGB BOTNEGA TOPNEGA W Reset 0 0 0 0 0 0 0 0...

Page 498: ...his bit determines the polarity for Pair A bottom side PWM PWM1 This bit cannot be modified after the WP bit is set 0 Positive PWM1 polarity 1 Negative PWM1 polarity 0 TOPNEGA Pair A Top Side PWM Polarity This bit determines the polarity for Pair A top side PWM PWM0 This bit cannot be modified after the WP bit is set 0 Positive PWM0 polarity 1 Negative PWM0 polarity Address Module Base 0x0002 Acce...

Page 499: ...6 PMF Configure 3 Register PMFCFG3 Table 14 8 PMFCFG3 Field Descriptions Field Description 7 PMFWAI PMF Stops While in WAIT Mode When set to zero the PWM generators will continue to run while the chip is in WAIT mode In this mode the peripheral clock continues to run but the CPU clock does not If the device enters WAIT mode and this bit is one then the PWM outputs will be switched to their inactiv...

Page 500: ...MPSRCB signal This bit has no effect in independent mode Note PINVB is buffered The value written does not take effect until the LDOK bit or global load OK is set and the next PWM load cycle begins Reading PINVB returns the value in the buffer and not necessarily the value in use 0 No inversion 1 COMPSRCB inverted only in complementary mode 0 PINVA PWM Invert Complement Source Pair A This bit cont...

Page 501: ...3 3 Manual Fault Recovery for more details 0 Manual fault recovery of FAULTm input faults 1 Automatic fault recovery of FAULTm input faults m is 0 1 2 3 4 and 5 Address Module Base 0x0006 Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R 0 FIE5 0 FIE4 FIE3 FIE2 FIE1 FIE0 W Reset 0 0 0 0 0 0 0 0 Figure 14 9 PMF Fault Interrupt Enable Register PMFFIE Table 14 11 PMFFIE Field De...

Page 502: ...ag remains set The fault protection is enabled when FENm is set even when the PWMs are not enabled therefore a fault will be latched in requiring to be cleared in order to prevent an interrupt 0 No fault on the FAULTm input 1 Fault on the FAULTm input Note Clearing FIFm satisfies pending FIFm CPU interrupt requests m is 0 1 2 3 4 and 5 1 The active input level may be defined or programmable at SoC...

Page 503: ...in two bus cycles 01 5 samples 10 10 samples 11 15 samples Address Module Base 0x000C Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R 0 0 OUTCTL5 OUTCTL4 OUTCTL3 OUTCTL2 OUTCTL1 OUTCTL0 W Reset 0 0 0 0 0 0 0 0 Figure 14 13 PMF Output Control Register PMFOUTC Table 14 15 PMFOUTC Field Descriptions Field Description 5 0 OUTCTL 5 0 OUTCTLn Bits These bits enable software contr...

Page 504: ...illustrated in Table 14 17 Note OUTn is buffered if ENCE is set The value written does not take effect until the next commutation cycle begins Reading OUTn with OUTCTLn 1 returns the value in the buffer and not necessarily the value the output control is currently using n is 0 1 2 3 4 and 5 OUTn Bit Complementary Channel Operation Independent Channel Operation OUT0 1 PWM0 is active 0 PWM0 is inact...

Page 505: ...able 14 20 Note The user must provide current sensing circuitry causing the voltage at the corresponding input to be low for positive current and high for negative current The top PWMs are PWM 0 2 and 4 and the bottom PWMs are PWM 1 3 and 5 Note The ISENS bits are not buffered Changing the current status sensing method can affect the present PWM cycle 2 IPOLC Current Polarity This buffered bit sel...

Page 506: ...urpose input output ports 01 Manual correction 10 Current status sample correction on inputs IS0 IS1 and IS2 during deadtime 2 2 The polarity of the related IS input is latched when both the top and bottom PWMs are off At the 0 and 100 duty cycle boundaries there is no deadtime so no new current value is sensed 11 Current status sample on inputs IS0 IS1 and IS2 3 At the half cycle in center aligne...

Page 507: ...set and the next PWM load cycle begins Reading PMFVALn returns the value in the buffer and not necessarily the value the PWM generator is currently using n is 0 1 2 3 4 and 5 Address Module Base 0x001C Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R 0 0 0 0 0 PMFROIEC PMFROIEB PMFROIEA W Reset 0 0 0 0 0 0 0 0 Figure 14 18 PMF Interrupt Enable Register PMFROIE Table 14 22 PM...

Page 508: ...ther prior to the complementary logic and deadtime insertion Table 14 23 PMFROIF Field Descriptions Field Description 2 PMFROIFC Reload Overrun Interrupt Flag C If a reload event occurs when the LDOKC or global load OK bit is not set then this flag will be set 0 No Reload Overrun C occurred 1 Reload Overrun C occurred 1 PMFROIFB Reload Overrun Interrupt Flag B If a reload event occurs when the LDO...

Page 509: ... Pulse Edge Control This bit controls PWM0 PWM1 pair 0 Normal operation 1 Allow one of PMFVAL0 and PMFVAL1 to activate the PWM pulse and the other to deactivate the pulse 2 ICCC Internal Correction Control This bit controls PWM4 PWM5 pair 0 IPOLC setting determines whether to use the PMFVAL4 or PMFVAL5 register 1 Use PMFVAL4 register when the PWM counter is counting up Use PMFVAL5 register when co...

Page 510: ...put 3 Please see the output operations in Figure 14 42 and Figure 14 43 0 PWM output 3 is high when PMFCNTB PMFCNTA if MTG 1 is less than PMFVAL3 1 PWM output 3 is high when PMFCNTB PMFCNTA if MTG 1 is greater than PMFVAL3 2 CINV2 PWM Compare Invert 2 This bit controls the polarity of PWM compare output 2 Please see the output operations in Figure 14 42 and Figure 14 43 0 PWM output 2 is high when...

Page 511: ...ted at the next commutation event This bit cannot be modified after the WP bit is set 0 No PWM generator A restart at the next commutation event 1 PWM generator A restarts at the next commutation event 1 LDOKA Load Okay A When MTG is clear this bit allows loads of the PRSCA bits the PMFMODA register and the PMFVAL0 5 registers into a set of buffers The buffered prescaler A divisor PWM counter modu...

Page 512: ...currently in effect The PRSCA field takes effect at the beginning of the next PWM cycle and only when the LDOKA bit or global load OK is set 0 PWMRFA PWM Reload Flag A This flag is set at the beginning of every reload cycle regardless of the state of the LDOKA bit or global load OK Clear PWMRFA by reading PMFFQCA with PWMRFA set and then writing a logic one to the PWMRFA bit If another reload occu...

Page 513: ...clock cycles in complementary channel operation A reset sets the PWM deadtime register to the maximum value of 0x0FFF selecting a deadtime Address Module Base 0x0022 Access User read write 1 1 Read Anytime Write Never 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PMFCNTA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 14 26 PMF Counter A Register PMFCNTA Address Module Base 0x0024 Access User read writ...

Page 514: ...d OK defined on device level replaces the function of LDOKB This bit cannot be modified after the WP bit is set 0 LDOKB controls double reload of buffered registers 1 PMF external global load OK controls reload of double buffered registers 2 RSTRTB Restart Generator B When this bit is set PWM generator B will be restarted at the next commutation event This bit cannot be modified after the WP bit i...

Page 515: ...details 0 Half cycle reloads disabled 1 Half cycle reloads enabled 2 1 PRSCB 1 0 Prescaler B This buffered field selects the PWM clock frequency illustrated in Table 14 31 Note Reading the PRSCB field reads the buffered value and not necessarily the value currently in effect The PRSCB field takes effect at the beginning of the next PWM cycle and only when the LDOKB bit or global load OK is set 0 P...

Page 516: ... 1111 Every 16 PWM opportunities Table 14 31 PWM Prescaler B PRSCB 1 0 Prescaler Value PB PWM Clock Frequency fPWM_B 00 1 fcore 01 2 fcore 2 10 4 fcore 4 11 8 fcore 8 Address Module Base 0x002A Access User read write 1 1 Read Anytime Returns zero if MTG is clear Write Never 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PMFCNTB W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 14 31 PMF Counter B Register...

Page 517: ... 1 0 R PWMENC GLDOKC 0 0 0 RSTRTC LDOKC PWMRIEC W Reset 0 0 0 0 0 0 0 0 Figure 14 34 PMF Enable Control C Register PMFENCC Table 14 32 PMFENCC Field Descriptions Field Description 7 PWMENC PWM Generator C Enable If MTG is clear this bit reads zero and cannot be written If MTG is set this bit when set enables the PWM generator C and the PWM4 and PWM5 outputs When PWMENC is clear PWM generator C is ...

Page 518: ...ss User read write 1 1 Read Anytime Returns zero if MTG is clear Write Anytime if MTG is set 7 6 5 4 3 2 1 0 R LDFQC HALFC PRSCC PWMRFC W Reset 0 0 0 0 0 0 0 0 Figure 14 35 PMF Frequency Control C Register PMFFQCC Table 14 33 PMFFQCC Field Descriptions Field Description 7 4 LDFQC 3 0 Load Frequency C This field selects the PWM load frequency according to Table 14 34 See Section 14 4 12 3 Load Freq...

Page 519: ... PWM Reload Frequency LDFQ 3 0 PWM Reload Frequency 0000 Every PWM opportunity 1000 Every 9 PWM opportunities 0001 Every 2 PWM opportunities 1001 Every 10 PWM opportunities 0010 Every 3 PWM opportunities 1010 Every 11 PWM opportunities 0011 Every 4 PWM opportunities 1011 Every 12 PWM opportunities 0100 Every 5 PWM opportunities 1100 Every 13 PWM opportunities 0101 Every 6 PWM opportunities 1101 Ev...

Page 520: ...egister to the maximum value of 0x0FFF selecting a deadtime of 4095 PWM clock cycles Deadtime is affected by changes to the prescaler value The deadtime duration is determined as follows TDEAD_C PMFDTMC fPWM_C PMFDTMC PC Tcore Eqn 14 3 Address Module Base 0x0034 Access User read write 1 1 Read Anytime Returns zero if MTG is clear Write Anytime if MTG is set Do not write a modulus value of zero for...

Page 521: ...ied after the WP bit is set 00 PWMn unaffected by FAULT5 event interrupt flag setting only 01 PWMn unaffected by FAULT5 event interrupt flag setting only 10 PWMn disabled on FAULT5 event 11 PWMn forced to OUTFn on FAULT5 event n is 0 1 2 3 4 and 5 5 4 DMPn4 PWM Disable Mapping Channel n FAULT4 This bit selects for PWMn whether the output is disabled or forced to OUTFn at a FAULT4 event Disabling P...

Page 522: ...en the corresponding DMPn4 or DMPn5 bits are set to switch to output control on a related FAULT4 or FAULT5 event these bits control the PWM outputs illustrated in Table 14 38 This register cannot be modified after the WP bit is set OUTFn Bit Complementary Channel Operation Independent Channel Operation OUTF0 1 PWM0 is active 0 PWM0 is inactive 1 PWM0 is active 0 PWM0 is inactive OUTF1 1 PWM1 is co...

Page 523: ...negative polarity for PWM0 BOTNEGA negative polarity for PWM1 MSK0 and MSK1 bits are set both the PWM complementary outputs of generator A will be high See Section 14 3 2 2 PMF Configure 1 Register PMFCFG1 for the description of TOPNEG and BOTNEG bits and Section 14 3 2 3 PMF Configure 2 Register PMFCFG2 for the description of the MSK0 and MSK1 bits INDEPA 1 OUTF0 OUT0 Fault4 5 Detect OUTCTL0 1 1 ...

Page 524: ... the PWM output period in clock cycles Pulse width The number written to the PWM value register determines the pulse width duty cycle of the PWM output in clock cycles With center aligned output the pulse width is twice the value written to the PWM value register With edge aligned output the pulse width is the value written to the PWM value register 14 4 3 1 Alignment and Compare Output Polarity E...

Page 525: ...MFMODx The PWM counter is an up down counter in center aligned mode In this mode the PWM highest output resolution is two core clock cycles PWM period PWM modulus PWM clock period 2 Eqn 14 4 Figure 14 44 Center Aligned PWM Period Up Down Counter Modulus 4 Alignment Reference PWM Compare Output Duty Cycle 50 CINVn 0 CINVn 1 Up Counter Modulus 4 Alignment Reference PWM Compare Output Duty Cycle 50 C...

Page 526: ...be guaranteed In edge aligned mode the PWM counter is an up counter The PWM output resolution is one core clock cycle PWM period PWM modulus PWM clock period Eqn 14 5 Figure 14 45 Edge Aligned PWM Period NOTE In edge aligned mode the modulus equals zero and one cases are considered illegal 14 4 3 3 Duty Cycle The signed 16 bit number written to the PMF value registers PMFVALn is the pulse width in...

Page 527: ...14 46 Center Aligned PWM Pulse Width Edge aligned operation is illustrated in Figure 14 47 PWM pulse width PWM value PWM clock period Eqn 14 7 Table 14 39 PWM Value and Underflow Conditions PMFVALn Condition PWM Value Used 0x0000 0x7FFF Normal Value in registers 0x8000 0xFFFF Underflow 0x0000 P DOWN COUNTERER MODULUS 4 PWM VALUE 0 0 4 0 PWM VALUE 1 1 4 25 PWM VALUE 2 2 4 50 PWM VALUE 3 3 4 75 PWM ...

Page 528: ...channels in independent channel operation Writing a logic zero to a INDEPx bit configures the PWM output as a pair of complementary channels The PWM outputs are paired as shown in Figure 14 48 in complementary channel operation Figure 14 48 Complementary Channel Pairs UP COUNTERER PWM VALUE 0 MODULUS 4 PWM VALUE 1 PWM VALUE 2 PWM VALUE 3 PWM VALUE 4 0 4 0 1 4 25 2 4 50 3 4 75 4 4 100 COUNTER 1 2 3...

Page 529: ... are an inversion of each other When the top PWM channel is active the bottom PWM channel is inactive and vice versa NOTE To avoid a short circuit on the DC bus and endangering the transistor there must be no overlap of conducting intervals between the top and bottom transistor But the transistor s characteristics make its switching off time longer than switching on time To avoid the conducting ov...

Page 530: ...UX OUT2 OUTCTL2 MUX OUT4 OUTCTL4 PWM GENERATOR CURRENT STATUS DEADTIME GENERATOR OUT1 DEADTIME GENERATOR DEADTIME GENERATOR PWM0 PWM2 PWM4 OUT3 OUT5 TOP BOTTOM GENERATOR TOP BOTTOM GENERATOR TOP BOTTOM GENERATOR TOP PWM0 TO FAULT PROTECTION TO FAULT PROTECTION TO FAULT PROTECTION BOTTOM PWM1 TOP PWM2 BOTTOM PWM3 TOP PWM4 BOTTOM PWM5 PWM1 PWM3 PWM5 PWM0 NO DEADTIME PWM1 NO DEADTIME PWM0 DEADTIME 1 ...

Page 531: ...oid overlap of conducting interval between the top and bottom transistor Both transistors in complementary mode are off during deadtime allowing the output voltage to be determined by the current status of the load and introduce distortion in the output voltage See Figure 14 54 On AC induction motors running open loop the distortion typically manifests itself as poor low speed performance such as ...

Page 532: ... a typical circuit in complementary channel operation only one of the transistors will be effective in controlling the output voltage at any given time This depends on the direction of the motor current for that pair See Figure 14 54 To correct distortion one of two different factors must be added to the desired PWM value depending on whether the top or bottom transistor is controlling the output ...

Page 533: ...e considered the top PWMs while the bottom PWMs are PWM 1 3 and 5 14 4 6 1 Manual Correction The IPOLx bits select either the odd or the even PWM value registers to use in the next PWM cycle Table 14 40 Correction Method Selection ISENS Correction Method 00 No correction 1 1 The current status inputs can be used as general purpose input output ports 01 Manual correction 10 Current status sample co...

Page 534: ...ers Software can then set the IPOLx bit to toggle PMFVAL registers according to DTn values Figure 14 56 Current Status Sense Scheme for Deadtime Correction Both D flip flops latch low DT0 0 DT1 0 during deadtime periods if current is large and flowing out of the complementary circuit See Figure 14 56 Both D flip flops latch the high DT0 1 DT1 1 during deadtime periods if current is also large and ...

Page 535: ...nal voltage sensor can be used when current status is completed during deadtime ISENS 10 Deadtime does not exist at the 100 percent and zero percent duty cycle boundaries Therefore the second automatic mode must be used for correction ISENS 11 where current status is sampled at the half cycle Table 14 42 Top Bottom Current Sense Correction Pin Logic State Output Control IS0 0 PMFVAL0 controls PWM0...

Page 536: ...ue does not take effect until the next PWM period When initially enabled by setting the PWMEN bit no current status has previously been sampled PWM value registers one three and five initially control the three PWM pairs when configured for current status correction Figure 14 60 Correction with Positive Current D Q CLK PWM CONTROLLED BY PWM CONTROLLED BY DEADTIME GENERATOR D Q CLK ISx PIN A B A B ...

Page 537: ...rs to use in the PWM cycle The related CINVn bits of the PWM pair must select the same polarity for both generators NOTE If an ICCx bit in the PMFICCTL register changes during a PWM period the new value does not take effect until the next PWM period ICCx bits take effect at the end of each PWM cycle regardless of the state of the related LDOKx bit or global load OK Table 14 43 Top Bottom Correctio...

Page 538: ...odd value register and its associated CINVn bit The resulting signal can optionally be negated by PINVx and is then fed into the complement and deadtime logic Figure 14 63 If the value of the inverted register exceeds the non inverted register value no output pulse is generated 0 or 100 duty cycle See right half of Figure 14 64 In contrast to asymmetric PWM output mode the PWM phase shift can pass...

Page 539: ...ction in Figure 14 63 in complementary center aligned mode the PWM output can be configured for double switching operation Figure 14 65 Figure 14 66 By setting the non inverted value register greater or equal to the PWM modulus the output function can be switched to single pulse generation on PWM reload cycle basis 9 8 7 6 5 4 3 2 1 Up Counter Modulus 9 PMFVAL0 3 CINV0 1 PMFVAL0 6 CINV0 1 PMFVAL1 ...

Page 540: ...witching PWM Output VAL0 VAL1 Center Aligned Figure 14 66 Double Switching PWM Output VAL0 VAL1 Center Aligned 9 8 7 6 5 4 3 2 1 0 Up Down Counter Modulus 9 PMFVAL0 3 CINV0 1 PMFVAL1 6 CINV1 0 PWM0 PINV 0 PWM0 PINV 1 EDGEA 0 PECA 1 9 8 7 6 5 4 3 2 1 0 Up Down Counter Modulus 9 PMFVAL0 6 CINV0 1 PMFVAL1 3 CINV1 0 PWM0 PINV 0 PWM0 PINV 1 EDGEA 0 PECA 1 0 100 ...

Page 541: ... 14 4 11 Software Output Control Setting output control enable bit OUTCTLn enables software to drive the PWM outputs instead of the PWM generator In independent mode with OUTCTLn 1 the output bit OUTn controls the PWMn channel In complementary channel operation the even OUTCTLn bit is used to enable software output control for the pair The OUTCTLn bits must be switched in pairs for proper operatio...

Page 542: ...gnals with respect to the even OUTn bits Setting the odd OUTn bit makes its corresponding PWM the complement of its even pair while clearing the odd OUTn bit deactivates the odd PWM Setting the OUTCTLn bits does not disable the PWM generators and current status sensing circuitry They continue to run but no longer control the outputs When the OUTCTLn bits are cleared the outputs of the PWM generato...

Page 543: ...re 14 69 Clearing OUT0 with OUTCTL Set in Complementary Mode Figure 14 70 Setting OUTCTL with OUT0 Set in Complementary Mode MODULUS 4 PWM VALUE 2 DEADTIME 2 PWM0 PWM1 PWM0 WITH DEADTIME PWM1 WITH DEADTIME OUTCTL0 OUT0 PWM0 PWM1 OUT1 MODULUS 4 PWM VALUE 2 DEADTIME 2 PWM0 PWM1 PWM0 WITH DEADTIME PWM1 WITH DEADTIME OUTCTL0 OUT0 PWM0 PWM1 OUT1 ...

Page 544: ...the beginning of the next PWM reload cycle Set LDOK by reading it when it is a logic zero and then writing a logic one to it After the PWM reload event LDOK is automatically cleared If LDOK is set in the same cycle as the PWM reload event occurs then the current buffers will be used and the LDOK is valid at the next PWM reload event See Figure 14 71 If an asserted LDOK bit is attempted to be set a...

Page 545: ...controls half cycle reloads for center aligned PWMs If the half bit is set a reload opportunity occurs at the beginning of every PWM cycle and half cycle when the count equals the modulus If the half bit is not set a reload opportunity occurs only at the beginning of every cycle Reload opportunities can only occur at the beginning of a PWM cycle in edge aligned mode NOTE Setting the half bit takes...

Page 546: ... set reloads still occur at the selected reload rate without generating CPU interrupt requests Figure 14 75 PWMRF Reload Interrupt Request Figure 14 76 Full Cycle Center Aligned PWM Value Loading RELOAD CHANGE UP DOWN EVERY TWO OPPORTUNITIES EVERY OPPORTUNITY COUNTERER RELOAD FREQUENCY EVERY FOUR OPPORTUNITIES RELOAD CHANGE UP DOWN EVERY TWO OPPORTUNITIES EVERY OPPORTUNITY COUNTERER RELOAD FREQUEN...

Page 547: ...er Aligned Modulus Loading UP DOWN PWM HALF 0 LDFQ 3 0 0000 RELOAD EVERY CYCLE LDOK 1 MODULUS 2 PWM VALUE 1 PWMRF 1 1 3 1 1 1 2 1 1 1 1 1 1 0 2 1 1 COUNTERER PWM HALF 1 LDFQ 3 0 0000 RELOAD EVERY HALF CYCLE LDOK 1 MODULUS 3 PWM VALUE 1 PWMRF 1 0 3 2 1 1 3 1 1 0 3 3 1 UP DOWN COUNTERER 1 3 2 1 0 3 2 1 1 3 3 1 1 3 1 1 UP DOWN PWM HALF 1 LDFQ 3 0 0000 RELOAD EVERY HALF CYCLE LDOK 1 MODULUS 2 PWM VALU...

Page 548: ... PMFROIFx If the PWM reload overrun interrupt enable bit PMFROIEx is set the PMFROIFx flag generates a CPU interrupt request allowing software to handle the error condition Figure 14 82 PMFROIF Reload Overrun Interrupt Request UP ONLY PWM LDFQ 3 0 0000 RELOAD EVERY CYCLE COUNTERER LDOK 1 MODULUS 3 PWM VALUE 1 PWMRF 1 0 3 2 1 1 3 2 1 0 3 1 1 0 3 1 1 UP ONLY PWM LDFQ 3 0 0000 RELOAD EVERY CYCLE LDOK...

Page 549: ...WM is not enabled therefore a fault will be latched in and will be cleared in order to prevent an interrupt when the PWM is enabled 14 4 13 1 Fault Input Sample Filter Each fault input has a sample filter to test for fault conditions After every bus cycle setting the FAULTm input at logic zero the filter synchronously samples the input once every four bus cycles QSMP determines the number of conse...

Page 550: ...M outputs are enabled on the next IP bus cycle when the logic level detected by the filter at the fault input is logic zero If QSMPm 01 10 or 11 the PWMs are enabled when the next PWM half cycle begins regardless of the state of the logic level detected by the filter at the fault See Figure 14 84 and Figure 14 85 PWM outputs disabled by the FAULT1 or FAULT3 5 inputs are enabled when Software clear...

Page 551: ...daries while the PWM generator is engaged PWMEN equals one But the OUTn bits can control the PWM outputs while the PWM generator is off PWMEN equals zero Thus fault recovery occurs at IPbus cycles while the PWM generator is off and at the start of PWM cycles when the generator is engaged 14 5 Resets All PMF registers are reset to their default values upon any system reset 14 6 Clocks The gated sys...

Page 552: ...K is not set setting PWMEN also sets the PWMRF flag To prevent a CPU interrupt request clear the PWMRIE bit before setting PWMEN Setting PWMEN for the first time after reset without first setting LDOK loads a prescaler divisor of one a PWM value of 0x0000 and an unknown modulus The PWM generator uses the last values loaded if PWMEN is cleared and then set while LDOK equals zero Initializing the de...

Page 553: ...s active unless FENm 0 Software output control remains active Deadtime insertion continues during software output control 14 8 1 1 Register Write Protection The following configuration registers and bits can be write protected PMFCFG0 PMFCFG1 PMFCFG3 PMFFEN PMFQSMP0 1 PMFENCA RSTRTA GLDOKA PMFENCB RSTRTB GLDOKB PMFENCC RSTRTC GLDOKC PMFDTMA B C PMFDMP0 5 PMFOUTF NOTE Make sure to set the write pro...

Page 554: ...0x0D Branch C B mask A 300 PMFOUTC 0x1C Branch A B mask C 360 Table 14 46 Unipolar Switching Sequence 14 8 2 2 Bipolar Switching Mode Bipolar switching mode uses register bits MSK5 0 and PINVA B C to perform commutation The recommended setup is PMFCFG0 INDEPC INDEPB INDEPA 0x0 Complementary mode PMFCFG1 ENCE 1 Enable commutation event PMFCFG2 MSK5 MSK0 0x30 Branch A B mask C 0 PMFCFG3 PINVC PINVB ...

Page 555: ...x03 Branch B C mask A 240 PMFCFG3 PINVC PINVB PINVA 0x4 Invert C PMFCFG2 MSK5 MSK0 0x0c Branch A C mask B 300 PMFCFG3 PINVC PINVB PINVA 0x4 Invert C PMFCFG2 MSK5 MSK0 0x30 Branch A B mask A 360 PMFCFG3 PINVC PINVB PINVA 0x2 Invert B Table 14 47 Bipolar Switching Sequence Branch Channel 0 60 120 180 240 300 A PWM0 PWMgen Masked PWMgen Masked PWMgen PWM1 PWMgen Masked PWMgen Masked PWMgen B PWM2 PWM...

Page 556: ...Chapter 14 Pulse Width Modulator with Fault Protection PMF15B6CV3 MC9S12ZVM Family Reference Manual Rev 1 3 556 Freescale Semiconductor ...

Page 557: ...tive Date Author Description of Changes 06 01 05 29 2012 update register map change BD move IREN to SCIACR2 06 02 10 17 2012 fix typo on page 15 562 and on page 15 562 fix typo of version V6 update fast data tolerance calculation and add notes 06 03 10 25 2012 fix typo Table 15 2 SBR 15 4 not SBR 15 0 06 04 12 19 2012 fix typo Table 15 6 15 4 1 15 575 06 05 02 22 2013 fix typo Figure 15 1 15 559 F...

Page 558: ...6 bit baud rate selection Programmable 8 bit or 9 bit data format Separately enabled transmitter and receiver Programmable polarity for transmitter and receiver Programmable transmitter output parity Two receiver wakeup methods Idle line wakeup Address mark wakeup Interrupt driven operation with eight flags Transmitter empty Transmission complete Receiver full Idle receiver input Receiver overrun ...

Page 559: ... is a high level block diagram of the SCI module showing the interaction of various function blocks Figure 15 1 SCI Block Diagram SCI Data Register RXD Data In Data Out TXD Receive Shift Register Infrared Decoder Receive Wakeup Control Data Format Control Transmit Control Bus Clock 1 16 Transmit Shift Register SCI Data Register Receive Interrupt Generation Transmit Interrupt Generation Infrared En...

Page 560: ...he RXD pin receives SCI standard or infrared data An idle line is detected as a line high This input is ignored when the receiver is disabled and should be terminated to a known voltage 15 3 Memory Map and Register Definition This section provides a detailed description of all the SCI registers 15 3 1 Module Memory Map and Register Definition The memory map for the SCI module is given below in Fig...

Page 561: ...R8 W 0x0001 SCIBDL1 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W 0x0002 SCICR11 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W 0x0000 SCIASR12 R RXEDGIF 0 0 0 0 BERRV BERRIF BKDIF W 0x0001 SCIACR12 R RXEDGIE 0 0 0 0 0 BERRIE BKDIE W 0x0002 SCIACR22 R IREN TNP1 TNP0 0 0 BERRM1 BERRM0 BKDFE W 0x0003 SCICR2 R TIE TCIE RIE ILIE TE RE RWU SBK W 0x0004 SCISR1 R TDRE TC RDRF IDLE OR NF FE PF W 0x0005 SCISR2 R AM...

Page 562: ...Figure 15 4 SCI Baud Rate Register SCIBDL Table 15 2 SCIBDH and SCIBDL Field Descriptions Field Description SBR 15 0 SCI Baud Rate Bits The baud rate for the SCI is determined by the bits in this register The baud rate is calculated two different ways depending on the state of the IREN bit The formulas for calculating the baud rate are When IREN 0 then SCI baud rate SCI bus clock SBR 15 0 When IRE...

Page 563: ... Source Bit When LOOPS 1 the RSRC bit determines the source for the receiver shift register input See Table 15 4 0 Receiver input internally connected to transmitter output 1 Receiver input connected externally to transmitter 4 M Data Format Mode Bit MODE determines whether data characters are eight or nine bits long 0 One start bit eight data bits one stop bit 1 One start bit nine data bits one s...

Page 564: ...the SCI generates and checks for even parity or odd parity With even parity an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit With odd parity an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit 0 Even parity 1 Odd parity Table 15 4 Loop Functions LOOPS RSRC Function 0 x Normal operation 1 0 Loop mode with transmitter output in...

Page 565: ... BERRV Bit Error Value BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and a mismatch to the expected value happened The value is only meaningful if BERRIF 1 0 A low input was sampled when a high was expected 1 A high input reassembled when a low was expected 1 BERRIF Bit Error Interrupt Flag BERRIF is asserted when the bit error detect circuitry is enabled...

Page 566: ...s Field Description 7 RXEDGIE Receive Input Active Edge Interrupt Enable RXEDGIE enables the receive input active edge interrupt flag RXEDGIF to generate interrupt requests 0 RXEDGIF interrupt requests disabled 1 RXEDGIF interrupt requests enabled 1 BERRIE Bit Error Interrupt Enable BERRIE enables the bit error interrupt flag BERRIF to generate interrupt requests 0 BERRIF interrupt requests disabl...

Page 567: ... Transmitter Narrow Pulse Bits These bits enable whether the SCI transmits a 1 16 3 16 1 32 or 1 4 narrow pulse See Table 15 8 2 1 BERRM 1 0 Bit Error Mode Those two bits determines the functionality of the bit error detect feature See Table 15 9 0 BKDFE Break Detect Feature Enable BKDFE enables the break detect circuitry 0 Break detect circuit disabled 1 Break detect circuit enabled Table 15 8 IR...

Page 568: ...t requests disabled 1 RDRF and OR interrupt requests enabled 4 ILIE Idle Line Interrupt Enable Bit ILIE enables the idle line flag IDLE to generate interrupt requests 0 IDLE interrupt requests disabled 1 IDLE interrupt requests enabled 3 TE Transmitter Enable Bit TE enables the SCI transmitter and configures the TXD pin as being controlled by the SCI The TE bit can be used to queue an idle preambl...

Page 569: ...ty 6 TC Transmit Complete Flag TC is set low when there is a transmission in progress or when a preamble or break character is loaded TC is set high when the TDRE flag is set and no data preamble or break character is being transmitted When TC is set the TXD pin becomes idle logic 1 Clear TC by reading SCI status register 1 SCISR1 with TC set and then writing to SCI data register low SCIDRL TC is ...

Page 570: ...ay be at exactly the same time as event 2 or any time after When this happens a dummy SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received 2 NF Noise Flag NF is set when the SCI detects noise on the receiver input NF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun Clear NF by reading SCI status reg...

Page 571: ... of a bit time remaining idle high for a one for inverted polarity 0 Normal polarity 1 Inverted polarity 3 RXPOL Receive Polarity This bit control the polarity of the received data In NRZ format a one is represented by a mark and a zero is represented by a space for normal polarity and the opposite for inverted polarity In IrDA format a zero is represented by short high pulse in the middle of a bi...

Page 572: ...8 is rewritten In 8 bit data format only SCI data register low SCIDRL needs to be accessed Module Base 0x0006 7 6 5 4 3 2 1 0 R R8 T8 0 0 0 Reserved Reserved Reserved W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 15 12 SCI Data Registers SCIDRH Module Base 0x0007 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 Reset 0 0 0 0 0 0 0 0 Figure 15 13 SCI Data Registers SCI...

Page 573: ...cation Interface S12SCIV6 MC9S12ZVM Family Reference Manual Rev 1 3 Freescale Semiconductor 573 When transmitting in 9 bit data format and using 8 bit write instructions write first to SCI data register high SCIDRH then SCIDRL ...

Page 574: ...nerator The CPU monitors the status of the SCI writes the data to be transmitted and processes received data Figure 15 14 Detailed SCI Block Diagram SCI Data Receive Shift Register SCI Data Register Transmit Shift Register Register Receive Generator SBR15 SBR0 Bus Transmit Control 16 Receive and Wakeup Data Format Control Control T8 PF FE NF RDRF IDLE TIE OR TCIE TDRE TC R8 RAF LOOPS RWU RE PE ILT...

Page 575: ...pulses during transmission The infrared block receives two clock sources from the SCI R16XCLK and R32XCLK which are configured to generate the narrow pulse width during transmission The R16XCLK and R32XCLK are internal clocks with frequencies 16 and 32 times the baud rate respectively Both R16XCLK and R32XCLK clocks are used for transmitting data The receive decoder uses only the R16XCLK clock 15 ...

Page 576: ...figured for 9 bit data characters the ninth data bit is the T8 bit in SCI data register high SCIDRH It remains unchanged after transmission and can be used repeatedly without rewriting it A frame with nine data bits has a total of 11 bits Table 15 14 Example of 8 Bit Data Formats Start Bit Data Bits Address Bits Parity Bits Stop Bit 1 8 0 0 1 1 7 0 1 1 1 7 1 1 1 The address bit identifies the fram...

Page 577: ...acquisition rate of 16 samples per bit time Baud rate generation is subject to one source of error Integer division of the bus clock may not give the exact target frequency Table 15 16 lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz When IREN 0 then SCI baud rate SCI bus clock SCIBR 15 0 1 The address bit identifies the frame as an address character See Sect...

Page 578: ...SCIDRH SCIDRL which in turn are transferred to the transmitter shift register The transmit shift register then shifts a frame out through the TXD pin after it has prefaced them with a start bit and appended them with a stop bit The SCI data registers SCIDRH and SCIDRL are the write only buffers between the internal data bus and the transmit shift register PE PT H 8 7 6 5 4 3 2 1 0 L 11 Bit Transmi...

Page 579: ...to SCIDRH L where the ninth bit is written to the T8 bit in SCIDRH if the SCI is in 9 bit data format A new transmission will not result until the TDRE flag has been cleared 3 Repeat step 2 for each subsequent transmission NOTE The TDRE flag is set when the shift register is loaded with the next data to be transmitted from SCIDRH L which happens generally speaking a little over half way through th...

Page 580: ...length depends on the M bit in SCI control register 1 SCICR1 As long as SBK is at logic 1 transmitter logic continuously loads break characters into the transmit shift register After software clears the SBK bit the shift register finishes transmitting the last break character and then transmits at least one logic 1 The automatic logic 1 at the end of a break character guarantees the recognition of...

Page 581: ...l logic 1s and has no start stop or parity bit Idle character length depends on the M bit in SCI control register 1 SCICR1 The preamble is a synchronizing idle character that begins the first transmission initiated after writing the TE bit from 0 to 1 If the TE bit is cleared during a transmission the TXD pin becomes idle after completion of the transmission in progress Clearing and then setting t...

Page 582: ...orted and the byte in transmit buffer is discarded the transmit data register empty and the transmission complete flag will be set The bit error interrupt flag BERRIF will be set No further transmissions will take place until the BERRIF is cleared Figure 15 19 Timing Diagram Bit Error Detection If the bit error detect feature is disabled the bit error interrupt flag is cleared NOTE The RXPOL and T...

Page 583: ...pin The SCI data register is the read only buffer between the internal data bus and the receive shift register After a complete frame shifts into the receive shift register the data portion of the frame transfers to the SCI data register The receive data register full flag RDRF in SCI status register 1 SCISR1 becomes set All 1s M WAKE ILT PE PT RE H 8 7 6 5 4 3 2 1 0 L 11 Bit Receive Shift Registe...

Page 584: ...valid logic 0 To locate the start bit data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s When the falling edge of a possible start bit occurs the RT clock begins to count to 16 Figure 15 21 Receiver Data Sampling To verify the start bit and to detect noise data recovery logic takes samples at RT3 RT5 and RT7 Figure 15 17 summarizes the results of the start bit...

Page 585: ...t samples are logic 1s following a successful start bit verification the noise flag NF is set and the receiver assumes that the bit is a start bit logic 0 To verify a stop bit and to detect noise recovery logic takes samples at RT8 RT9 and RT10 Table 15 19 summarizes the results of the stop bit samples Table 15 18 Data Bit Recovery RT8 RT9 and RT10 Samples Data Bit Determination Noise Flag 000 0 0...

Page 586: ...ple at RT3 is high The RT3 sample sets the noise flag Although the perceived bit time is misaligned the data samples RT8 RT9 and RT10 are within the bit time and data recovery is successful Figure 15 23 Start Bit Search Example 2 Reset RT Clock RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT10 RT9 RT8 RT14 RT13 RT12 RT11 RT15 RT16 RT1 RT2 RT3 Samples RT Clock RT Clock Count Star...

Page 587: ...Figure 15 25 shows the effect of noise early in the start bit time Although this noise does not affect proper synchronization with the start bit time it does set the noise flag Figure 15 25 Start Bit Search Example 4 Reset RT Clock RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT13 RT12 RT11 RT16 RT15 RT14 RT4 RT3 RT2 RT1 RT5 RT6 RT7 RT8 RT9 Samples RT Clock RT Clock Count Actual Start Bit ...

Page 588: ... RT8 RT9 and RT10 data samples are ignored Figure 15 27 Start Bit Search Example 6 15 4 6 4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame it sets the framing error flag FE in SCI status register 1 SCISR1 A break character also sets the FE flag because a break character has no stop bit The FE flag is set at the same time that t...

Page 589: ...T1 but arrives in time for the stop bit data samples at RT8 RT9 and RT10 Figure 15 28 Slow Data Let s take RTr as receiver RT clock and RTt as transmitter RT clock For an 8 bit data character it takes the receiver 9 bit times x 16 RTr cycles 7 RTr cycles 151 RTr cycles to start data sampling of the stop bit With the misaligned character shown in Figure 15 28 the receiver counts 151 RTr cycles at t...

Page 590: ...he receiver counts 169 RTr cycles at the point when the count of the transmitting device is 11 bit times x 16 RTt cycles 176 RTt cycles The maximum percent difference between the receiver count and the transmitter count of a fast 9 bit character with no errors is 176 169 176 x 100 3 98 NOTE Due to asynchronous sample and internal logic there is maximal 2 bus cycles between startbit edge and 1st RT...

Page 591: ...LE or the receive data register full flag RDRF The idle line type bit ILT determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit ILT is in SCI control register 1 SCICR1 15 4 6 6 2 Address Mark Wakeup WAKE 1 In this wakeup method a logic 1 in the most significant bit MSB position of a frame clears the RWU bit and wakes up the SCI Th...

Page 592: ...re operation data from the TXD pin is inverted if RXPOL is set 15 4 8 Loop Operation In loop operation the transmitter output goes to the receiver input The RXD pin is disconnected from the SCI Figure 15 31 Loop Operation LOOPS 1 RSRC 0 Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 SCICR1 Setting the LOOPS bit disables the path from the RXD pin ...

Page 593: ... for reduced power consumption The STOP instruction does not affect the SCI register states but the SCI bus clock will be disabled The SCI operation resumes from where it left off after an external interrupt brings the CPU out of stop mode Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI The receive input active edge detect circuit is still active in s...

Page 594: ...level Indicates that an active edge falling for RXPOL 0 rising for RXPOL 1 was detected BERRIF SCIASR1 1 BERRIE Active high level Indicates that a mismatch between transmitted and received data in a single wire application has happened BKDIF SCIASR1 0 BRKDIE Active high level Indicates that a break character has been received Table 15 20 SCI Interrupt Sources ...

Page 595: ...terrupt indicates that there is no transmission in progress TC is set high when the TDRE flag is set and no data preamble or break character is being transmitted When TC is set the TXD pin becomes idle logic 1 Clear TC by reading SCI status register 1 SCISR1 with TC set and then writing to SCI data register low SCIDRL TC is cleared automatically when data preamble or break is queued and ready to b...

Page 596: ...ceived data in a single wire application like LIN was detected Clear BERRIF by writing a 1 to the SCIASR1 SCI alternative status register 1 This flag is also cleared if the bit error detect feature is disabled 15 5 3 1 8 BKDIF Description The BKDIF interrupt is set when a break signal was received Clear BKDIF by writing a 1 to the SCIASR1 SCI alternative status register 1 This flag is also cleared...

Page 597: ...ransfer width Bidirectional mode Slave select output Mode fault error flag with CPU interrupt capability Double buffered data register Serial clock with programmable polarity and phase Control of SPI operation during wait mode 16 1 3 Modes of Operation The SPI functions in three modes run wait and stop Table 16 1 Revision History Revision Number Revision Date Sections Affected Description of Chang...

Page 598: ...to run mode If the SPI is configured as a slave reception and transmission of data continues so that the slave stays synchronized to the master Stop mode The SPI is inactive in stop mode for reduced power consumption If the SPI is configured as a master any transmission in progress stops but is resumed after CPU goes into run mode If the SPI is configured as a slave reception and transmission of d...

Page 599: ...slave 16 2 2 MISO Master In Slave Out Pin This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master SPI Control Register 1 SPI Control Register 2 SPI Baud Rate Register SPI Status Register SPI Data Register Shifter Port Control Logic MOSI SCK Interrupt Control SPI MSB LSB LSBFE 1 LSBFE 0 LSBFE 0 LSBFE 1 Data In LSBFE 1...

Page 600: ...d by the SPI 16 3 1 Module Memory Map The memory map for the SPI is given in Figure 16 2 The address listed for each register is the sum of a base address and an address offset The base address is defined at the SoC level and the address offset is defined at the module level Reads from the reserved bits return zeros and writes to the reserved bits have no effect Register Name Bit 7 6 5 4 3 2 1 Bit...

Page 601: ...er are reset 0 SPI disabled lower power consumption 1 SPI enabled port pins are dedicated to SPI functions 5 SPTIE SPI Transmit Interrupt Enable This bit enables SPI interrupt requests if SPTEF flag is set 0 SPTEF interrupt disabled 1 SPTEF interrupt enabled 4 MSTR SPI Master Slave Mode Select Bit This bit selects whether the SPI operates in master or slave mode Switching the SPI from master to sl...

Page 602: ...SB in the data register Reads and writes of the data register always have the MSB in the highest bit position In master mode a change of this bit will abort a transmission in progress and force the SPI system into idle state 0 Data is transferred most significant bit first 1 Data is transferred least significant bit first Table 16 3 SS Input Output Selection MODFEN SSOE Master Mode Slave Mode 0 0 ...

Page 603: ...fer to Table 16 3 In master mode a change of this bit will abort a transmission in progress and force the SPI system into idle state 0 SS port pin is not used by the SPI 1 SS port pin with MODF feature 3 BIDIROE Output Enable in the Bidirectional Mode of Operation This bit controls the MOSI and MISO output buffer of the SPI when in bidirectional mode of operation SPC0 is set In master mode this bi...

Page 604: ...PIBR Field Descriptions Field Description 6 4 SPPR 2 0 SPI Baud Rate Preselection Bits These bits specify the SPI baud rates as shown in Table 16 7 In master mode a change of these bits will abort a transmission in progress and force the SPI system into idle state 2 0 SPR 2 0 SPI Baud Rate Selection Bits These bits specify the SPI baud rates as shown in Table 16 7 In master mode a change of these ...

Page 605: ...kbit s 0 1 1 1 0 1 256 97 66 kbit s 0 1 1 1 1 0 512 48 83 kbit s 0 1 1 1 1 1 1024 24 41 kbit s 1 0 0 0 0 0 10 2 5 Mbit s 1 0 0 0 0 1 20 1 25 Mbit s 1 0 0 0 1 0 40 625 kbit s 1 0 0 0 1 1 80 312 5 kbit s 1 0 0 1 0 0 160 156 25 kbit s 1 0 0 1 0 1 320 78 13 kbit s 1 0 0 1 1 0 640 39 06 kbit s 1 0 0 1 1 1 1280 19 53 kbit s 1 0 1 0 0 0 12 2 08333 Mbit s 1 0 1 0 0 1 24 1 04167 Mbit s 1 0 1 0 1 0 48 520 8...

Page 606: ...SPI data register For information about clearing SPIF Flag please refer to Table 16 9 0 Transfer not yet complete 1 New data copied to SPIDR 5 SPTEF SPI Transmit Empty Interrupt Flag If set this bit indicates that the transmit data register is empty For information about clearing this bit and placing data into the transmit data register please refer to Table 16 10 0 SPI data register not empty 1 S...

Page 607: ...dly without any effect on SPIF SPIF Flag is cleared only by the read of SPIDRL after reading SPISR with SPIF 1 Byte Read SPIDRL or Word Read SPIDRH SPIDRL XFRW Bit SPTEF Interrupt Flag Clearing Sequence 0 Read SPISR with SPTEF 1 then Write to SPIDRL 1 1 Any write to SPIDRH or SPIDRL with SPTEF 0 is effectively ignored 1 Read SPISR with SPTEF 1 then Byte Write to SPIDRL 1 2 2 Data in SPIDRH is unde...

Page 608: ...f SPIF is set and not serviced and a second data value has been received the second received data is kept as valid data in the receive shift register until the start of another transmission The data in the SPIDR does not change If SPIF is set and valid data is in the receive shift register and SPIF is serviced before the start of a third transmission the data in the receive shift register is trans...

Page 609: ... The SPI system is enabled by setting the SPI enable SPE bit in SPI control register 1 While SPE is set the four associated SPI port pins are dedicated to the SPI function as Slave select SS Serial clock SCK Master out slave in MOSI Master in slave out MISO Receive Shift Register SPIF SPI Data Register Data A Data B Data A Data A Received Data B Received Data C Data C SPIF Serviced Data C Received...

Page 610: ... see Section 16 4 3 Transmission Formats The SPI can be configured to operate as a master or as a slave When the MSTR bit in SPI control register1 is set master mode is selected when the MSTR bit is clear slave mode is selected NOTE A change of CPOL or MSTR bit while there is a received byte pending in the receive shift register will destroy the received byte and must be avoided 16 4 1 Master Mode...

Page 611: ...he SPI into idle state The remote slave cannot detect this therefore the master must ensure that the remote slave is returned to idle state 16 4 2 Slave Mode The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear Serial clock In slave mode SCK is the SPI clock input from the master MISO MOSI pin In slave mode the function of the serial data output pin MISO and serial d...

Page 612: ...the SPI data is driven out of the serial data output pin After the nth1 shift the transfer is considered complete and the received data is transferred into the SPI data register To indicate transfer is complete the SPIF flag in the SPI status register is set NOTE A change of the bits CPOL CPHA SSOE LSBFE MODFEN SPC0 or BIDIROE with SPC0 set in slave mode will corrupt a transmission in progress and...

Page 613: ...hift register depending on LSBFE bit After this second edge the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave This process continues for a total of 16 edges on the SCK line with data being latched on odd numbered edges and shifted on even numbered edges Data reception is double buffered Data is shifted serially i...

Page 614: ... 5 Bit 2 Bit 6 Bit 1 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 CHANGE O SEL SS I MOSI pin MISO pin Master only MOSI MISO tT If next transfer begins here for tT tl tL Minimum 1 2 SCK tI tL tL Minimum leading time before the first SCK edge tT Minimum trailing time after the last SCK edge tI Minimum idling time between transfers minimum SS high time tL tT and tI are guaranteed for the master mo...

Page 615: ...rst edge of SCK occurs immediately after the half SCK clock cycle synchronization delay This first edge commands the slave to transfer its first data bit to the serial data input pin of the master A half SCK cycle later the second edge appears on the SCK pin This is the latching edge for both the master and slave 1 n depends on the selected transfer width please refer to Section 16 3 2 2 SPI Contr...

Page 616: ...he transfer is complete Figure 16 14 shows two clocking variations for CPHA 1 The diagram may be interpreted as a master or slave timing diagram because the SCK MISO and MOSI pins are connected directly between the master and the slave The MISO signal is the output from the slave and the MOSI signal is the output from the master The SS line is the slave select input to the slave The SS pin of the ...

Page 617: ...PR1 and SPR0 determine the divisor to the SPI module clock which results in the SPI baud rate The SPI clock rate is determined by the product of the value in the baud rate preselection bits SPPR2 SPPR0 and the value in the baud rate selection bits SPR2 SPR0 The module clock divisor equation is shown in Equation 16 3 tL Begin End SCK CPOL 0 SAMPLE I CHANGE O SEL SS O Transfer SCK CPOL 1 MSB first L...

Page 618: ...ase refer to the SPI Electrical Specification in the Electricals chapter of this data sheet 16 4 5 Special Features 16 4 5 1 SS Output The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices When SS output is selected the SS output pin is connected to the SS input pin of the external device...

Page 619: ... this case MISO becomes occupied by the SPI and MOSI is not used This must be considered if the MISO pin is used for another purpose 16 4 6 Error Conditions The SPI has one error condition Mode fault error 16 4 6 1 Mode Fault Error If the SS input becomes low while the SPI is configured as a master it indicates a system error where more than one master may be trying to drive the MOSI and SCK lines...

Page 620: ... Low Power Mode Options 16 4 7 1 SPI in Run Mode In run mode with the SPI system enable SPE bit in the SPI control register clear the SPI system is in a low power disabled state SPI registers remain accessible but clocks to the core of this module are disabled 16 4 7 2 SPI in Wait Mode SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2 If SPISWAI is clea...

Page 621: ...he SPI will stay synchronized with the master The stop mode is not dependent on the SPISWAI bit 16 4 7 4 Reset The reset values of registers and signals are described in Section 16 3 Memory Map and Register Definition which details the registers and their bit fields If a data transmission occurs in slave mode after reset without a write to SPIDR it will transmit garbage or the data last received f...

Page 622: ...ter After SPIF is set it does not clear until it is serviced SPIF has an automatic clearing process which is described in Section 16 3 2 4 SPI Status Register SPISR 16 4 7 5 3 SPTEF SPTEF occurs when the SPI data register is ready to accept new data After SPTEF is set it does not clear until it is serviced SPTEF has an automatic clearing process which is described in Section 16 3 2 4 SPI Status Re...

Page 623: ...for BEMF zero crossing detection in sensorless BLDC applications Table 17 1 Revision History Table 4 0 27 May 2013 Changed overvoltage behaviourTable 17 22 4 1 27 June 2013 Corrected GLVLSS description Minor corrections 4 2 8 July 2013 Corrected GHHDIF description Reworked Table 1 24 fault protection summary Added Filter circiut and Note to Figure 1 19 Modified GOCA0 and GOCA1 bit descriptions 4 3...

Page 624: ...ait mode All GDU features are available 3 Stop mode The GDU is disabled in stop mode The high side drivers low side drivers charge pump voltage regulator boost circuit and current sense amplifier are switched off The bits in the GDUE register are cleared on entry into stop mode The GDU will weakly pull the gates of the MOSFET to their source potential On exit from stop mode the GDUE register bits ...

Page 625: ...s a block diagram of the GDU module Figure 17 1 GDU Block Diagram HD VBS 2 0 HG 2 0 HS 2 0 VLS 2 0 LG 2 0 LS 2 0 VSSB BST CP VCP VSUP VLS_OUT AMP 1 0 AMPM 1 0 AMPP 1 0 Boost Converter Option Charge Pump Two Current Sense Amplifiers Voltage Regulator Register Level Shifters FET Pre Drivers Control Error ADC Channels PWM Channels IP Bus ...

Page 626: ...igh side power FETs 17 2 4 HS 2 0 High Side Source Pins The pins are the source connection for the high side power FETs and the drain connection for the low side power FETs The low voltage end of the bootstrap capacitor is also connected to this pin 17 2 5 VLS 2 0 Voltage Supply for Low Side Pre Drivers The pins are the voltage supply pins for the three low side FET pre drivers This pins should be...

Page 627: ...lly between 0V and 11V 17 2 5 7 VCP Charge Pump Input for High Side Driver Supply This pin is the charge pump input for the high side FET pre driver supply VBS 2 0 17 2 5 8 BST Boost Converter Pin This pin provides the basic switching elements required to implement a boost converter for low battery voltage conditions This requires external diodes capacitors and a coil 17 2 5 9 VSSB Boost Ground Pi...

Page 628: ...U level and the Address Offset is defined at the module level Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 GDUE R GWP 0 EPRES GCSE1 GBOE GCSE0 GCPE GFDE W 0x0001 GDUCTR R GHHDLVL 0 GBKTIM2 3 0 GBKTIM1 1 0 W 0x0002 GDUIE R 0 0 0 GOCIE 1 0 GDSEIE GHHDIE GLVLSIE W 0x0003 GDUDSE R 0 GDHSIF 2 0 0 GDLSIF 2 0 W 0x0004 GDUSTAT R GPHS 2 0 GOCS 1 0 GHHDS GLVLSS W 0x0005 GDUSRC R 0 GSRCHS 2 0 ...

Page 629: ...number Details of register bit and field function follow the register diagrams in bit order Unused bits read back zero 0x000A GDUCSO R 0 GCSO1 2 0 0 GCSO0 2 0 W 0x000B GDUDSLVL R 0 GDSLHS 2 0 0 GDSLLS 2 0 W 0x000C GDUPHL R 0 0 0 0 0 GPHL 2 0 W 0x000D GDUCLK2 R 0 0 0 0 GCPCD 3 0 W 0x000E GDUOC0 R GOCA0 GOCE0 0 0 GOCT0 3 0 W 0x000F GDUOC1 R GOCA1 GOCE1 GOCT1 3 0 W 0x0010 0x001F Address Offset Regist...

Page 630: ... 5 EPRES Enable High Side Driver Preserve Functionality This bit controls the bootstrap charge preserve mode of the high side drivers If EPRES is set and the high side driver is switched off the input current of the VBSx pins is reduced by typically 100uA in order to preserve the charge on the bootstrap capacitor This bit cannot be modified after GWP bit is set 0 High side driver preserve function...

Page 631: ...w side and high side FET pre drivers This bit cannot be modified after GWP bit is set See Section 17 4 2 Low Side FET Pre Drivers and Section 17 4 3 High Side FET Pre Driver 0 Low side and high side drivers are disabled 1 Low side and high side drivers are enabled NOTE It is not allowed to set and clear GFDE bit periodically in order to switch on and off the FET pre drivers In order to switch on a...

Page 632: ...Level Select Selects the voltage threshold of the overvoltage detection on HD pin This bit cannot be modified after GWP bit is set 0 Voltage threshold of the overvoltage detection on HD pin VHVHDL 1 Voltage threshold of the overvoltage detection on HD pin VHVHDH 5 2 GBKTIM2 3 0 GDU Blanking Time These bits adjust the blanking time tBLANK of the desaturation error comparators The resulting blanking...

Page 633: ...ister is set 2 GDSEIE GDU Desaturation Error Interrupt Enable Enables desaturation error interrupt on low side or high side drivers 0 No interrupt will be requested if any of the flags in the GDUDSE register is set 1 Interrupt will be requested if any of the flags in the GDUDSE register is set 1 GHHDIE GDU High HD Interrupt Enable Enables the high HD interrupt 0 No interrupt will be requested when...

Page 634: ...ccurs If the GDSEIE bit is set an interrupt is requested Writing a logic 1 to the bit field clears the flag 0 No desaturation error on high side driver 1 Desaturation error on high side driver 2 0 GDLSIF 2 0 GDU Low Side Driver Desaturation Interrupt Flag The flag is set to 1 when a desaturation error on associated low side driver pin LS 2 0 occurs If the GDSEIE bit is set an interrupt is requeste...

Page 635: ...red when the voltage on the overcurrent comparator input is less than VOCT Section 17 4 8 Current Sense Amplifier and Overcurrent Comparator 0 Voltage on overcurrent comparator input is is less than VOCT 1 Voltage on overcurrent comparator is greater than VOCT 1 GHHDS GDU High HD Supply Status The status bit is set to 1 when the voltage on HD pin is above the threshold voltage VHVHDLA or VHVHDHA d...

Page 636: ... 0 GDU Slew Rate Control Bits High Side FET Pre Drivers These bits control the slew rate on the HG 2 0 pins see FET Pre Driver Details These bits cannot be modified after GWP bit is set 000 slowest 111 fastest 3 0 GSRCLS 2 0 GDU Slew Rate Control Bits Low Side FET Pre Drivers These bits control the slew rate on the LG 2 0 pins see FET Pre Driver Details These bits cannot be modified after GWP bit ...

Page 637: ... drivers are driven by the PWM channels The flag is set by hardware if a high voltage condition on HD pin occurs The flag is set if the voltage on pin HD is greater than the threshold voltage VHVHDLA or VHVHDHA Writing a logic 1 to the bit field clears the flag 0 Voltage on pin HD is less than VHVHDLD or VHVHDHD 1 Voltage on pin HD is greater than VHVHDLA or VHVHDHA 5 GLVLSF GDU Low VLS Supply Fla...

Page 638: ...is set or GLVLSS is cleared If the GLVLSIE bit is set an interrupt is requested Writing a logic 1 to the bit field clears the flag Module Base 0x0007 Access User read write 1 1 Read Anytime Write Anytime if GWP 0 7 6 5 4 3 2 1 0 R 0 GBOCD 4 0 GBODC 1 0 W Reset 0 0 0 0 0 0 0 0 Figure 17 10 GDU Clock Control Register 1 GDUCLK1 Table 17 9 GDUCLK1 Register Field Descriptions Field Description 6 2 GBOC...

Page 639: ...OOST 00000 fBUS 4 00001 fBUS 4 00010 fBUS 4 00011 fBUS 4 00100 fBUS 4 00101 fBUS 4 00110 fBUS 6 00111 fBUS 6 01000 fBUS 8 01001 fBUS 8 01010 fBUS 10 01011 fBUS 10 01100 fBUS 12 01101 fBUS 12 01110 fBUS 14 01111 fBUS 14 10000 fBUS 16 10001 fBUS 24 10010 fBUS 32 10011 fBUS 48 10100 fBUS 64 10101 fBUS 96 10110 fBUS 100 10111 fBUS 128 11000 fBUS 192 11001 fBUS 200 11010 fBUS 256 ...

Page 640: ...GDUV4 MC9S12ZVM Family Reference Manual Rev 1 3 Freescale Semiconductor 640 11011 fBUS 384 11100 fBUS 400 11101 fBUS 512 11110 fBUS 768 11111 fBUS 800 Table 17 10 Boost Option Clock Divider Factors k fBUS fBOOST GBOCD 4 0 fBOOST ...

Page 641: ...lectrical parameters Module Base 0x0009 Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 GPHMX 1 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 17 12 GDU Phase Mux Register GDUPHMUX Table 17 12 GDU Phase Mux Register Field Descriptions Field Description 1 0 GPHMUX GDU Phase Multiplexer These buffered bits are used to select the voltage which is routed to internal...

Page 642: ...set of the current sense amplifier See Section 17 4 8 Current Sense Amplifier and Overcurrent Comparator 000 No offset 001 Offset is 5mV 010 Offset is 10mV 011 Offset is 15mV 100 No offset 101 Offset is 15mV 110 Offset is 10mV 111 Offset is 5mV 2 0 GCSO0 2 0 GDU Current Sense Amplifier 0 Offset These bits adjust the offset of the current sense amplifier See Section 17 4 8 Current Sense Amplifier a...

Page 643: ...s set See Section 17 4 5 Desaturation Error 000 Vdesaths VHD 0 30V 001 Vdesaths VHD 0 45V 010 Vdesaths VHD 0 60V 011 Vdesaths VHD 0 75V 100 Vdesaths VHD 0 90V 101 Vdesaths VHD 1 05V 110 Vdesaths VHD 1 20V 111 Vdesaths VHD 1 35V 2 0 GDSLLS GDU Desaturation Level for Low Side Drivers This bits adjust the desaturation level of the three low side FET pre drivers These bits cannot be modified after GWP...

Page 644: ...r Field Descriptions Field Description 2 0 GPHL GDU Phase Log Bits If a desaturation error occurs the phase status bits GPHS 2 0 in register GDUSTAT are copied to this register The GDUPHL register is cleared only on reset See Section 17 4 5 Desaturation Error Module Base 0x000D Access User read write 1 1 Read Anytime Write Only if GWP 0 7 6 5 4 3 2 1 0 R 0 0 0 0 GCPCD 3 0 W Reset 0 0 0 0 0 0 0 0 F...

Page 645: ...tor 645 Table 17 17 Charge Pump Clock Divider Factors k fBUS fCP GCPCD 3 0 fCP 0000 fBUS 16 0001 fBUS 24 0010 fBUS 32 0011 fBUS 48 0100 fBUS 64 0101 fBUS 96 0110 fBUS 100 0111 fBUS 128 1000 fBUS 192 1001 fBUS 200 1010 fBUS 256 1011 fBUS 384 1100 fBUS 400 1101 fBUS 512 1110 fBUS 768 1111 fBUS 800 ...

Page 646: ...7 22 and Table 17 21 6 GOCE0 GDU Overcurrent Comparator Enable This bit cannot be modified after GWP bit is set 0 Overcurrent Comparator is disabled 1 Overcurrent Comparator is enabled 3 0 GOCT0 3 0 GDU Overcurrent Comparator Threshold These bits cannot be modified after GWP bit is set The overcurrent comparator threshold voltage is the output of a 6 bit digital to analog converter The upper two b...

Page 647: ...modified after GWP bit is set This bit controls the action in case of an overcurrent event or overvoltage event See Table 17 22 and Table 17 21 6 GOCE1 GDU Overcurrent Enable This bit cannot be modified after GWP bit is set 0 Overcurrent Comparator 1 is disabled 1 Overcurrent Comparator 1 is enabled 3 0 GOCT1 3 0 GDU Overcurrent Comparator Threshold These bits cannot be modified after GWP bit is s...

Page 648: ...e the bootstrap capacitor CBS Care must be taken after a long period of inactivity of the low side FET pre drivers to verify that the bootstrap capacitor CBS is not discharged see also Calculation of Bootstrap Capacitor The register bits GSRCHS 2 0 in the GDUSRC Register see Figure 17 8 control the slew rate of the high side FET pre driver in order to control fast voltage changes dv dt see also Se...

Page 649: ...p input RC filter can be used to avoid overpumpimg effect when voltage spikes are present on the high side drains Vref VBAT hs_on ls_on VLS_OUT CP VCP VBSx HGx HSx VLSx LGx LSx C1 D1 D2 CBS Rsense VSUP GSRCHS 2 0 GSRCLS 2 0 D4 D5 Reverse Battery Protection GCPE GCPCD 3 0 HD GHHDIF C2 100 220nF optional charge pump filter CG CG Charge Pump Connect C R optional RC filter to VBS pin 10uF ...

Page 650: ...trap capacitor CBS 17 4 4 Charge Pump The GDU module integrates the necessary hardware to build a charge pump with external components The charge pump is used to maintain the high side driver gate source voltage VGS when PWM is running at 100 duty cycle The external components needed are capacitors and diodes The supply voltage of the charge pump driver on pin CP is VVLS The output voltage on pin ...

Page 651: ...re 17 14 If the high side power FET T1 see Figure 17 20 is turned on and the drain source voltage VDS1 is greater than Vdesaths after the blanking time tBLANK a desaturation error will be flagged In this case the associated desaturation error flag GDHSIF 2 0 will be set see Figure 17 6 and the high side power FET T1 will be turned off The level of the voltage Vdesaths can be adjusted in the range ...

Page 652: ...ared 17 4 7 Fault Protection Features The GDU includes a number of fault protection features against overvoltage overcurrent undervoltage and power bridge faults like phase shorted to ground or supply Fault conditions enables response by the GDU and turn on or off low side and high side drivers as shown in Table 17 22 In addition five fault outputs are provided to signal detected faults to other m...

Page 653: ...off off on on on overcurrent condition comparator 1 GOCA1 0 x x x 1 0 000 000 off off off on on on undervoltage condition on VLS_OUT pin x x x x 1 000 000 off off off off off off overcurrent condition comparator 0 GOCA0 1 x x 1 x x 000 000 off off off off off off overcurrent condition comparator 1 GOCA1 1 x x x 1 x 000 000 off off off off off off desaturation error condition on high side FET pre d...

Page 654: ... all MOSFET transistors are turned off VBSX can reach phase voltage plus bootstrap voltage which may exceed allowable levels during high supply voltage conditions If such operating condition exist the application must make sure that VBSX levels are clamped below maximum ratings for example by using clamping diodes ...

Page 655: ...igure 17 21 Short to Supply Detection Figure 17 22 Short to Ground Detection LGx HGx HSx Phase Status Desat Error VHD 0 5 VHD correct voltage on HSx HSx shorted to supply correct fault tBLANK HGx LGx HSx Phase Status Desat Error VHD 0 5 VHD correct voltage on HSx HSx shorted to ground correct fault tBLANK ...

Page 656: ...e current sense amplifier can be adjusted with the GCSO 2 0 bits in the GDUCSO register see Figure 17 13 The output of the current sense amplifier is connected to the plus input of the overcurrent comparator The minus input is driven by the output voltage of a 6 Bit DA converter The digital input of the DA converter is 11 GOCTx 3 0 In order to use the overcurrent comparator GOCEx and GCSxE have to...

Page 657: ...emiconductor 657 17 4 9 GDU DC Link Voltage Monitor In addition to the feature described in Section 17 3 2 10 GDU Phase Mux Register GDUPHMUX the voltage on pin HD divide by 5 is routed to an ADC channel See SOC section for ADC channel number This feature is only available if GFDE is set ...

Page 658: ...cuit to limit the current through coil This current limit can be adjusted with the bits GBCL 3 0 in the GDUBCL register See GDU electrical parameters The output voltage of the boost converter on VSUP pin is divided down and compared with a reference voltage Vref As long as the divided voltage VVSUP is below Vref the boost converter clock is enabled assuming that GBOE GDU Boost Option Enable is set...

Page 659: ...flags are combined into one interrupt line and the over and under voltage detection are combined into another interrupt line see SOC section interrupt vector table Table 17 23 GDU Module Interrupt Sources GDU Module Interrupt Source Module Internal Interrupt Source Local Enable 0 GDU desaturation error interrupt GDU low side and high side desaturation error flags GDHSF 2 0 and GDLSF 2 0 GDSEIE 1 1...

Page 660: ...tors T3 and T4 are switched on For on resistance Rgduoffn and Rgduoffp of transistors T3 and T4 refer to GDU electricals The reference current IREF is controlled by the slew rate conrol bits GSRCHS 2 0 IREF 10uA GSRCHS 10uA 10uA 20uA 80uA Assuming an ideal op amp the voltage across R1 is equal voltage across R2 and IOUT2 is given by V1 V2 IREF R1 IOUT2 R2 IOUT2 IREF R1 R2 With the ratio of the tra...

Page 661: ... needed to turn on the power FET used in the application If the bootstrap capacitor is too small there can be a large voltage drop due to charge sharing between bootstrap capacitor CBS and the total gate capacitance of the power FET CG The resulting voltage on the gate of the power FET can be calculated as follow Eqn 17 1 For example if CBS 20 CG then the resulting gate voltage is VG 0 95 VBS VG Q...

Page 662: ...Chapter 17 Gate Drive Unit GDUV4 MC9S12ZVM Family Reference Manual Rev 1 3 662 Freescale Semiconductor ...

Page 663: ... 25 June 2012 All Added LIN TxD dominant timeout feature V02 06 11 Jan 2013 All Added application note to help the ISR development for the Interrupts timeout and overcurrent V02 08 10 Apr 2013 Register and interrupt descriptions application section Added notes regarding the correct handling of clearing LPOCIF and LPDTIF V02 09 27 Jun 2013 Feature list Added the SAE J2602 2 LIN compliance V02 10 21...

Page 664: ...all time from recessive to dominant and the rise time from dominant to recessive is selectable and controlled to guarantee communication quality and reduce EMC emissions The symmetry between both slopes is guaranteed 18 1 2 Modes of Operation The LIN Physical Layer can operate in the following four modes 1 Shutdown Mode The LIN Physical Layer is fully disabled No wake up functionality is available...

Page 665: ...iagram of the LIN Physical Layer The module consists of a receiver with wake up control a transmitter with slope and timeout control a current sensor with overcurrent protection as well as a registers control block Figure 18 1 LIN Physical Layer Block Diagram NOTE The external 220 pF capacitance between LIN and LGND is strongly recommended for correct operation ...

Page 666: ... and filter noise 18 2 3 VLINSUP Positive Power Supply External power supply to the chip The VLINSUP supply mapping is described in device level documentation 18 2 4 LPTxD LIN Transmit Pin This pin can be routed to the SCI LPDR1 register bit an external pin or other options Please refer to the PIM chapter of the device specification for the available routing options This input is only used in norm...

Page 667: ...Address Module Base Address Address Offset where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 LPDR R 0 0 0 0 0 0 LPDR1 LPDR0 W 0x0001 LPCR R 0 0 0 0 LPE RXONLY LPWUE LPPUE W 0x0002 Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x0003 LPSLRM...

Page 668: ... 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 LPDR1 LPDR0 W Reset 0 0 0 0 0 0 1 1 Unimplemented Figure 18 3 Port LP Data Register LPDR Field Description 1 LPDR1 Port LP Data Bit 1 The LIN Physical Layer LPTxD input see Figure 18 1 can be directly controlled by this register bit The routing of the LPTxD input is done in the Port Inetrgation Module PIM Please refer to the PIM chapter o...

Page 669: ...ical Layer functions are available except that the bus line is held in its recessive state by a high ohmic 330kΩ resistor All registers are normally accessible 1 The LIN Physical Layer is not in shutdown mode 2 RXONLY Receive Only Mode bit This bit controls RXONLY mode 0 The LIN Physical Layer is not in receive only mode 1 The LIN Physical Layer is in receive only mode 1 LPWUE LIN Wake Up Enable T...

Page 670: ... write 1 1 Read Anytime Write Only in special mode 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W Reset x x x x x x x x Unimplemented Figure 18 5 LIN Test register Table 18 4 Reserved Register Field Description Field Description 7 0 Reserved These reserved bits are used for test purposes Writing to these bits can alter the module functionality Module Ba...

Page 671: ... section 18 4 2 for details on how the slew rate control works These bits are only writable in shutdown mode LPE 0 00 Normal Slew Rate optimized for 20 kbit s 01 Slow Slew Rate optimized for 10 4 kbit s 10 Fast Mode Slew Rate up to 250 kbit s This mode is not compliant with the LIN Protocol LIN electrical characteristics like duty cycles reference levels etc are not fulfilled It is only meant to b...

Page 672: ...plemented Figure 18 8 LIN Status Register LPSR Table 18 7 LPSR Field Description Field Description 7 LPDT LIN Transmitter TxD dominant timeout Status Bit This read only bit signals that the LPTxD pin is still dominant after a TxD dominant timeout As long as the LPTxD is dominant after the timeout the LIN transmitter is shut down and the LPTDIF is set again after attempting to clear it 0 If there w...

Page 673: ... 3 2 1 0 R LPDTIE LPOCIE 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 18 9 LIN Interrupt Enable Register LPIE Table 18 8 LPIE Field Description Field Description 7 LPDTIE LIN transmitter TxD dominant timeout Interrupt Enable 0 Interrupt request is disabled 1 Interrupt is requested if LPDTIF bit is set 6 LPOCIE LIN transmitter Overcurrent Interrupt Enable 0 Interrupt request is disabled...

Page 674: ...DTIF is not allowed if LPDTIF 0 already If the LPTxD is still dominant after clearing the flag the transmitter stays disabled and this flag is set again see 18 4 4 2 TxD dominant timeout Interrupt If interrupt requests are enabled LPDTIE 1 LPDTIF causes an interrupt request 0 No TxD dominant timeout has occurred 1 A TxD dominant timeout has occurred 6 LPOCIF LIN Transmitter Overcurrent Interrupt F...

Page 675: ...ted the LIN Physical Layer can be enabled again NOTE For 20 kbit s and Fast Mode communication speeds the corresponding slew rate MUST be set otherwise the communication is not guaranteed violation of the specified LIN duty cycles For 10 4 kbit s the 20 kbit s slew rate can be set but the EMC performance is worse The up to 250 kbit s slew rate must be chosen ONLY for fast mode not for any of the 1...

Page 676: ...utdown mode 18 4 3 2 Normal Mode The full functionality is available Both receiver and transmitter are enabled The internal pullup resistor can be chosen to be high ohmic 330 kΩ if LPPUE 0 or LIN compliant 34 kΩ if LPPUE 1 If RXONLY is set the module leaves normal mode to enter receive only mode If the MCU enters stop mode the LIN Physical Layer enters standby mode 18 4 3 3 Receive Only Mode Enter...

Page 677: ...p enabled If LPWUE 0 the internal pullup resistor is not selectable and remains at 330 kΩ regardless of the state of the LPPUE bit If LPWUE 1 selecting the 330 kΩ pullup resistor LPPUE 0 reduces the current consumption in standby mode NOTE When using the LIN wake up feature in combination with other non LIN device wake up features like a periodic time interrupt some care must be taken If the devic...

Page 678: ...Chapter 18 LIN Physical Layer S12LINPHYV2 MC9S12ZVM Family Reference Manual Rev 1 3 678 Freescale Semiconductor Figure 18 11 LIN Physical Layer Mode Transitions ...

Page 679: ... enable the transmitter again the following prerequisites must be met 1 Overcurrent condition is over 2 LPTxD is recessive or the LIN Physical Layer is in shutdown or receive only mode for a minimum of a transmit bit time To re enable the transmitter then the LPOCIF flag must be cleared by writing a 1 NOTE Please make sure that LPOCIF 1 before trying to clear it It is not allowed to try to clear L...

Page 680: ...more than tDTLIM the transmitter is disabled and the LPDT status flag and the LPDTIF interrupt flag are set In order to re enable the transmitter again the following prerequisites must be met 1 TxD dominant condition is over LPDT 0 2 LPTxD is recessive or the LIN Physical Layer is in shutdown or receive only mode for a minimum of a transmit bit time To re enable the transmitter then the LPDTIF fla...

Page 681: ... the transmitter remains disabled and the LPDTIF flag is set after a time again to indicate that the attempt to re enable has failed This time is equal to minimum 1 IRC period 1 us 2 bus periods maximum 2 IRC periods 2 us 3 bus periods If the bit LPDTIE is set in the LPIE register an interrupt is requested Figure 18 13 shows the different scenarios of TxD dominant timeout interrupt handling Figure...

Page 682: ...ng to clear an error flag always make sure that it is already set 18 5 2 Interrupt handling in Interrupt Service Routine ISR Both interrupts TxD dominant timeout and overcurrent represent a failure in transmission To avoid more disturbances on the transmission line the transmitter is de activated in both cases The interrupt subroutine must take care of clearing the error condition and starting the...

Page 683: ... 5 Enable the interrupts again LPDTIE and LPOCIE 6 Enable the LIN Physical Layer or leave the receive only mode LPCR register 7 Wait for a minimum of a transmit bit before beginning transmission again If there is a problem re enabling the transmitter then the error flag will be set again during step 3 and the ISR will be called again ...

Page 684: ...Chapter 18 LIN Physical Layer S12LINPHYV2 MC9S12ZVM Family Reference Manual Rev 1 3 684 Freescale Semiconductor ...

Page 685: ...iption of wait state control bits Section 19 3 2 4 and Section 19 3 2 5 Updated section describing the procedure to enable disable wait states Section 19 4 3 V02 01 06 Mar 2012 Modified behavior of ECC flags Section 19 3 2 8 Attempt to access P Flash and EEPROM simultaneously when not allowed will report illegal access Section 19 4 6 V02 02 20 Mar 2012 Updated feature description Section 19 4 6 V0...

Page 686: ... bus cycle for bytes and aligned words For misaligned words access the CPU has to perform twice the byte read access command For Flash memory an erased bit reads 1 and a programmed bit reads 0 It is possible to read from P Flash memory while some commands are executing on EEPROM memory It is not possible to read from EEPROM memory while a command is executing on P Flash memory Simultaneous P Flash...

Page 687: ...rs of 512 bytes Single bit fault correction and double bit fault detection within a 32 bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phrase program operation Ability to read the P Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or er...

Page 688: ...igure 19 1 Figure 19 1 FTMRZ128K512 Block Diagram 19 2 External Signal Description The Flash module contains no signals that connect off chip Bus Clock Divider Clock Command Interrupt Request FCLK Protection Security Registers Flash Interface 16bit internal bus sector 0 sector 1 sector 255 32Kx39 P Flash Error Interrupt Request CPU 256x22 sector 0 sector 1 sector 127 EEPROM Memory Controller ...

Page 689: ...to Section 19 6 for a complete description of the reset sequence 19 3 1 Module Memory Map The S12Z architecture places the P Flash memory between global addresses 0xFE_0000 and 0xFF_FFFF as shown in Table 19 3 The P Flash memory map is shown in Figure 19 2 The FPROT register described in Section 19 3 2 9 can be set to protect regions in the Flash memory from accidental program or erase Three separ...

Page 690: ...dress Size Bytes Description 0xFF_FE00 0xFF_FE07 8 Backdoor Comparison Key Refer to Section 19 4 7 11 Verify Backdoor Access Key Command and Section 19 5 1 Unsecuring the MCU using Backdoor Key Access 0xFF_FE08 0xFF_FE091 2 Protection Override Comparison Key Refer to Section 19 4 7 17 Protection Override Command 0xFF_FE0A 0xFF_FE0B 1 1 0xFF_FE08 0xFF_FE0F form a Flash phrase and must be programmed...

Page 691: ... Unprotected Lower Region 1 2 4 8 KB 0xFF_8000 0xFF_9000 0xFF_8400 0xFF_8800 0xFF_A000 P Flash END 0xFF_FFFF 0xFF_F800 0xFF_F000 0xFF_E000 Flash Protected Unprotected Higher Region 2 4 8 16 KB Flash Protected Unprotected Region 8 KB up to 29 KB 16 bytes 0xFF_FE00 0xFF_FE0F Flash Protected Unprotected Region 96 KB P Flash START 0xFE_0000 Protection Protection Protection Movable End Fixed End Fixed ...

Page 692: ... 19 4 2 0x1F_C0B8 0x1F_C0BF 8 Reserved 0x1F_C0C0 0x1F_C0FF 64 Program Once Field Refer to Section 19 4 7 6 Program Once Command Table 19 6 Memory Controller Resource Fields NVM Resource Area 1 1 See Section 19 4 4 for NVM Resources Area description Global Address Size Bytes Description 0x1F_4000 0x1F_41FF 512 Reserved 0x1F_4200 0x1F_7FFF 15 872 Reserved 0x1F_8000 0x1F_97FF 6 144 Reserved 0x1F_9800...

Page 693: ...lash command execution for more detail see Caution note in Section 19 3 A summary of the Flash module registers is given in Figure 19 4 with detailed descriptions in the following subsections Address Name 7 6 5 4 3 2 1 0 0x0000 FCLKDIV R FDIVLD FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W 0x0001 FSEC R KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 W 0x0002 FCCOBIX R 0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX...

Page 694: ...S FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 W 0x0009 DFPROT R DPOPEN 0 0 0 DPS3 DPS2 DPS1 DPS0 W 0x000A FOPT R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 W 0x000B FRSV1 R 0 0 0 0 0 0 0 0 W 0x000C FCCOB0HI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x000D FCCOB0LO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x000E FCCOB1HI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x000F FCCOB1LO R...

Page 695: ...COB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x0012 FCCOB3HI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x0013 FCCOB3LO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x0014 FCCOB4HI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x0015 FCCOB4LO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x0016 FCCOB5HI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x0017 FCCO...

Page 696: ...ely divide BUSCLK down to 1 MHz to control timed events during Flash program and erase algorithms Table 19 8 shows recommended values for FDIV 5 0 based on the BUSCLK frequency Please refer to Section 19 4 5 Flash Command Operations for more information Table 19 8 FDIV values for various BUSCLK Frequencies BUSCLK Frequency MHz FDIV 5 0 BUSCLK Frequency MHz FDIV 5 0 MIN 1 MAX 2 MIN1 MAX2 1 0 1 6 0x...

Page 697: ...ing the Flash security byte during the reset sequence all bits in the FSEC register will be set to leave the Flash module in a secured state with backdoor key access disabled 18 6 19 6 0x12 44 6 45 6 0x2C 19 6 20 6 0x13 45 6 46 6 0x2D 20 6 21 6 0x14 46 6 47 6 0x2E 21 6 22 6 0x15 47 6 48 6 0x2F 22 6 23 6 0x16 48 6 49 6 0x30 23 6 24 6 0x17 49 6 50 6 0x31 24 6 25 6 0x18 25 6 26 6 0x19 1 BUSCLK is Gre...

Page 698: ...dule as shown in Table 19 10 5 2 RNV 5 2 Reserved Nonvolatile Bits The RNV bits should remain in the erased state for future enhancements 1 0 SEC 1 0 Flash Security Bits The SEC 1 0 bits define the security state of the MCU as shown in Table 19 11 If the Flash module is unsecured using backdoor key access the SEC bits are forced to 10 Table 19 10 Flash KEYEN States KEYEN 1 0 Status of Backdoor Key...

Page 699: ...ld Description 7 FPOVRD Flash Protection Override Status The FPOVRD bit indicates if the Protection Override feature is currently enabled See Section 19 4 7 17 Protection Override Command for more details 0 Protection is not overridden 1 Protection is overridden contents of registers FPROT and or DFPROT and effective protection limits determined by their current contents were determined during exe...

Page 700: ...ield to the unsecure state d release MCU security by setting the SEC field of the FSEC register to the unsecure state as defined in Table 19 9 of Section 19 3 2 2 The ERSAREQ bit sets to 1 when soc_erase_all_req is asserted CCIF 1 and the Memory Controller starts executing the sequence ERSAREQ will be reset to 0 by the Memory Controller when the operation is completed see Section 19 4 7 7 1 4 IGNS...

Page 701: ...ociated interrupt routine The FSFD bit is cleared by writing a 0 to FSFD 0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected 1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set see Section 19 3 2 7 and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is ...

Page 702: ...Flag The CCIF flag indicates that a Flash command has completed The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation 0 Flash command in progress 1 Flash command has completed 5 ACCERR Flash Access Error Flag The ACCERR bit indicates an illegal access has occurred to the Flash memory caused by either a violation of ...

Page 703: ...that was under a Flash command operation 1 The DFDF flag is cleared by writing a 1 to DFDF Writing a 0 to DFDF has no effect on DFDF 2 0 No double bit fault detected 1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command running See Section 19 4 3 Flash Block Read Access for details 1 In case of ECC errors the corresponding flag must be clear...

Page 704: ... set in the FSTAT register The block erase of a P Flash block is not possible if any of the P Flash sectors contained in the same P Flash block are protected Offset Module Base 0x0008 7 6 5 4 3 2 1 0 R FPOPEN RNV6 FPHDIS FPHS 1 0 FPLDIS FPLS 1 0 W Reset F 1 1 Loaded from Flash configuration field during reset sequence F1 F1 F1 F1 F1 F1 F1 Unimplemented or Reserved Figure 19 13 Flash Protection Reg...

Page 705: ...s Size The FPLS bits determine the size of the protected unprotected area in P Flash memory as shown in Table 19 22 The FPLS bits can only be written to while the FPLDIS bit is set Table 19 20 P Flash Protection Function FPOPEN FPHDIS FPLDIS Function 1 1 For range sizes refer to Table 19 21 and Table 19 22 1 1 1 No P Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Prote...

Page 706: ... 5 4 FPHS 1 0 FPLS 1 0 3 2 1 0 FPHS 1 0 FPLS 1 0 FPHDIS 1 FPLDIS 1 FPHDIS 1 FPLDIS 0 FPHDIS 0 FPLDIS 1 FPHDIS 0 FPLDIS 0 Scenario Scenario Unprotected region Protected region with size Protected region Protected region with size defined by FPLS defined by FPHS not defined by FPLS FPHS 0xFF_8000 0xFF_FFFF 0xFF_8000 0xFF_FFFF FLASH START FLASH START FPOPEN 1 FPOPEN 0 ...

Page 707: ...ot removed Writes must increase the DPS value and the DPOPEN bit can only be written from 1 protection disabled to 0 protection enabled If the DPOPEN bit is set the state of the DPS bits is irrelevant During the reset sequence fields DPOPEN and DPS of the DFPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0xFF_FE0D located ...

Page 708: ...ble if any of the EEPROM sectors are protected 19 3 2 11 Flash Option Register FOPT The FOPT register is the Flash option register Table 19 24 DFPROT Field Descriptions Field Description 7 DPOPEN EEPROM Protection Control 0 Enables EEPROM memory protection from program and erase with protected address range defined by DPS bits 1 Disables EEPROM memory protection from program and erase 3 0 DPS 3 0 ...

Page 709: ...er FRSV1 This Flash register is reserved for factory testing All bits in the FRSV1 register read 0 and are not writable 19 3 2 13 Flash Common Command Object Registers FCCOB The FCCOB is an array of six words Byte wide reads and writes are allowed to the FCCOB registers Offset Module Base 0x000A 7 6 5 4 3 2 1 0 R NV 7 0 W Reset F 1 1 Loaded from Flash configuration field during reset sequence F1 F...

Page 710: ...W Reset 0 0 0 0 0 0 0 0 Figure 19 19 Flash Common Command Object 0 Low Register FCCOB0LO Offset Module Base 0x000E 7 6 5 4 3 2 1 0 R CCOB 15 8 W Reset 0 0 0 0 0 0 0 0 Figure 19 20 Flash Common Command Object 1 High Register FCCOB1HI Offset Module Base 0x000F 7 6 5 4 3 2 1 0 R CCOB 7 0 W Reset 0 0 0 0 0 0 0 0 Figure 19 21 Flash Common Command Object 1 Low Register FCCOB1LO Offset Module Base 0x0010...

Page 711: ...W Reset 0 0 0 0 0 0 0 0 Figure 19 24 Flash Common Command Object 3 High Register FCCOB3HI Offset Module Base 0x0013 7 6 5 4 3 2 1 0 R CCOB 7 0 W Reset 0 0 0 0 0 0 0 0 Figure 19 25 Flash Common Command Object 3 Low Register FCCOB3LO Offset Module Base 0x0014 7 6 5 4 3 2 1 0 R CCOB 15 8 W Reset 0 0 0 0 0 0 0 0 Figure 19 26 Flash Common Command Object 4 High Register FCCOB4HI Offset Module Base 0x001...

Page 712: ... available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller The value written to the FCCOBIX field must reflect the amount of CCOB words loaded for command execution Table 19 27 shows the generic Flash command format The high byte of the first word in the CCOB array contains the command code followed by the parameters for this specific Flash com...

Page 713: ...1 with both 0b_0000 and 0b_1111 meaning none 19 4 3 Flash Block Read Access If data read from the Flash block results in a double bit fault ECC error meaning that data is detected to be in error and cannot be corrected the read data will be tagged as invalid during that access please look into the Reference Manual for details Forcing the DFDF status bit by setting FDFD see Section 19 3 2 5 has eff...

Page 714: ...eads the value of FPSTAT WSTATACK the new wait state configuration will be effective when it reads as 1 user must re write FCLKDIV to set a new value based on the lower frequency The following sequence must be followed on the contrary direction going from a lower frequency to a higher frequency user writes to FCNFG WSTAT to enable wait states user reads the value of FPSTAT WSTATACK the new wait st...

Page 715: ...FCLKDIV register has not been written any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set 19 4 5 2 Command Write Sequence The Memory Controller will launch all valid Flash commands entered using a command write sequence Before launching a command the ACCERR and FPVIOL bits in the FSTAT register must be clear s...

Page 716: ...r and Protection Violation Read FSTAT register START Check FCCOB ACCERR FPVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no FDIV Correct no Bit Polling for Command Completion Check yes CCIF Set to indicate number of parameters to be loaded Write to FCCOB register to load required command parameter yes no More Parameters Availability Check Results from previous Command Note FCLKDIV ...

Page 717: ...Command Unsecured Secured NS 1 1 Unsecured Normal Single Chip mode SS 2 2 Unsecured Special Single Chip mode NS 3 3 Secured Normal Single Chip mode SS 4 4 Secured Special Single Chip mode 0x01 Erase Verify All Blocks 0x02 Erase Verify Block 0x03 Erase Verify P Flash Section 0x04 Read Once 0x06 Program P Flash 0x07 Program Once 0x08 Erase All Blocks 0x09 Erase Flash Block 0x0A Erase P Flash Sector ...

Page 718: ...byte field in the nonvolatile information register in P Flash block that is allowed to be programmed only once 0x08 Erase All Blocks Erase all P Flash and EEPROM blocks An erase of all Flash blocks is only possible when the FPLDIS FPHDIS and FPOPEN bits in the FPROT register and the DPOPEN bit in the DFPROT register are set prior to launching the command 0x09 Erase Flash Block Erase a P Flash or E...

Page 719: ...reading Table 19 31 EEPROM Commands FCMD Command Function on EEPROM Memory 0x01 Erase Verify All Blocks Verify that all EEPROM and P Flash blocks are erased 0x02 Erase Verify Block Verify that the EEPROM block is erased 0x08 Erase All Blocks Erase all EEPROM and P Flash blocks An erase of all Flash blocks is only possible when the FPLDIS FPHDIS and FPOPEN bits in the FPROT register and the DPOPEN ...

Page 720: ...bed on Section 19 4 6 If the ACCERR or FPVIOL bits are set in the FSTAT register the user must clear these bits before starting any command write sequence see Section 19 3 2 7 CAUTION A Flash word or phrase must be in the erased state before being programmed Cumulative programming of bits within a Flash word or phrase is not allowed Table 19 32 Allowed P Flash and EEPROM Simultaneous Operations EE...

Page 721: ... launch the Erase Verify Block command the Memory Controller will verify that the selected P Flash or EEPROM block is erased The CCIF flag will set after the Erase Verify Block operation has completed If the block is not erased it means blank check failed both MGSTAT bits will be set Table 19 33 Erase Verify All Blocks Command FCCOB Requirements Register FCCOB Parameters FCCOB0 0x01 Not required T...

Page 722: ...s supplied see Table 19 3 FPVIOL None MGSTAT1 Set if any errors have been encountered during the read or if blank check failed MGSTAT0 Set if any non correctable errors have been encountered during the read or if blank check failed Table 19 37 Erase Verify P Flash Section Command FCCOB Requirements Register FCCOB Parameters FCCOB0 0x03 Global address 23 16 of a P Flash block FCCOB1 Global address ...

Page 723: ...attempt to read addresses within P Flash block will return invalid data 8 19 4 7 5 Program P Flash Command The Program P Flash operation will program a previously erased phrase in the P Flash memory using an embedded algorithm CAUTION A P Flash phrase must be in the erased state before being programmed Cumulative programming of bits within a Flash phrase is not allowed Table 19 39 Read Once Comman...

Page 724: ...id code runaway Table 19 41 Program P Flash Command FCCOB Requirements Register FCCOB Parameters FCCOB0 0x06 Global address 23 16 to identify P Flash block FCCOB1 Global address 15 0 of phrase location to be programmed 1 1 Global address 2 0 must be 000 FCCOB2 Word 0 program value FCCOB3 Word 1 program value FCCOB4 Word 2 program value FCCOB5 Word 3 program value Table 19 42 Program P Flash Comman...

Page 725: ... space and verify that it is erased If the Memory Controller verifies that the entire Flash memory space was properly erased security will be released During the execution of this command CCIF 0 the user must not write to any Flash module register The CCIF flag will set after the Erase All Blocks operation has completed FCCOB3 Program Once word 1 value FCCOB4 Program Once word 2 value FCCOB5 Progr...

Page 726: ...e see Section 19 3 2 2 The security byte in the Flash Configuration Field will be programmed to the unsecure state see Table 19 9 The status of the erase all request is reflected in the ERSAREQ bit in the FCNFG register see Section 19 3 2 5 The ERSAREQ bit in FCNFG will be cleared once the operation has completed and the normal FSTAT error reporting will be available as described inTable 19 47 At ...

Page 727: ...sh Block Command FCCOB Requirements Register FCCOB Parameters FCCOB0 0x09 Global address 23 16 to identify Flash block FCCOB1 Global address 15 0 in Flash block to be erased Table 19 49 Erase Flash Block Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available in current mode see Table 19 29 Set if an invalid global...

Page 728: ... Access Key command releases security if user supplied keys match those stored in the Flash security bytes of the Flash configuration field see Table 19 Table 19 51 Erase P Flash Sector Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available in current mode see Table 19 29 Set if an invalid global address 23 0 is s...

Page 729: ... Access Key command are aborted set ACCERR until a reset occurs The CCIF flag is set after the Verify Backdoor Access Key operation has completed 19 4 7 12 Set User Margin Level Command The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P Flash or EEPROM block Table 19 54 Verify Backdoor Access Key Command FCCOB Requirements Reg...

Page 730: ...lash memory contents have adequate margin for normal level read operations If unexpected results are encountered when checking Flash memory contents at user margin levels a potential loss of information has been detected FCCOB2 Margin level setting Table 19 57 Valid Set User Margin Level Settings FCCOB2 Level Description 0x0000 Return to Normal Level 0x0001 User Margin 1 Level 1 1 Read margin to t...

Page 731: ...OM reads However when the P Flash block is targeted the P Flash field margin levels are applied to both P Flash and EEPROM reads It is not possible to apply field margin levels to the P Flash block only Valid margin level settings for the Set Field Margin Level command are defined in Table 19 60 Table 19 59 Set Field Margin Level Command FCCOB Requirements Register FCCOB Parameters FCCOB0 0x0E Glo...

Page 732: ... the number of words Upon clearing CCIF to launch the Erase Verify EEPROM Section command the Memory Controller will verify the selected section of EEPROM memory is erased The CCIF flag will set after the Erase Verify EEPROM Section operation has completed If the section is not erased it means blank check failed both MGSTAT bits will be set Table 19 61 Set Field Margin Level Command Error Handling...

Page 733: ...k The CCIF flag is set when the operation has completed Table 19 63 Erase Verify EEPROM Section Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if command not available in current mode see Table 19 29 Set if an invalid global address 23 0 is supplied Set if a misaligned word address is supplied global address 0 0 Set if the request...

Page 734: ... end of the EEPROM block FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation MGSTAT0 Set if any non correctable errors have been encountered during the verify operation Table 19 66 Erase EEPROM Sector Command FCCOB Requirements Register FCCOB Parameters FCCOB0 0x12 Global address 23 16 to identify EEPROM bloc...

Page 735: ... s loaded on FCCOB parameters The new values loaded into FPROT and or DFPROT can reconfigure protection without any restriction by increasing decreasing or disabling protection limits If the command executes successfully the FPSTAT FPOVRD bit will set If the comparison key does not match the key programmed in the Flash Configuration Field or if the key loaded on FCCOB is 16 hFFFF the value of regi...

Page 736: ...ompleted or when a Flash command operation has detected an ECC fault NOTE Vector addresses and their relative interrupt priority are determined at the MCU level Table 19 70 Protection Override Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 010 or 011 at command launch Set if command not available in current mode see Table 19 29 Set if protection is sup...

Page 737: ...t via the CCIF interrupt see Section 19 4 8 Interrupts 19 4 10 Stop Mode If a Flash command is active CCIF 0 when the MCU requests stop mode the current Flash operation will be completed before the MCU is allowed to enter stop mode 19 5 Security The Flash module provides security information to the MCU The Flash security state is defined by the SEC bits of the FSEC register see Table 19 11 During ...

Page 738: ... 11 2 If the Verify Backdoor Access Key command is successful the MCU is unsecured and the SEC 1 0 bits in the FSEC register are forced to the unsecure state of 10 The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will prohibit future use of the Verify Backdoor Access Key command A reset of the MCU is the only method to re enable the Verify Backdoor Ac...

Page 739: ...equence to program the Flash security byte to the unsecured state 8 Reset the MCU 19 5 3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 19 29 19 6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the F...

Page 740: ...Chapter 19 128 KB Flash Module S12ZFTMRZ128K512V2 MC9S12ZVM Family Reference Manual Rev 1 3 740 Freescale Semiconductor ...

Page 741: ...is shown in the column labeled C in the parameter tables where appropriate P These parameters are guaranteed during production testing on each individual device M These parameters are characterized at 175 C and tested in production over an ambient temperature range of 40 C to 150 C with appropriate guardbanding to guarantee operation at 175 C C These parameters are achieved in design characterizat...

Page 742: ...ated by on chip voltage regulator VDDF 2 8 V 2 8V flash supply voltage generated by on chip voltage regulator VDDX1 1 1 All VDDX pins are internally connected by metal NOTE VDDA is connected to VDDX pins by diodes for ESD protection such that VDDX must not exceed VDDA by more than a diode voltage drop VSSA and VSSX are connected by anti parallel diodes for ESD protection 5 0 V 5V power supply outp...

Page 743: ...o the power and ground pins VSUP VDDX VSSX and VSSA Px represents any 5 V GPIO pin Assume Px is configured as an input The pad driver transistors P1 and N1 are switched off high impedance If the voltage Vin on Px is greater than VDDX a positive injection current Iin will flow through diode D1 into VDDX node If this injection current Iin is greater than ILoad the internal power supply VDDX may go o...

Page 744: ...de Drain VHD 0 3 42 V 6 FET Predriver Bootstrap Capacitor Connection VVBS 0 3 42 V 7 FET Predriver High Side Gate 1 VHG 5 42 V 8 FET Predriver High Side Source 1 VHS 5 42 V 9 Generated FET Predriver Low Side Supply VVLS_OUT 0 3 42 V 10 FET Predriver Low Side Supply Inputs VVLS 0 3 42 V 11 FET Predriver Low Side Gate 1 VLG 5 42 V 12 FET Predriver Low Side Source 1 VLS 5 42 V 13 FET Predriver Charge...

Page 745: ...ice to increase the track length to the BST pin 28 Storage temperature range T stg 65 155 C 1 Negative limit for pulsed operation only 2 VDDX and VDDA must be shorted 3 EXTAL XTAL pins configured for external oscillator operation only 4 All digital I O pins are internally clamped to VSSX and VDDX or VSSA and VDDA Table A 3 ESD and Latch up Test Conditions Model Spec Description Symbol Value Unit H...

Page 746: ...egative ILAT 100 100 mA 7 C Latch up Current of 5V GPIOs at 27 C positive negative ILAT 200 200 mA 8 C Latch up Current VCP BST LIN HD HS HG LG LS T 27 C positive negative ILAT 200 200 mA Table A 5 Recommended Capacitor Values nominal component values Num Characteristic Symbol Typical Unit 1 VDDX decoupling capacitor 1 2 1 X7R ceramic 2 One capacitor per VDDX pin CVDDX1 2 100 220 nF 2 VDDA decoupl...

Page 747: ...owever some electrical parameters are specified only in the range above 4 5 V VSUP 3 5 12 40 V 2 Voltage difference VDDX to VDDA VDDX 0 1 0 1 V 3 Voltage difference VSSX to VSSA VSSX 0 1 0 1 V 4 Oscillator fosc 4 16 MHz 5 Bus frequency 2 40 C Tj 150 C 150 C Tj 175 C Temp option W only 2 The flash program and erase operations must configure fNVMOP as specified in the NVM electrical section fbus 4 4...

Page 748: ...ponent Description PVSUP VSUP ISUP Internal Power through VSUP pin PBCTL VBCTL IBCTL Internal Power through BCTL pin PINT VDDX IVDDX VDDA IVDDA Internal Power through VDDX A pins PGPIO VI O II O Power dissipation of external load driven by GPIO Port Assuming the load is connected between GPIO and ground This power component is included in PINT and is subtracted from overall MCU power dissipation P...

Page 749: ...4LQFP EP double sided PCB 3 with 2 internal planes Natural Convection θJA 30 C W 10 D Thermal resistance 64LQFP EP single sided PCB 3 200 ft min θJA 51 C W 11 D Thermal resistance 64LQFP EP double sided PCB 3 with 2 internal planes 200 ft min 3 Junction to ambient thermal resistance θJA was simulated to be equivalent to the JEDEC specification JESD51 6 with the board JESD51 7 horizontal θJA 24 C W...

Page 750: ...rface of the board near the package 5 Thermal resistance between the die and the case top surface as measured by the cold plate method MIL SPEC 883 Method 1012 1 6 Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any interface resistance 7 Thermal characterization parameter indicating the temperature difference between package top and t...

Page 751: ...5 C I in 1 1 µA 7 M Output high voltage All GPIO except EVDD1 IOH 4 mA V OH VDDX 0 8 V 8a M Output high voltage EVDD1 VDDX 4 85V Partial Drive IOH 2 mA Full Drive IOH 20mA V OH VDDX 0 8 V 8b C Output high voltage EVDD1 VDDX 4 85V Full Drive IOH 10mA V OH VDDX 0 1 V 9 M Output low voltage All GPIO except EVDD1 IOL 4mA V OL 0 8 V 10 M Output low voltage EVDD1 Partial drive IOL 2mA or Full drive IOL ...

Page 752: ...y the application should avoid current injection into pin HS0 and HG0 during ADC conversions This can be achieved by correct synchronization of ADC and FET switching Table A 10 Pin Timing Characteristics Junction Temperature From 40 C To 175 C Conditions are 4 5 V VDDX 5 5 V unless otherwise noted I O Characteristics for all GPIO pins defined in A 1 2 1 A 742 Num C Rating Symbol Min Typ Max Unit 1...

Page 753: ...d SPI Configured to master mode continuously transmit data 0x55 at 1Mbit s ADC The peripheral is configured to operate at its maximum specified frequency and to continuously convert voltages on a single input channel MSCAN Configured in loop back mode with a bit rate of 500kbit s DBG The module is disabled as in typical final applications PTU The module is enabled bits TG1EN and TG0EN are set PTUF...

Page 754: ...nit 1 P Run Current 40 C TJ 150 C fbus 50MHz ISUPR 53 66 mA 2 P Wait Current 40 C TJ 150 C fbus 50MHz ISUPW 42 50 mA 3 M Run Current TJ 175 C fbus 40MHz ISUPR 45 55 mA 4 M Wait Current TJ 175 C fbus 40MHz ISUPW 36 45 mA Table A 15 Stop Current Characteristics Conditions are VSUP 12 V Num C Rating 1 1 If MCU is in STOP long enough then TA TJ Die self heating due to stop current can be ignored Symbo...

Page 755: ...ment Conditions Description Symbol Max Unit Regulator Supply Voltage at VSUP VSUP 5 V Supply Voltage at VDDX and VDDA VDDX A 5 V ADC reference voltage high VRH 5 V ADC reference voltage low VRL 0 V ADC clock fATDCLK 2 MHz ADC sample time tSMP 4 ADC clock cycles Bus clock frequency fbus 48 MHz Junction temperature Tj 40 and 150 C ...

Page 756: ...Appendix A MCU Electrical Specifications MC9S12ZVM Family Reference Manual Rev 1 3 756 Freescale Semiconductor ...

Page 757: ...4 50 3 13 2 5 5 0 5 0 5 5 5 15 5 15 5 15 5 75 V V V V 4b M Output Voltage VDDX without external PNP 1 Full Performance Mode VSUP 6V Full Performance Mode 5 5V VSUP 6V Full Performance Mode 3 5V VSUP 5 5V Reduced Performance Mode stop VSUP 3 5V VDDX 4 80 4 50 3 13 2 5 4 95 4 95 5 5 5 10 5 10 5 10 5 75 V V V V 5a P Load Current VDDX 2 3 without external PNP Full Performance Mode VSUP 6V 40 C TJ 150 ...

Page 758: ...AX 2 3 mA 18b C Max Base Current For External PNP VDDC 10 150 C TJ 175 C IBCTLCMAX 1 5 mA 19 D Recovery time from STOP tSTP_REC 23 µs 1 External PNP regulator has a higher regulation point to ensure that the current flows through the PNP when the application fails to disable the internal regulator byclearing INTXON 2 Please note that the core current is derived from VDDX 3 Further limitation may a...

Page 759: ...ncy factory trimmed fIRC1M_TRIM 0 9895 1 1 0145 MHz 1b M Junction Temperature 150 to 175 Celsius 1 Internal Reference Frequency factory trimmed 1 Full characterization not complete fIRC1M_TRIM 0 9855 1 1 0145 MHz Num C Rating Symbol Min Typ Max Unit 1 C Nominal crystal or resonator frequency fOSC 4 0 20 MHz 2 M Startup Current iOSC 100 µA 3a C Oscillator start up time 4MHz 1 1 These values apply f...

Page 760: ... tnom is at its maximum for one clock period and decreases towards zero for larger number of clock periods N Defining the jitter as The following equation is a good fit for the maximum jitter Figure B 2 Maximum Bus Clock Jitter Approximation N number of bus cycles 2 3 N 1 N 1 0 tnom tmax1 tmin1 tmaxN tminN J N max 1 t max N N t nom 1 t min N N t nom J N j1 N POSTDIV 1 1 5 10 20 N J N ...

Page 761: ... unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 D VCO frequency during system reset fVCORST 8 32 MHz 2 C VCO locking range fVCO 32 64 MHz 3 C Reference Clock fREF 1 MHz 4 D Lock Detection Lock 0 1 5 1 1 deviation from target frequency 5 D Un Lock Detection unl 0 5 2 5 1 7 C Time to lock tlock 150 256 fREF µs 8a C Jitter fit parameter 1 2 40 C TJ 150 C 2 fREF 1MHz fBUS 50MHz j1 2 8b ...

Page 762: ...Appendix B CPMU Electrical Specifications VREG OSC IRC PLL MC9S12ZVM Family Reference Manual Rev 1 3 762 Freescale Semiconductor ...

Page 763: ... A further factor is that PortAD pins that are configured as output drivers switching Supply voltage 4 5 V VDDA 5 5 V Junction Temperature From 40o C To 175o C Num C Rating Symbol Min Typ Max Unit 1 D Reference potential Low High VRL VRH VSSA VDDA 2 VDDA 2 VDDA V V 2 D Voltage difference VDDX to VDDA VDDX 0 1 0 0 1 V 3 D Voltage difference VSSX to VSSA VSSX 0 1 0 0 1 V 4 C Differential reference v...

Page 764: ... or operating conditions are less than worst case or leakage induced error is acceptable larger values of source resistance of up to 10Kohm are allowed C 1 1 3 Source Capacitance When sampling an additional internal capacitor is switched to the input This can cause a voltage drop due to charge sharing with the external and the pin capacitance For a maximum sampling error of the input voltage 1LSB ...

Page 765: ...3b D Input internal Resistance Junction temperature from 150o C to 175o C RINA 12 kΩ 4 T Disruptive analog input current INA 2 5 2 5 mA 5 T Coupling ratio positive current injection Kp 1E 4 A A 6 T Coupling ratio negative current injection Kn 5E 3 A A PAD00 PAD08 VDDA VSSA Tjmax 150o C Ileakp 1µA Ileakn 1µA Cbottom 3 7pF S H Cap 6 2pF incl parasitics 920Ω RINA 12KΩ incl parasitics direct sampling ...

Page 766: ...cluding any errors due to current injection input capacitance and source resistance C 1 2 1 ADC Accuracy Definitions For the following definitions see also Figure C 2 Differential non linearity DNL is defined as the difference between two adjacent switching steps The integral non linearity INL is defined as the sum of all DNLs DNL i V i V i 1 1LSB 1 INL n DNL i i 1 n V n V 0 1LSB n ...

Page 767: ...s 1 5 Vin mV 10 15 20 25 30 35 40 85 90 95 100 105 110 115 120 65 70 75 80 60 0 3 2 5 4 7 6 45 3F7 3F9 3F8 3FB 3FA 3FD 3FC 3FE 3FF 3F4 3F6 3F5 8 9 1 2 FF FE FD 3F3 10 Bit Resolution 8 Bit Resolution Ideal Transfer Curve 10 Bit Transfer Curve 8 Bit Transfer Curve 55 10 Bit Absolute Error Boundary 8 Bit Absolute Error Boundary LSB Vi 1 Vi DNL 5000 ...

Page 768: ...2 1 2 counts 8 C Absolute Error 10 Bit AE 3 2 3 counts 9 C Resolution 8 Bit LSB 20 mV 10 C Differential Nonlinearity 8 Bit DNL 0 5 0 3 0 5 counts 11 C Integral Nonlinearity 8 Bit INL 1 0 5 1 counts 12 C Absolute Error 8 Bit AE 1 5 1 1 5 counts Supply voltage VDDA 5 12 V VREF VRH VRL 5 12 V fADCCLK 8 0 MHz The values are tested to be valid with no PortAD output drivers switching simultaneous with c...

Page 769: ...AX 3 At temperatures above 25 C the current may be naturally limited by the driver in this case the limitation circuit is not engaged and the flag is not set ILIN_LIM 40 200 mA 3 M Input leakage current in dominant state VLIN 0V VLINSUP 12V ILIN_PAS_dom 1 mA 4 M Input leakage current in recessive state 8V VLINSUP 18V 8V VLIN 18V VLIN VLINSUP ILIN_PAS_rec 20 µA 5 T Input leakage current when ground...

Page 770: ...LAYER DRIVER CHARACTERISTICS FOR NOMINAL SLEW RATE 20 0KBIT S 5 T Rising falling edge time min to max max to min trise 6 5 µs 6 T Over current masking window IRC trimmed at 1MHz tOCLIM 15 16 µs 7 M Duty cycle 1 THRec max 0 744 x VLINSUP THDom max 0 581 x VLINSUP VLINSUP 7 0V 18V tBit 50us D1 tBus_rec min 2 x tBit D1 0 396 8 M Duty cycle 2 THRec min 0 422 x VLINSUP THDom min 0 284 x VLINSUP VLINSUP...

Page 771: ... T Over current masking window IRC trimmed at 1MHz tOCLIM 5 6 µs 1 For 3 5V VLINSUP 7V the LINPHY is still working but with degraded parametrics Characteristics noted under conditions 7V V LINSUP 18 V unless otherwise noted 1 Typical values noted reflect the approximate parameter mean at TA 25 C under nominal conditions unless otherwise noted Num C Ratings Symbol Min Typ Max Unit ...

Page 772: ...Appendix D LINPHY Electrical Specifications MC9S12ZVM Family Reference Manual Rev 1 3 772 Freescale Semiconductor ...

Page 773: ...0 mA 12a M VLS low voltage monitor trippoint assert VLVLSA 6 2 6 5 7 V 12b M VLS low voltage monitor trippoint deassert VLVLSD 6 2 6 58 7 V 13a M HD high voltage monitor assert trippoint low VHVHDLA 20 21 22 V 13b M HD high voltage monitor deassert trippoint low VHVHDLD 19 5 20 5 21 6 V 14a M HD high voltage monitor assert trippoint high VHVHDHA 26 6 28 3 29 4 V 14b M HD high voltage monitor deass...

Page 774: ... Current Sense Amplifier open loop gain AVCSA 100000 37 C Current Sense Amplifier common mode rejection ratio CMRRCSA 400 38 M Current Sense Amplifier input offset VCSAoff 15 15 mV 39 C Max effective Current Sense Amplifier output resistance 0 1V VDDA 0 2V RCSAout 2 Ω 40 C Min Current Sense Amplifier output current 0 1V VDDA 0 2V 13 ICSAout 750 750 µΑ 41 D Current Sense Amplifier large signal sett...

Page 775: ...V to 9V HGx LGx vs HSx LSx 8 VBSx HSx 10V respectively VLSx 10V measured from 9V to 1V HGx LGx vs HSx LSx 9 V VBSx V VLSx 9V resp VLSx 9V 10 V VBSx V VLSx 9V resp VLSx 9V nmos branch only 11 V VBSx V VLSx 9V resp VLSx 9V pmos branch only 12 VLS 6V 13 Output current range for which the effective output resistance specification applies 14 Av 10 no frequency compensation in feedback network 90 output...

Page 776: ...Appendix E GDU Electrical Specifications MC9S12ZVM Family Reference Manual Rev 1 3 776 Freescale Semiconductor ...

Page 777: ...ny means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum When attempting to program or erase the NVM module at a lower frequency a full program or erase transition is not assured The following sections provide equations which can be used to determine the time required to execute specific flash commands All timing paramete...

Page 778: ...9 62 481 00 us 8 D Program P Flash 4 Word 164 3077 tPGM_4 0 22 0 23 0 41 12 51 ms 9 D Program Once 164 3054 tPGMONCE 0 22 0 23 0 23 3 26 ms 10 D Erase All Blocks5 6 100066 34223 tERSALL 95 99 100 75 101 43 193 53 ms 11 D Erase Flash Block Pflash 5 100060 33681 tERSBLK_P 95 97 100 73 101 41 192 44 ms 12 D Erase Flash Block EEPROM 6 100060 1154 tERSBLK_D 95 32 100 08 100 11 127 38 ms 13 D Erase P Fl...

Page 779: ... 481 00 us 8 D Program P Flash 4 Word 164 3077 tPGM_4 0 23 0 24 0 47 12 51 ms 9 D Program Once 164 3054 tPGMONCE 0 23 0 24 0 24 3 26 ms 10 D Erase All Blocks5 6 100066 34223 tERSALL 96 16 100 92 101 78 193 53 ms 11 D Erase Flash Block Pflash 5 100060 33681 tERSBLK_P 96 14 100 90 101 74 192 44 ms 12 D Erase Flash Block EEPROM 6 100060 1154 tERSBLK_D 95 32 100 09 100 12 127 38 ms 13 D Erase P Flash ...

Page 780: ...f TJavg 85 C 1 after up to 10 000 program erase cycles 1 TJavg does not exceed 85 C in a typical temperature profile over the lifetime of a consumer industrial or automotive application tNVMRET 20 100 2 2 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de rated to 25 C using the Arrhenius equation For additional information on how ...

Page 781: ...ed on VSUP pin VLBI2_A VLBI2_D VLBI2_H 6 6 75 0 4 7 25 7 75 V V V 3 M M C Low Voltage Warning LBI 3 Assert Measured on VSUP pin falling edge Deassert Measured on VSUP pin rising edge Hysteresis measured on VSUP pin VLBI3_A VLBI3_D VLBI3_H 7 7 75 0 4 8 5 9 V V V 4 M M C Low Voltage Warning LBI 4 Assert Measured on VSUP pin falling edge Deassert Measured on VSUP pin rising edge Hysteresis measured o...

Page 782: ...c Electrical Characteristics BATS Characteristics noted under conditions 5 5V VSUP 18 V unless otherwise noted Typical values noted reflect the approximate parameter mean at TA 25 C 1 under nominal conditions 1 TA Ambient Temperature Num C Ratings Symbol Min Typ Max Unit 1 D Enable Uncertainty Time TEN_UNC 1 us 2 D Voltage Warning Low Pass Filter fVWLP_filter 0 5 Mhz ...

Page 783: ...I Master Timing CPHA 0 In Figure H 3 the timing diagram for master mode with transmission format CPHA 1 is depicted Figure H 1 Measurement Conditions Description Value Unit Drive mode full drive mode Load capacitance CLOAD 1 on all outputs 1 Timing specified for equal load on all SPI output pins Avoid asymmetric load 50 pF Thresholds for delay measurement points 35 65 VDDX V SCK OUTPUT SCK OUTPUT ...

Page 784: ... Enable Lead Time tlead 1 2 tsck 3 D Enable Lag Time tlag 1 2 tsck 4 D Clock SCK High or Low Time twsck 1 2 tsck 5 D Data Setup Time Inputs tsu 4 ns 6 D Data Hold Time Inputs thi 5 ns 9 D Data Valid after SCK Edge tvsck 10 ns 10 D Data Valid after SS fall CPHA 0 tvss 9 ns 11 D Data Hold Time Outputs tho 1 2 ns 12 D Rise and Fall Time Inputs trfi 8 ns 13 D Rise and Fall Time Outputs trfo 8 ns SCK O...

Page 785: ... see SPI Block Guide derates with increasing fbus please see Figure H 4 H 1 1 Slave Mode In Figure H 1 the timing diagram for slave mode with transmission format CPHA 0 is depicted Figure H 5 SPI Slave Timing CPHA 0 1 2 1 4 fSCK fbus fbus MHz 10 20 30 40 15 25 35 5 SCK INPUT SCK INPUT MOSI INPUT MISO OUTPUT SS INPUT 1 9 5 6 MSB IN BIT 6 1 LSB IN SLAVE MSB SLAVE LSB OUT BIT 6 1 11 4 4 2 7 CPOL 0 CP...

Page 786: ... Setup Time Inputs tsu 3 ns 6 D Data Hold Time Inputs thi 2 ns 7 D Slave Access Time time to data active ta 28 ns 8 D Slave MISO Disable Time tdis 26 ns 9a D Data Valid after SCK Edge 40 C Tj 150 C tvsck 2 2 0 5tbus added due to internal synchronization delay ns 9b D Data Valid after SCK Edge 150 C Tj 175 C 1 tvsck 2 ns 10a D Data Valid after SS fall 40 C Tj 150 C tvss 2 ns 10b D Data Valid after ...

Page 787: ...al Specifications Table I 1 MSCAN Wake up Pulse Characteristics Junction Temperature From 40 C To 175 C Conditions are 4 5 V VDDX 5 5 V unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 M MSCAN wake up dominant pulse filtered tWUP 1 5 µs 2 M MSCAN wake up dominant pulse pass tWUP 5 µs ...

Page 788: ...Appendix I MSCAN Electrical Specifications MC9S12ZVM Family Reference Manual Rev 1 3 788 Freescale Semiconductor ...

Page 789: ...Appendix J Package Information MC9S12ZVM Family Reference Manual Rev 1 3 Freescale Semiconductor 789 Appendix J Package Information Figure J 1 64LQFP EP Mechanical Information ...

Page 790: ...Appendix J Package Information MC9S12ZVM Family Reference Manual Rev 1 3 790 Freescale Semiconductor ...

Page 791: ...v 1 3 Freescale Semiconductor 791 Freescale s Package Reflow capability meets Pb free requirements for JEDEC standard J STD 020C For Peak Package Reflow Temperature and Moisture Sensitivity Levels MSL Go to www freescale com search by part number and review parametrics ...

Page 792: ...umber NOTES Not every combination is offered Table 1 2 1 lists available derivatives The mask identifier suffix and the Tape Reel suffix are always both omitted from the partnumber which is actually marked on the device S 9 12Z VM L 12 F0 M KH R Package Option Temperature Option Device Title Controller Family V 40 C to 105 C KH 64LQFP EP Status Partnumber type S or SC Maskset specific partnumber M...

Page 793: ...how the detailed register map of the MC9S12ZVM Family NOTE Smaller derivatives within the MC9S12ZVM Family feature a subset of the listed modules L 1 0x0000 0x0003 Part ID Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0000 PARTID0 R 0 0 0 0 0 0 0 0 W 0x0001 PARTID1 R 0 0 0 1 0 1 1 1 W 0x0002 PARTID2 R 0 0 0 0 0 0 0 0 W 0x0003 PARTID3 R Revision Dependent W ...

Page 794: ...W 0x0018 INT_CFDATA0 R 0 0 0 0 0 PRIOLVL 2 0 W 0x0019 INT_CFDATA1 R 0 0 0 0 0 PRIOLVL 2 0 W 0x001A INT_CFDATA2 R 0 0 0 0 0 PRIOLVL 2 0 W 0x001B INT_CFDATA3 R 0 0 0 0 0 PRIOLVL 2 0 W 0x001C INT_CFDATA4 R 0 0 0 0 0 PRIOLVL 2 0 W 0x001D INT_CFDATA5 R 0 0 0 0 0 PRIOLVL 2 0 W 0x001E INT_CFDATA6 R 0 0 0 0 0 PRIOLVL 2 0 W 0x001F INT_CFDATA7 R 0 0 0 0 0 PRIOLVL 2 0 W Address Name Bit 7 6 5 4 3 2 1 Bit 0 0...

Page 795: ...0 0 0 0 W L 4 0x0100 0x017F S12ZDBG Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x0100 DBGC1 R ARM 0 reserved BDMBP BRKCPU reserved EEVE W TRIG 0x0101 DBGC2 R 0 0 0 0 CDCM ABCM W 0x0102 DBGTCRH R reserved TSOURCE TRANGE TRCMOD TALIGN W 0x0103 DBGTCRL R 0 0 0 0 DSTAMP PDOE PROFILE STAMP W 0x0104 DBGTBH R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x0105 DBGTBL R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ...

Page 796: ... COMPE W 0x0111 0x0114 Reserved R 0 0 0 0 0 0 0 0 W 0x0115 DBGAAH R DBGAA 23 16 W 0x0116 DBGAAM R DBGAA 15 8 W 0x0117 DBGAAL R DBGAA 7 0 W 0x0118 DBGAD0 R Bit 31 30 29 28 27 26 25 Bit 24 W 0x0119 DBGAD1 R Bit 23 22 21 20 19 18 17 Bit 16 W 0x011A DBGAD2 R Bit 15 14 13 12 11 10 9 Bit 8 W 0x011B DBGAD3 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x011C DBGADM0 R Bit 31 30 29 28 27 26 25 Bit 24 W 0x011D DBGADM1 R Bit...

Page 797: ...x0135 DBGCAH R DBGCA 23 16 W 0x0136 DBGCAM R DBGCA 15 8 W 0x0137 DBGCAL R DBGCA 7 0 W 0x0138 DBGCD0 R Bit 31 30 29 28 27 26 25 Bit 24 W 0x0139 DBGCD1 R Bit 23 22 21 20 19 18 17 Bit 16 W 0x013A DBGCD2 R Bit 15 14 13 12 11 10 9 Bit 8 W 0x013B DBGCD3 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x013C DBGCDM0 R Bit 31 30 29 28 27 26 25 Bit 24 W 0x013D DBGCDM1 R Bit 23 22 21 20 19 18 17 Bit 16 W 0x013E DBGCDM2 R Bit 1...

Page 798: ...al Rev 1 3 798 Freescale Semiconductor 0x0141 0x0144 Reserved R 0 0 0 0 0 0 0 0 W 0x0145 DBGDAH R DBGDA 23 16 W 0x0146 DBGDAM R DBGDA 15 8 W 0x0147 DBGDAL R DBGDA 7 0 W 0x0148 0x017F Reserved R 0 0 0 0 0 0 0 0 W L 4 0x0100 0x017F S12ZDBG Address Name Bit 7 6 5 4 3 2 1 Bit 0 ...

Page 799: ...served R 0 0 0 0 0 0 0 0 W 0x0208 ECLKCTL R NECLK 0 0 0 0 0 0 0 W 0x0209 IRQCR R IRQE IRQEN 0 0 0 0 0 0 W 0x020A PIMMISC R 0 0 0 0 0 0 OCPE1 0 W 0x020B 0x020D Reserved R 0 0 0 0 0 0 0 0 W 0x020E Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x020F Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x0210 0x025F Reserved R 0 0...

Page 800: ... PTADL7 PTADL6 PTADL5 PTADL4 PTADL3 PTADL2 PTADL1 PTADL0 W 0x0282 PTIADH R 0 0 0 0 0 0 0 PTIADH0 W 0x0283 PTIADL R PTIADL7 PTIADL6 PTIADL5 PTIADL4 PTIADL3 PTIADL2 PTIADL1 PTIADL0 W 0x0284 DDRADH R 0 0 0 0 0 0 0 DDRADH0 W 0x0285 DDRADL R DDRADL7 DDRADL6 DDRADL5 DDRADL4 DDRADL3 DDRADL2 DDRADL1 DDRADL0 W 0x0286 PERADH R 0 0 0 0 0 0 0 PERADH0 W 0x0287 PERADL R PERADL7 PERADL6 PERADL5 PERADL4 PERADL3 P...

Page 801: ...IFADL2 PIFADL1 PIFADL0 W 0x0290 0x0297 Reserved R 0 0 0 0 0 0 0 0 W 0x0298 DIENADH R 0 0 0 0 0 0 0 DIENADH0 W 0x0299 DIENADL R DIENADL7 DIENADL6 DIENADL5 DIENADL4 DIENADL3 DIENADL2 DIENADL1 DIENADL0 W 0x029A 0x02BF Reserved R 0 0 0 0 0 0 0 0 W 0x02C0 PTT R 0 0 0 0 PTT3 PTT2 PTT1 PTT0 W 0x02C1 PTIT R 0 0 0 0 PTIT3 PTIT2 PTIT1 PTIT0 W 0x02C2 DDRT R 0 0 0 0 DDRT3 DDRT2 DDRT1 DDRT0 W 0x02C3 PERT R 0 0...

Page 802: ...PPSS1 PPSS0 W 0x02D5 Reserved R 0 0 0 0 0 0 0 0 W 0x02D6 PIES R 0 0 PIES5 PIES4 PIES3 PIES2 PIES1 PIES0 W 0x02D7 PIFS R 0 0 PIFS5 PIFS4 PIFS3 PIFS2 PIFS1 PIFS0 W 0x02D8 0x02DE Reserved R 0 0 0 0 0 0 0 0 W 0x02DF WOMS R 0 0 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 W 0x02E0 0x02EF Reserved R 0 0 0 0 0 0 0 0 W 0x02F0 PTP R 0 0 0 0 0 PTP2 PTP1 PTP0 W 0x02F1 PTIP R 0 0 0 0 0 PTIP2 PTIP1 PTIP0 W 0x02F2 DDRP ...

Page 803: ...28K512 Address Name 7 6 5 4 3 2 1 0 0x0380 FCLKDIV R FDIVLD FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W 0x0381 FSEC R KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 W 0x0382 FCCOBIX R 0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0 W 0x0383 FPSTAT R FPOVRD 0 0 0 0 0 0 WSTAT ACK W 0x0384 FCNFG R CCIE 0 ERSAREQ IGNSF WSTAT 1 0 FDFD FSFD W 0x0385 FERCNFG R 0 0 0 0 0 0 0 SFDIE W 0x0386 FSTAT R CCIF 0 ACCERR FPVIOL M...

Page 804: ...CCOB2HI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x0391 FCCOB2LO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x0392 FCCOB3HI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x0393 FCCOB3LO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x0394 FCCOB4HI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x0395 FCCOB4LO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CC...

Page 805: ...C ECCDDH R DDATA 15 8 W 0x03CD ECCDDL R DDATA 7 0 W 0x03CE ECCDE R 0 0 DECC 5 0 W 0x03CF ECCDCMD R ECCDRR 0 0 0 0 0 ECCDW ECCDR W L 8 0x0500 x053F PMF15B6C Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x0500 PMFCFG0 R WP MTG EDGEC EDGEB EDGEA INDEPC INDEPB INDEPA W 0x0501 PMFCFG1 R 0 ENCE BOTNEGC TOPNEGC BOTNEGB TOPNEGB BOTNEGA TOPNEGA W 0x0502 PMFCFG2 R REV1 REV0 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 W 0x0503 PM...

Page 806: ...P3 QSMP2 QSMP1 QSMP0 W 0x050A 0x050B Reserved R 0 0 0 0 0 0 0 0 W 0x050C PMFOUTC R 0 0 OUTCTL5 OUTCTL4 OUTCTL3 OUTCTL2 OUTCTL1 OUTCTL0 W 0x050D PMFOUTB R 0 0 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 W 0x050E PMFDTMS R 0 0 DT5 DT4 DT3 DT2 DT1 DT0 W 0x050F PMFCCTL R 0 0 ISENS 0 IPOLC IPOLB IPOLA W 0x0510 PMFVAL0 R PMFVAL0 W 0x0511 PMFVAL0 R PMFVAL0 W 0x0512 PMFVAL1 R PMFVAL1 W 0x0513 PMFVAL1 R PMFVAL1 W 0x0514...

Page 807: ...51D PMFROIF R 0 0 0 0 0 PMFROIF C PMFROIF B PMFROIF A W 0x051E PMFICCTL R 0 0 PECC PECB PECA ICCC ICCB ICCA W 0x051F PMFCINV R 0 0 CINV5 CINV4 CINV3 CINV2 CINV1 CINV0 W 0x0520 PMFENCA R PWMENA GLDOKA 0 0 0 RSTRTA LDOKA PWMRIEA W 0x0521 PMFFQCA R LDFQA HALFA PRSCA PWMRFA W 0x0522 PMFCNTA R 0 PMFCNTA W 0x0523 PMFCNTA R PMFCNTA W 0x0524 PMFMODA R 0 PMFMODA W 0x0525 PMFMODA R PMFMODA W 0x0526 PMFDTMA ...

Page 808: ... PMFFQCB R LDFQB HALFB PRSCB PWMRFB W 0x052A PMFCNTB R 0 PMFCNTB W 0x052B PMFCNTB R PMFCNTB W 0x052C PMFMODB R 0 PMFMODB W 0x052D PMFMODB R PMFMODB W 0x052E PMFDTMB R 0 0 0 0 PMFDTMB W 0x052F PMFDTMB R PMFDTMB W 0x0530 PMFENCC R PWMENC GLDOKC 0 0 0 RSTRTC LDOKC PWMRIEC W 0x0531 PMFFQCC R LDFQC HALFC PRSCC PWMRFC W L 8 0x0500 x053F PMF15B6C Address Name Bit 7 6 5 4 3 2 1 Bit 0 ...

Page 809: ... W 0x0539 PMFDMP1 R DMP15 DMP14 DMP13 DMP12 DMP11 DMP10 W 0x053A PMFDMP2 R DMP25 DMP24 DMP23 DMP22 DMP21 DMP20 W 0x053B PMFDMP3 R DMP35 DMP34 DMP33 DMP32 DMP31 DMP30 W 0x053C PMFDMP4 R DMP45 DMP44 DMP43 DMP42 DMP41 DMP40 W 0x053D PMFDMP5 R DMP55 DMP54 DMP53 DMP52 DMP51 DMP50 W 0x053E PMFOUTF R 0 0 OUTF5 OUTF4 OUTF3 OUTF2 OUTF1 OUTF0 W 0x053F Reserved R 0 0 0 0 0 0 0 0 W L 9 0x0580 0x059F PTU Addre...

Page 810: ...IFL R TG1AEIF TG1REIF TG1TEIF TG1DIF TG0AEIF TG0REIF TG0TEIF TG0DIF W 0x0586 TG0LIST R 0 0 0 0 0 0 0 TG0LIST W 0x0587 TG0TNUM R 0 0 0 TG0TNUM 4 0 W 0x0588 TG0TVH R TG0TV 15 8 W 0x0589 TG0TVL R TG0TV 7 0 W 0x058A TG1LIST R 0 0 0 0 0 0 0 TG1LIST W 0x058B TG1TNUM R 0 0 0 TG1TNUM4 0 W 0x058C TG1TVH R TG1TV 15 8 W 0x058D TG1TVL R TG1TV 7 0 W 0x058E PTUCNTH R PTUCNT 15 8 W 0x058F PTUCNTL R PTUCNT 7 0 W ...

Page 811: ...F PTUDEBUG R 0 PTUREPE PTUT1PE PTUT0PE 0 0 0 0 W PTUFRE TG1FTE TG0FTE L 10 0x05C0 0x05FF TIM0 Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x05C0 TIM0TIOS R IOS3 IOS2 IOS1 IOS0 W 0x05C1 TIM0CFORC R 0 0 0 0 0 0 0 0 W FOC3 FOC2 FOC1 FOC0 0x05C2 Reserved R W 0x05C3 Reserved R W 0x05C4 TIM0TCNTH R TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 W 0x05C5 TIM0TCNTL R TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TC...

Page 812: ...15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x05D1 TIM0TC0L R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x05D2 TIM0TC1H R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x05D3 TIM0TC1L R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x05D4 TIM0TC2H R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x05D5 TIM0TC2L R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit ...

Page 813: ...C_CFG 1 0 STR_SEQ A MOD_CF G W 0x0601 ADC0CTL_1 R CSL_BMO D RVL_BMO D SMOD_AC C AUT_RST A 0 0 0 0 W 0x0602 ADC0STS R CSL_SEL RVL_SEL DBECC_E RR Reserved READY 0 0 0 W 0x0603 ADC0TIM R 0 PRS 6 0 W 0x0604 ADC0FMT R DJM 0 0 0 0 SRES 2 0 W 0x0605 ADC0FLWCTL R SEQA TRIG RSTA LDOK 0 0 0 0 W 0x0606 ADC0EIE R IA_EIE CMD_EIE EOL_EIE Reserved TRIG_EIE RSTAR_EI E LDOK_EIE 0 W 0x0607 ADC0IE R SEQAD_I E CONIF_...

Page 814: ...Reserved R Reserved 0 0 W 0x0614 ADC0CMD_0 R CMD_SEL 0 0 INTFLG_SEL 3 0 W 0x0615 ADC0CMD_1 R VRH_SEL VRL_SEL CH_SEL 5 0 W 0x0616 ADC0CMD_2 R SMP 4 0 0 0 Reserved W 0x0617 ADC0CMD_3 R Reserved Reserved Reserved W 0x0618 Reserved R Reserved W 0x0619 Reserved R Reserved W 0x061A Reserved R Reserved W 0x061B Reserved R Reserved W 0x061C ADC0CIDX R 0 0 CMD_IDX 5 0 W 0x061D ADC0CBP_0 R CMD_PTR 23 16 W 0...

Page 815: ...0 STR_SEQ A MOD_CF G W 0x0641 ADC1CTL_1 R CSL_BMO D RVL_BMO D SMOD_AC C AUT_RST A 0 0 0 0 W 0x0642 ADC1STS R CSL_SEL RVL_SEL DBECC_E RR Reserved READY 0 0 0 W 0x0643 ADC1TIM R 0 PRS 6 0 W 0x0644 ADC1FMT R DJM 0 0 0 0 SRES 2 0 W 0x0645 ADC1FLWCTL R SEQA TRIG RSTA LDOK 0 0 0 0 W 0x0646 ADC1EIE R IA_EIE CMD_EIE EOL_EIE Reserved TRIG_EIE RSTAR_EI E LDOK_EIE 0 W 0x0647 ADC1IE R SEQAD_I E CONIF_OI E Res...

Page 816: ...55 ADC1CMD_1 R VRH_SEL VRL_SEL CH_SEL 5 0 W 0x0656 ADC1CMD_2 R SMP 4 0 0 0 Reserved W 0x0657 ADC1CMD_3 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x0658 Reserved R Reserved W 0x0659 Reserved R Reserved W 0x065A Reserved R Reserved W 0x065B Reserved R Reserved W 0x065C ADC1CIDX R 0 0 CMD_IDX 5 0 W 0x065D ADC1CBP_0 R CMD_PTR 23 16 W 0x065E ADC1CBP_1 R CMD_PTR 15 8 W ...

Page 817: ...0x06BF GDU Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x06A0 GDUE R GWP 0 EPRES GCS1E GBOE GCS0E GCPE GFDE W 0x06A1 GDUCTR R GHHDLVL 0 GBKTIM2 3 0 GBKTIM1 1 0 W 0x06A2 GDUIE R 0 0 0 GOCIE 1 0 GDSEIE GHHDIE GLVLSIE W 0x06A3 GDUDSE R 0 GDHSIF 2 0 0 GDLSIF 2 0 W 0x06A4 GDUSTAT R GPHS 2 0 GOCS 1 0 GHHDS GLVLSS W 0x06A5 GDUSRC R 0 GSRCHS 2 0 0 GSRCLS 2 0 W 0x06A6 GDUF R GSUF GHHDF GLVLSF GOCIF 1 0 0 GHHDIF G...

Page 818: ...06DF CPMU Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x06C0 CPMU RESERVED00 R 0 0 0 0 0 0 0 0 W 0x06C1 CPMU RESERVED01 R 0 0 0 0 0 0 0 0 W 0x06C2 CPMU RESERVED02 R 0 0 0 0 0 0 0 0 W 0x06C3 CPMURFLG R 0 PORF LVRF 0 COPRF 0 OMRF PMRF W 0x06C4 CPMU SYNR R VCOFRQ 1 0 SYNDIV 5 0 W 0x06C5 CPMU REFDIV R REFFRQ 1 0 0 0 REFDIV 3 0 W 0x06C6 CPMU POSTDIV R 0 0 0 POSTDIV 4 0 W 0x06C7 CPMUIFLG R RTIF 0 0 LOCKIF LOCK...

Page 819: ... CPMU LVCTL R 0 0 0 0 0 LVDS LVIE LVIF W 0x06D2 CPMU APICTL R APICLK 0 0 APIES APIEA APIFE APIE APIF W 0x06D3 CPMUACLKT R R ACLKTR5 ACLKTR4 ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0 0 0 W 0x06D4 CPMUAPIRH R APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 W 0x06D5 CPMUAPIRL R APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0 W 0x06D6 RESERVED CPMUTEST3 R 0 0 0 0 0 0 0 0 W 0x06D7 CPMUHTTR R HTOE 0 0 0 HTT...

Page 820: ... 0 0 0 0 0 BVHIE BVLIE W 0x06F3 BATIF R 0 0 0 0 0 0 BVHIF BVLIF W 0x06F4 0x06F5 Reserved R 0 0 0 0 0 0 0 0 W 0x06F6 0x06F7 Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W L 16 0x0700 0x0707 SCI0 Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x0700 SCI0BDH1 R SBR15 SBR14 SBR13 SBR12 SBR11 SBR10 SBR9 SBR8 W 0x0701 SCI0BDL1 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W 0x070...

Page 821: ...I0SR1 R TDRE TC RDRF IDLE OR NF FE PF W 0x0705 SCI0SR2 R AMAP 0 0 TXPOL RXPOL BRK13 TXDIR RAF W 0x0706 SCI0DRH R R8 T8 0 0 0 0 0 0 W 0x0707 SCI0DRL R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 1 These registers are accessible if the AMAP bit in the SCISR2 register is set to zero 2 These registers are accessible if the AMAP bit in the SCISR2 register is set to one L 16 0x0700 0x0707 SCI0 Add...

Page 822: ...W 0x0713 SCI1CR2 R TIE TCIE RIE ILIE TE RE RWU SBK W 0x0714 SCI1SR1 R TDRE TC RDRF IDLE OR NF FE PF W 0x0715 SCI1SR2 R AMAP 0 0 TXPOL RXPOL BRK13 TXDIR RAF W 0x0716 SCI1DRH R R8 T8 0 0 0 0 0 0 W 0x0717 SCI1DRL R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 1 These registers are accessible if the AMAP bit in the SCISR2 register is set to zero 2 These registers are accessible if the AMAP bit in...

Page 823: ... BRP2 BRP1 BRP0 W 0x0803 CAN0BTR1 R SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 W 0x0804 CAN0RFLG R WUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF W 0x0805 CAN0RIER R WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE W 0x0806 CAN0TFLG R 0 0 0 0 0 TXE2 TXE1 TXE0 W 0x0807 CAN0TIER R 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 W 0x0808 CAN0TARQ R 0 0 0 0 0 ABTRQ2 ABTRQ1 ABTRQ0 W 0x0809 CAN0TAAK...

Page 824: ...N0RXFG R FOREGROUND RECEIVE BUFFER W 0x0830 0x083F CAN0TXFG R FOREGROUND TRANSMIT BUFFER W L 20 0x0980 0x0987 LINPHY0 Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x0980 LP0DR R 0 0 0 0 0 0 LPDR1 LPDR0 W 0x0981 LP0CR R 0 0 0 0 LPE RXONLY LPWUE LPPUE W 0x0982 Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x0983 LP0SLRM R LPDTDIS 0 0 0 0 0 LPSLR1 LPSLR0 W 0x0984 Reserv...

Page 825: ...lity including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including typicals must be validated for each customer application by customer s technical experts Freescale does not convey any licen...

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