Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Appendix L SPI Electrical Specifications
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 819
Figure L-3. Derating of maximum f
SCK
to f
bus
ratio in Master Mode
In Master Mode the allowed maximum f
SCK
to f
bus
ratio (= minimum Baud Rate Divisor, pls. see
SPI Block Guide) derates with increasing f
bus
, please see Figure L-3. .
L.2 Slave Mode
In Figure L-4. the timing diagram for slave mode with transmission format CPHA=0 is depicted.
1/2
1/4
f
SCK
/f
bus
f
bus
[MHz]
10 20 30 40
15 25 35 5