Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Appendix L SPI Electrical Specifications
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 817
Appendix L
SPI Electrical Specifications
This section provides electrical parametrics and ratings for the SPI.
In Table L-1. the measurement conditions are listed.
L.1 Master Mode
In Figure L-1. the timing diagram for master mode with transmission format CPHA=0 is depicted.
Figure L-1. SPI Master Timing (CPHA=0)
In Figure L-2. the timing diagram for master mode with transmission format CPHA=1 is depicted.
Table L-1. Measurement Conditions
Description Value Unit
Drive mode full drive mode —
Load capacitance C
LOAD
(1)
,
on all outputs
1. Timing specified for equal load on all SPI output pins. Avoid asymmetric load.
50 pF
Thresholds for delay
measurement points
(35% / 65%) VDDX V
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS
1
(OUTPUT)
1
9
5 6
MSB IN
2
BIT 6 . . . 1
LSB IN
MSB OUT
2
LSB OUT
BIT 6 . . . 1
11
4
4
2
10
(CPOL

0)
(CPOL

1)
3 13
13
1. If enabled.
2. LSBFE = 0. For LSBFE = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
12
12