Chapter 21 64 KB Flash Module (S12ZFTMRZ64K2KV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
731
Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will
check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory
Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the
Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash
configuration field with Key 0 compared to 0xFF_FE00, etc. If the backdoor keys match, security will be
released. If the backdoor keys do not match, security is not released and all future attempts to execute the
Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is
set after the Verify Backdoor Access Key operation has completed.
21.4.7.12 Set User Margin Level Command
The Set User Margin Level command causes the Memory Controller to set the margin level for future read
operations of the P-Flash or EEPROM block.
Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the
user margin level for the targeted block and then set the CCIF flag.
NOTE
When the EEPROM block is targeted, the EEPROM user margin levels are
applied only to the EEPROM reads. However, when the P-Flash block is
targeted, the P-Flash user margin levels are applied to both P-Flash and
EEPROM reads. It is not possible to apply user margin levels to the P-Flash
block only.
Valid margin level settings for the Set User Margin Level command are defined in
.
Table 21-55. Verify Backdoor Access Key Command Error Handling
Register
Error Bit
Error Condition
FSTAT
ACCERR
Set if CCOBIX[2:0] != 100 at command launch
Set if an incorrect backdoor key is supplied
Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see
Set if the backdoor key has mismatched since the last reset
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
Table 21-56. Set User Margin Level Command FCCOB Requirements
Register
FCCOB Parameters
FCCOB0
0x0D
Global address [23:16] to identify Flash
block
FCCOB1
Global address [15:0] to identify Flash block
FCCOB2
Margin level setting.