Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 5 Background Debug Controller (S12ZBDCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 143
5.1.3.3 Low-Power Modes
5.1.3.3.1 Stop Mode
The execution of the CPU STOP instruction leads to stop mode only when all bus masters (CPU, or others,
depending on the device) have finished processing. The operation during stop mode depends on the
ENBDC and BDCCIS bit settings as summarized in
Table 5-3
A disabled BDC has no influence on stop mode operation. In this case the BDCSI clock is disabled in stop
mode thus it is not possible to enable the BDC from within stop mode.
STOP Mode With BDC Enabled And BDCCIS Clear
If the BDC is enabled and BDCCIS is clear, then the BDC prevents the BDCCLK clock ( Figure 5-5 ) from
being disabled in stop mode. This allows BDC communication to continue throughout stop mode in order
to access the BDCCSR register. All other device level clock signals are disabled on entering stop mode.
NOTE
This is intended for application debugging, not for fast flash programming.
Thus the CLKSW bit must be clear to map the BDCSI to BDCCLK.
With the BDC enabled, an internal acknowledge delays stop mode entry and exit by 2 BDCSI clock + 2
bus clock cycles. If no other module delays stop mode entry and exit, then these additional clock cycles
represent a difference between the debug and not debug cases. Furthermore if a BDC internal access is
being executed when the device is entering stop mode, then the stop mode entry is delayed until the internal
access is complete (typically for 1 bus clock cycle).
Accesses to the internal memory map are not possible when the internal device clocks are disabled. Thus
attempted accesses to memory mapped resources are suppressed and the NORESP flag is set. Resources
can be accessed again by the next command received following exit from Stop mode.
A BACKGROUND command issued whilst in stop mode remains pending internally until the device
leaves stop mode. This means that subsequent active BDM commands, issued whilst BACKGROUND is
pending, set the ILLCMD flag because the device is not yet in active BDM.
If ACK handshaking is enabled, then the first ACK, following a stop mode entry is long to indicate a stop
exception. The BDC indicates a stop mode occurrence by setting the BDCCSR bit STOP. If the host
attempts further communication before the ACK pulse generation then the OVRUN bit is set.
Table 5-3. BDC STOP Operation Dependencies
ENBDC BDCCIS Description Of Operation
0 0 BDC has no effect on STOP mode.
0 1 BDC has no effect on STOP mode.
1 0 Only BDCCLK clock continues
1 1 All clocks continue