Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 5 Background Debug Controller (S12ZBDCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 151
When BDM is activated, the CPU finishes executing the current instruction. Thereafter only BDC
commands can affect CPU register contents until the BDC GO command returns from active BDM to user
code or a device reset occurs. When BDM is activated by a breakpoint, the type of breakpoint used
determines if BDM becomes active before or after execution of the next instruction.
NOTE
Attempting to activate BDM using a BGND instruction whilst the BDC is
disabled, the CPU requires clock cycles for the attempted BGND execution.
However BACKGROUND commands issued whilst the BDC is disabled
are ignored by the BDC and the CPU execution is not delayed.
5.4.3 Clock Source
The BDC clock source can be mapped to a constant frequency clock source or a PLL based fast clock. The
clock source for the BDC is selected by the CLKSW bit as shown in
Figure 5-5 . The BDC internal clock
is named BDCSI clock. If BDCSI clock is mapped to the BDCCLK by CLKSW then the serial interface
communication is not affected by bus/core clock frequency changes. If the BDC is mapped to BDCFCLK
then the clock is connected to a PLL derived source at device level (typically bus clock), thus can be
subject to frequency changes in application. Debugging through frequency changes requires SYNC pulses
to re-synchronize. The sources of BDCCLK and BDCFCLK are specified at device level.
BDC accesses of internal device resources always use the device core clock. Thus if the ACK handshake
protocol is not enabled, the clock frequency relationship must be taken into account by the host.
When changing the clock source via the CLKSW bit a minimum delay of 150 cycles at the initial clock
speed must elapse before a SYNC can be sent. This guarantees that the start of the next BDC command
uses the new clock for timing subsequent BDC communications.
Figure 5-5. Clock Switch
5.4.4 BDC Commands
BDC commands can be classified into three types as shown in Table 5-7 .
BDCSI Clock
Core clock
1
0
CLKSW
BDCCLK
BDC serial interface
and FSM
BDC device resource
interface
BDCFCLK