Chapter 3 Memory Mapping Control (S12ZMMCV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
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Freescale Semiconductor
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All illegal accesses performed by the ADC module trigger error interrupts. See ADC section for
details.
NOTE
Illegal accesses caused by S12ZCPU opcode prefetches will also trigger
machine exceptions, even if those opcodes might not be executed in the
program flow. To avoid these machine exceptions, S12ZCPU instructions
must not be executed from the last (high addresses) 8 bytes of RAM,
EEPROM, and Flash.
3.4.3
Uncorrectable ECC Faults
RAM and flash use error correction codes (ECC) to detect and correct memory corruption. Each
uncorrectable memory corruption, which is detected during a S12ZCPU or ADC access triggers a machine
exception. Uncorrectable memory corruptions which are detected during a S12ZBDC access, are captured
in the RAMWF or the RDINV bit of the BDCCSRL register.
