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Freescale Semiconductor MC68881, User Manual

The Freescale Semiconductor MC68881 is a powerful math co-processor designed to enhance the computational capabilities of compatible microprocessors. Unlock the full potential of your system by downloading the user manual for this exceptional product, absolutely free, from manualshive.com. Explore the intricacies and functionalities with our comprehensive user manual.

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Summary of Contents for MC68881

Page 1: ......

Page 2: ...Set Coprocessor Programming Exception Processing Coprocessor Interface Instruction Executive Timing Functional Signal Descriptions Bus Operation Interfacing Methods Electrical Specifications Ordering Information and Mechanical Data Glossary Abbreviations and Acronyms Index ...

Page 3: ...FLOATING POINT COPROCESSOR USER S MANUAL Second Edition PRENTICE HALL Englewood Cliffs N J 07632 ...

Page 4: ...nse under its patent rights nor the rights of other Freescale Semiconductor Inc general policy does not recommend the use of its components in life support applications where in a failure or malfunction of the component may directly threaten life or injury Per FreescaleTermsand Conditions of Sale the user of IFreescalecomponents in life support applications assumes all risk of such use and indemni...

Page 5: ...Trap On Condition 1 15 Miscellaneous Instructions 1 15 Addressing Modes 1 15 MC68882 Programming Considerations 1 16 2 1 2 2 2 2 1 2 2 2 2 3 2 3 1 2 3 2 2 3 3 2 3 4 2 4 3 1 3 2 3 2 1 3 2 2 3 2 3 Section 2 Programming Model Floating Point Data Registers 2 1 Floating Point Control Register 2 2 FPCR E x c e p t i o n Enable Byte 2 2 FPCR Mode Control Byte 2 3 Floating Point Status Register 2 4 FPSR F...

Page 6: ...omputational Accuracy 4 5 Arithmetic Instructions 4 6 Transcendental Instructions 4 7 Decimal Conversions 4 8 Conditional Test Definitions 4 8 IEEE Nonaware Tests 4 10 IEEE Aware Tests 4 11 Miscellaneous Tests 4 12 Detailed Instruction Descriptions 4 12 Addressing Modes 4 12 Instruction Description Format 4 13 Operation Tables 4 13 NANs 4 15 Nonsignaling NANs 4 15 Signaling NANs 4 15 Operation Pos...

Page 7: ...ams 4 141 Section 5 Coprocessor Programming Applications Programming 5 1 Concurrency 5 1 Concurrent Integer and Floating Point Computations 5 1 Concurrent Floating Point Computations 5 2 Optimization of Code for the MC68882 5 9 Unrolling Loops 5 9 Avoiding Register Conflicts 5 9 Arranging FMOVE Instructions 5 9 Performance Improvement Example 5 10 Systems Programming 5 10 State Frame Sizes 5 10 Ex...

Page 8: ... 26 Address and Bus Errors 6 27 Privilege Violations 6 27 Format Error Exceptions 6 28 MC68882 Exception Handlers 6 28 Context Switching 6 28 FSAVE and FRESTORE Instruction Overviews 6 29 State Frames 6 29 Null State Frame 6 32 Idle State Frame 6 32 Busy State Frame 6 35 FSAVE Protocol 6 36 Reset Phase 6 37 Idle Phase 6 38 Initial Phase 6 38 Middle Phase 6 38 End Phase 6 38 FRESTORE Protocol 6 38 ...

Page 9: ...ASS 011 7 24 Move Control Registers OPCLASS 100 and 101 7 26 Move Multiple FPn OPCLASS 110 and 111 7 27 Conditional Instructions 7 28 Context Switch Instructions 7 28 FSAVE 7 29 FRESTORE 7 30 Exception Processing 7 31 Take Pre lnstruction Exception 7 31 Take Mid Instruction Exception 7 32 Mid Instruction Interrupt 7 35 Take BSUN Exception 7 38 F Line Emulator Exception 7 39 Format Exception FSAVE ...

Page 10: ...fer 8 38 Exception Processing 8 39 Main Processor Instruction Overlap Timing 8 40 Section 9 Functional Signal Descriptions Address Bus A0 A4 9 1 Data Bus D0 D31 9 2 Size SIZE 9 2 Address Strobe AS 9 3 Chip Select CS 9 3 Read Write R W 9 3 Data Strobe DS 9 3 Data Transfer and Size Acknowledge DSACK0 DSACK1 9 3 Reset RESET 9 4 Clock CLK 9 4 Sense Device SENSE 9 5 Power Vcc and GND 9 5 No Connect NC ...

Page 11: ...al Processor Connection 11 4 Peripheral Processor Operation 11 4 12 1 12 2 12 3 12 4 12 5 12 6 Section 12 Electrical Specifications Maximum Ratings 12 1 Thermal Characteristics PGA Package 12 1 Power Considerations 12 1 DC Electrical Characteristics 12 2 AC Electrical Characteristics Clock Input 12 3 AC Electrical Characteristics Read and Write Cycles 12 4 13 1 13 2 13 3 Section 13 Ordering Inform...

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Page 13: ... Signed Integer Data Formats 3 1 3 2 Binary Real Data Formats 3 2 3 3 Format of Normalized Numbers 3 4 3 4 Format of De normalized Numbers 3 4 3 5 Format of Zero 3 5 3 6 Format of Infinity 3 5 3 7 Format of Not A Numbers 3 6 3 8 Binary Real Data Type Summary 3 7 3 9 Packed Decimal Real Data Format 3 7 3 10 Intermediate Result Format 3 8 3 11 Packed Decimal Real Data Format Detail 3 13 4 1 Instruct...

Page 14: ...ion Primitive Format 7 17 Pre lnstruction Exception Stack Frame 7 18 Take Mid Instruction Exception Primitive Format 7 18 Mid Instruction Stack Frame 7 19 MC68881 Register to Register Instruction Dialog 7 23 MC68881 MC68882 External to Register Instruction Dialog 7 23 MC68882 External to Register Instruction Dialog 7 24 MC68881 MC68882 Register to External Instruction Dialog 7 24 MC68882 Register ...

Page 15: ...ice Circuit Example 9 5 10 1 FPCPData Bus Bit Assignments 10 2 10 2 Data Bus Activity vs Port Size and Operand Alignment 10 2 10 3 FPCP Reset Logic Example 10 6 10 4 Example of Early Chip Select Circuits 10 8 10 5 Example of Late Chip Select Circuit 10 9 10 6 Synchronous Read Cycle Timing Diagram 10 10 10 7 Asynchronous Read Cycle Timing Diagram 10 12 10 8 Asynchronous Write Cycle Timing Diagram 1...

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Page 17: ...g Mode Categories 4 13 General Type Instruction Command Word Fields 4 126 Register Field Encoding 4 127 Extension Field Encoding for Arithmetic Operations 4 128 Source Format Field Encoding 4 129 Destination Format Field Encoding 4 130 Extension Field Encoding 4 131 Encoding for Move FPcr Operations 4 132 Encodings for Move Multiple FPn Operations 4 134 Encodings for the FDBcc FScc and FTRAPcc Ins...

Page 18: ... 8 16 Timing Calculation Example 8 16 Move Control Register and MOVEM Execution Times 8 17 Conditional Instruction Execution Times 8 18 FSAVE and FRESTORE Instruction Execution Times 8 19 Instruction Start Up Times 8 25 Null Primitive Time Values 8 26 Operand Transfer Time External Operand 8 26 Operand Transfer Time Immediate Operand 8 26 Input Operand Conversion 8 28 Arithmetic Calculation Times ...

Page 19: ...020 MC68030 hard ware conventions A prior knowledge of the MC68020 MC68030 bus interface particularly as it pertains to the M68000 Family coprocessor interface is quite helpful in understanding the operation of the MC68881 MC68882 bus interface Throughout this manual M68000 or M68000 Family is used to refer to the family of devices that support the Freescale68000 Family architecture A number that ...

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Page 21: ...the MC68881 or MC68882 can be used with any of the MPU devices of the family and may also be used as a peripheral to other processors The major features of the MC68881 and MC68882 are Eight general purpose floating point data registers each supporting a full 80 bit ex tended precision real data format a 64 bit mantissa plus a sign bit and a 15 bit signed exponent A 67 bit arithmetic unit to allow ...

Page 22: ...urrently with MPU integer instructions Concur rent instruction execution is further extended by the MC68882 which can execute multiple floating point instructions simultaneously However the coprocessor interface and the FPCP are designed to maintain a strictly sequential instruction execution model from the programmer s viewpoint The FPCP is a non DMA type coprocessor that uses a subset of the gen...

Page 23: ...ters as though the registers were resident in the MPU Thus an MPU and FPCP device pair appears to be one processor that supports seven floating point and integer data types with eight integer data registers eight address reg isters and eight floating point data registers The FPCP programming model is shown in Figures 1 1 through 1 6 and consists of the following Eight 80 bit floating point data re...

Page 24: ... instructions Though the BIU monitors the state of the APU closely it operates independently of the APU The APU operates on the command word and operands that the BIU passes to it In return the APU reports its internal status to the BIU The BIU contains the coprocessor interface registers CIRs In addition to these registers the CIR register select and DSACK timing control logic is contained in the...

Page 25: ...INED RESERVED 31 30 29 28 27 26 25 24 Figure 1 4 Condition Code Byte NOTA NUMBERORUNDRDERED INFINITY ZERO NEGATIVE 23 22 20 19 18 17 16 QUOTIENT I Figure 1 5 Quotient Byte SEVENLEASTSIGNIFICANT GtTSOFQUOTIENT SIGNOFQUO flENT EOP I OVI 5 4 3 2 1 O F I z I x I I I Figure 1 6 Accrued Exception Byte INEXACT DIVIDEBYZERO UNDERFLOW OVERFLOW INVAUOOPERATION MC68881 MC68882 USER S MANUAL FREESCALE 1 5 ...

Page 26: ... 9 the MC68882 has a conversion unit CU that performs data format conversions to the internal extended format The CU relieves the APU of a significant work load and allows the MC68882 to execute FMOVE instructions concurrently with arithmetic or transcendental operations 1 2 1 Bus Interface Unit All communications between the MPU and the FPCP are performed with standard M68000 Family bus transfers...

Page 27: ... J3S U O 3VSQ t 3VSQ ZIS Mill 0 SV 3 101 11N03 _ 11 I I SV OV SS UOOV I l Q OQ VlVO Figure 1 8 MC68881 Simplified Block Diagram MC68881 MC68882 USER S MANUAL FREESCALE 1 7 ...

Page 28: ...31 1AI I OclW31 I I I I OH NVI N03 I VSSLLNW SH lSID3U VlVll 1NIDd gNU VOIJ w 5 m il I I Z Z Z Sv S3 0 tN03 gv 0v ss3H0av 0 00 vLvo Figure 1 9 MC68882 Simplified Block Diagram FREESCALE 1 8 MC68881 MC68882 USER S MANUAL ...

Page 29: ... transfers the protocol is easily emulated by software when the FPCP is used as a peripheral with any processor capable of memory mapped I O over an M68000 style bus When used as a peripheral processor with the 8 bit MC68008 or either the 16 bit MC68000 or MC68010 all FPCP instructions are trapped by the main processor to an exception handler at execution time Trapping the instructions enables the...

Page 30: ...pon the state of the APU at the time that the FSAVE is executed If the MPU is in the reset state when the FSAVE instruction is initiated only one word of state is transferred to memory The stored word may be examined by the operating system to determine that the coprocessor programmer s model is empty If the APU is in the idle state when the FSAVE instruction is decoded only a few words of interna...

Page 31: ...alized numbers the most significant bit of the mantissa is implied as a one and is not included thus giving one extra bit of precision Table 1 1 Exponent and Mantissa Sizes Data Exponent Mantissa Format Bits Bits Single 8 23 1 Double 11 52 1 Extended 15 64 The extended precision data format is also in conformance with the IEEEstandard but the standard does not specify this format to the bit level ...

Page 32: ...ng modes For example all of the following are valid instructions FADD B 0 FP0 FADD W D2 FP3 FADD L BIGINT FP7 FADD S 3 14159 FP5 FADD D SP FP6 FADD X TEMP PTR A7 FP3 FADD P 1 23E25 FP0 Most on chip calculations are performed in the extended precision format and the eight floating point data registers always contain extended precision values All operands are converted to extended precision by the F...

Page 33: ...ternal extended precision format to the destination data format Note that data movement instructions perform arithmetic operations since the result is always rounded to the precision selected in the FPCR mode control byte The result is rounded using the selected rounding mode and is checked for overflow and underflow The syntax for the FMOVE instruction is FMOVE fmt ea FPn Move to FPCP FMOVE fmt F...

Page 34: ...oot is any of the following FSQRT fmt ea FPn FSQRT X FPm FPn FSQRT X FPn The monadic operations available with the FPCP are as follows FABS Absolute Value FLOG2 Log Base 2 FACOS Arc Cosine FLOGN Log Base e FASlN Arc Sine FLOGNP1 Log Base e of x 1 FATAN Arc Tangent FNEG Negate FATANH Hyperbolic Arc Tangent FSIN Sine FCOS Cosine FSINCOS Simultaneous Sine and Cosine FCOSH Hyperbolic Cosine FSINH Hype...

Page 35: ...APcc Trap on Condition with an Optional Parameter where cc is one of the 32 floating point conditional test specifiers listed in 3 3 PACKED DECIMAL REAL DATA FORMAT 1 4 6 Miscellaneous Instructions Miscellaneous instructions include moves to and from the status control and instruction address registers Also included are the virtual memory machine FSAVE and FRESTORE instructions that save and resto...

Page 36: ...point arithmetic is coded exactly like integer arithmetic 1 6 MC68882 PROGRAMMING CONSIDERATIONS To exploit the enhanced performance of the MC68882 requires the programmer to be aware of the manner in which the coprocessor overlaps execution of instructions Upgrading a system to use the MC68882 requires minor system software changes but no user software changes To optimize applications code for th...

Page 37: ...ecision numbers The data format used is identical to the extended precision data format described in Table 3 3 except that the reserved unused 16 bits are deleted from the table All external operands regardless of the data format are converted to extended precision values before being used in any calculation or stored in a floating point data register A reset function or a restore operation of the...

Page 38: ...te is also set an exception is signaled The address of the exception handler is derived from the vector address corresponding to the exception When a user writes to the control register ENABLE byte that enables a class of floating point exceptions a previously generated floating point exception does not cause a trap to be taken regardless of the value in the status register exception byte The eigh...

Page 39: ...g precision selects where rounding of the mantissa occurs For extended pre cision the result is rounded to a 64 bit boundary A single precision result is rounded to a 24 bit boundary and a double precision result is rounded to a 53 bit boundary The single and double rounding precisions are provided for emulation of machines that only support those precisions When the FPCP performs any operation th...

Page 40: ...n rounding may not be the same as the result of performing the same operations in extended precision and storing the final result in the single or double precision format 2 3 FLOATING POINT STATUS REGISTER The floating point status register FPSR contains a floating point condition code byte a floating point exception status byte quotient bits and a floating point accrued exception byte All bits in...

Page 41: ...nd trap on condition instructions the FPCPlogically combines the four condition codes to form the IEEEconditions according to the following equations EQ Z GT NvNANvZ LT NANANvZ UN NAN where A Logical AND v Logical OR Note that the setting of the FPCPcondition codes is independent of the operation executed the condition codes only indicate the data type of the result generated Unlike other M68000 c...

Page 42: ... shown in Figure 2 6 contains a bit for each floating point exception that may have occurred during the most recent arithmetic instruction or move operation This byte is cleared by the FPCPat the start of most operations operations that cannot generate any floating point exceptions the FMOVEM and FMOVE control register instructions do not clear this byte This byte can be used by an exception handl...

Page 43: ...ION Figure 2 7 MC68881 MC68882 FPSR Accrued Exception Byte Many users elect to disable traps for all or part of the floating point exception classes The AEXC byte is provided to make it unnecessary to poll the EXC byte after each floating point instruction At the end of most operations all but the FMOVEM and FMOVE control register instructions the bits in the EXC byte are logically combined to for...

Page 44: ...s that generate floating point exception traps the 32 bit floating point instruction address FPIAR register is loaded with the logical address of an instruction before the instruction is executed unless all arithmetic exceptions are disabled This address can then be used by a floating point exception handler to locate a floating point instruction that has caused an exception Since the FPCPFMOVE to...

Page 45: ...nized in memory consistently with the M68000 Family data organization i e the most significant byte is located at the lowest address nearest 00000000 with each successively less significant byte located at the next address N 1 N 2 etc The least significant byte is located at the highest address nearest FFFFFFFF Within the floating point data formats there are five types of numbers that can be repr...

Page 46: ...ingle and double precision operands are converted to extended precision values before the specified operation is performed Thus mixed mode arithmetic is implicitly supported The memory formats for the real data formats are shown in Figure 3 2 The exponent in all three binary formats is an unsigned binary integer with an implied bias added to it The bias values for single double and extended precis...

Page 47: ...kets enclosing the range defines whether the endpoint is inclusive or ex clusive A square bracket indicates inclusive and a parenthesis indicates exclu sive For example the range specification 1 0 2 0 defines the range of numbers greater than or equal to 1 0 and less than or equal to 2 0 The range specification 0 0 inf defines the range of numbers greater than 0 0 and less than or equal to positiv...

Page 48: ...y be positive or neg ative For denormalized numbers the implied integer part bit in single and double precision is a zero 0 in extended precision the integer bit is explicitly a zero 0 See Figure 3 4 I SIGNOFMANTISSA 0 OR1 Figure 3 4 Format of Denormalized Numbers Traditionally floating point number systems perform a flush to zero when underflow is detected This leaves a large gap in the number li...

Page 49: ...present real values that exceed the overflow threshold Overflow is detected for a given data format and operation when the result exponent is greater than or equal to the maximum exponent value This overflow description ignores the effects of rounding and the user selectable rounding modes See Figure 3 6 For extended precision infinities the most significant bit of the mantissa the integer bit can...

Page 50: ...FPCPaccomplishes this by using the source SNAN setting the most significant bit of the fraction and storing the resultant nonsignaling NAN in the destination Due to the IEEEformats for NANs the result of setting the most significant fraction bit of a SNAN is always a nonsignaling NAN When NANs are created by the FPCP the NANs always contain the same bit pattern in the mantissa for any precision al...

Page 51: ... 1 1 PUCIT OEaMAl 01 2BITS USEDONLY FGR_ INFINITY ORNAN S ZERQ OTHERWISE SIGNOFEXPONENT SIGNOFMANTISSA 0 I 7 oIG T I I I P A C K E B O E C I M A L E M ANT SS A I I I I I I Unless a binary to decimal conversion overflow occurs Figure 3 9 Packed Decimal Real Data Format 3 4 INTERNAL DATA FORMAT AI FPCP internal operations are performed in extended precision All external operands regardless of data f...

Page 52: ...T CONVERSIONS Two cases of conversion between two data formats are Converting an operand in any memory data format to the extended precision data format and storing it in a floating point data register or using it as the source operand for an arithmetic operation Converting the extended precision value in a floating point data register to any data format and storing it in a memory destination 3 5 ...

Page 53: ...oint data register Note that the regular use of unnormalized inputs defeats the purpose of the IEEE standard and may produce gross inaccuracy in the results 3 5 2 Conversions to Other Data Formats Conversion from the extended precision data format to any of the other six data formats occurs when the contents of an FPCPfloating point data register are stored to memory or an MPU data register Since ...

Page 54: ...f Mantissa Significand Signed Infinities e Format Maximum f Mantissa Significand NANs Not A Number s e Format Maximum f Representation of f XXXX XXXX f When Created by the FPCP Ranges Approximate Maximum Positive Normalized Minimum Positive Normalized Minimum Positive Denormalized 31 30 23 22 IS BIASED EXPONENT FRACTION l 8 23 32 0 1 127 7F 0 e 255 FF Zero or Nonzero l f 1 s x 2e 127 x l f 0 S 0 1...

Page 55: ...f Mantissa Significand Signed Infinities e Format Maximum f Mantissa Significand NANs Not A Number S e Format Maximum f Representation of f XXXX XXXX f When Created by the FPCP Ranges Approximate Maximum Positive Normalized Minimum Positive Normalized Minimum Positive Denormalized 63 62 52 51 S I BIASED I EXPONENT FRACTION 1023 0 e 2047 7FF Zero or Nonzero 1 f 1 s x 2e 1023 x l f 0 OOO 1022 3FE No...

Page 56: ...Significand Signed Infinities e Format Maximum j j f Mantissa Significand NANs Not A Numbers e j e Format Maximum f Representation of f xxx xxxx f When Created by the FPCP Ranges Approximate Maximum Positive Normalized Minimum Positive Normalized Minimum Positive Denormalized 95 94 80 79 64 62 0 BIASEO l ZERO INTEGER PART EXPONENT FRACTION i 1 15 15 1 63 95 Don t Care All Zeros 0 1 15383 3FFFI 0 e...

Page 57: ...is a zero then it is a SNAN 2 If a nondecimal digit A SF appears in the exponent of a zero the number is converted to a true zero The FPCP does not detect nondecimal digits A F in the exponent integer or fraction digits of an in range decimal string These nondecimal digits are converted to binary in the same manner as decimal digits however the result is probably useless although it is repeatable ...

Page 58: ...3 FREESCALE 3 14 MC68881 MC68882 USER S MANUAL ...

Page 59: ...32 bits Single precision real data format 32 bits Double precision real data format 64 bits Extended precision real data format 96 bits 16 bits unused Packed BCD real data format 96 bits 12bytes One of eight floating point data registers One of the three floating point system control registers FPCR FPSR or FPIAR Any valid MC68020 MC68030 MPU address mode A twos complement signed integer 64 to 17 t...

Page 60: ...ntain any combination of the three control register FPCR FPSR and FPIAR If the register list mask resides in a main processor data register only floating point data registers may be specified 4 2 2 Dyadic Operations The dyadic floating point instructions provide several arithmetic functions that require two input operands such as add subtract multiply and divide For these operations the first oper...

Page 61: ...he general format of these instructions is shown in Table 4 4 and the available operations are listed in Table 4 5 The form of the simultaneous sine and cosine instruction is given in Table 4 6 Table 4 4 Monadic Operation Format Instruction Operand Syntax Operand Format Operation F mop ea FPn B W L S D X P source I function 0 FPn FPm FPn X FPn X FPn 0 function FPn where mop is any one of the monad...

Page 62: ...tions that are available Table 4 7 Program Control Operations Instruction Fecc FDBcc FNOP FScc FTST Operand Syntax label Dn label None ea Operand Format W L W None B Operation If Condition True Then PC d I PC If Condition True Then No Operation Else Dn 1 i Dn If Dn 1 The PC d 0 PC No Operation if Condition True The l s Destination Else O s Destination ea B W L S D X P Set FPSRCondition Codes FPn X...

Page 63: ...asking system The conditional trap instruction uses the same conditional tests as the program control instructions and allows an optional 16 or 32 bit immediate operand to be included as part of the instruction for passing parameters to the operating system Table 4 9 summarizes the system control instructions Table 4 9 System Control Operations Instruction Operand Syntax Operand Size Operation FRE...

Page 64: ...and test Since the IEEEspecification defines the error bounds to which all calculations are performed the result obtained by any conforming machine can be predicted exactly for a particular precision and rounding mode The error bound defined by the IEEEspecification is one half unit in the last place of the destination data format in the round to nearest mode and one unit in the last place in the ...

Page 65: ...ons Due to the highly recursive nature of the algorithms used to calculate these functions the round off error in the input operands to a function combined with the limited precision of the FPCP ALU do not allow the calculation of a result with the same error limit as the arithmetic functions However these operations are quite accurate given the constraint of using an ALU with a finite precision o...

Page 66: ...ions When an extended precision number is converted to packed decimal the result may be a number that cannot be represented exactly or a number that is too large to be represented with a three digit exponent When this type of conversion is performed the kfactor specified is used to locate the decimal rounding boundary If the magnitude of the rounded decimal result exponent exceeds 999 the FPCP sig...

Page 67: ...opposite of floating point branch greater than FBGT is not floating point branch less than or equal FBLE Rather the opposite condition is floating point branch not greater than FBNGT If the result of the previous instruction was unordered FBNGT is true whereas both FBGT would be false since unordered fails both of these tests and sets BSUN Compiler programmers should be particularly careful of the...

Page 68: ... Than NANvZvN 010010 NGT Not Greater Than NANvZvN 011101 GE Greater Than or Equal Zv NANvN 010011 NGE Not Greater Than or Equal NANv NAZ 011100 LT Less Than NA NANvZ 010100 NLT Not Less Than NANv ZvN 011011 LE Less Than or Equal Zv NANAN 010101 NLE Not Less Than or Equal NANv Nv 011010 GL Greater or Less Than NANvZ 010110 NGL Not Grealer or Less Than NANvZ 011001 GLE NAN 010111 NGLE where Greater ...

Page 69: ...0010 Unordered or Less or Equal NANvZvN 001101 Ordered Greater Than or Equal Zv NANvN 000011 Unordered or Less Than NANv NAZ 001101 Ordered Less Than NA NANvZ 000100 Unordered or Greater or Equal NANvZvN 001011 Ordered Less Than or Equal Zv N NAN 000101 Unordered or Greter Than NANv NvZ 001010 Ordered Greater or Less Than NANvZ 000110 Unordered or Equal NANvZ 001001 OR Ordered NAN 000111 UN Unorde...

Page 70: ...s modes are categorized by the manner in which the modes are used The following classifications are used in the instruction details Data If an effective address is used to refer to data operands it is considered a data addressing mode Memory If an effective address is used to refer to memory operands it is con sidered a memory addressing mode Alterable If an effective address is used to refer to a...

Page 71: ...An Xn X X bd An Xn X X bd An Xn od X X bd An Xn od X X llxxx W X X xxx L X d16 PC X dB PC Xn X bd PC Xn X bd PC Xn od X bd PC Xn od I data 4 5 2 Instruction Description Format The details of each instruction are provided in 4 6 INDIVIDUAL INSTRUCTION DESCRIP TIONS Figure 4 1 illustrates what information is given in these instruction descriptions 4 5 3 Operation Tables An operation table is include...

Page 72: ... WIMMEDIATELYAFTERTHEILLUSTRATEDPDRTIDNSOF THEINSTRUCTIONS R E F E RTOTHEUSER SMANUALOFTHEMC68020 O RMC68030F O RTHEFORMATOFANYR E Q U I R E DEXTENSIONWORDS I MEANINGSANDALLOWED VALUES FOR THEVARIOUS FIELDS REQUIRED __ BYTHEINSTRUCTION FORMAT Operation Absolute Value of Sou Assembler FABS fmt ea Syntax FABS X FPrr FABS X FPn Attributes Format Byte Word Description Converts the source o absolute va...

Page 73: ...in a row and column for NANs because NANs are handled the same way in all operations 4 5 4 1 NONSIGNALING NANs If either but not both operand of an operation is a NAN and it is a nonsignaling NAN then that NAN is returned as the result If both operands are nonsignaling NANs then the destination operand nonsignaling NAN is returned as the result 4 5 4 2 SIGNALING NANs If either operand to an operat...

Page 74: ...ST DEFINITIONS for a description of the use of the four condition code bits to generate the 32 floating point conditional tests 415 5 2 UNDERFLOW ROUND OVERFLOW During calculation of an arithmetic result the ALU of the FPCP has more precision and range than the 80 bit extended precision format However the final result of these operations is an extended precision floating point value In some cases ...

Page 75: ...number infinity zero or smallest denormalized number is an extended precision number with an extended precision mantissa value 4 6 INDIVIDUAL INSTRUCTION DESCRIPTIONS The following notation is used in the detailed instruction definitions that follow operand Contents of the referenced location or register fmt Operand data format Byte word long single double extended or packed denoted in the assembl...

Page 76: ...tion Status Register Condition Codes Quotient Byte Exception Byte Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Not affected BSUN Cleared SNAN Refer to 4 5 4 NANs OPERR Cleared OVFL Cleared UNFL If the source is an extended precision denor realized number refer to 6 1 5 Underflow cleared otherwise DZ Cleared INEX2 Cleared INEX1 If fret is Packed refer to 6 1 8 Inexact Res...

Page 77: ...ter 111 000 111 001 111 100 111 010 111 011 111 011 111 011 111 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point data register FPm If R M 1 specifies the source data format 000 L Long Word Integer 001 S Sin...

Page 78: ... Cosine Zero Infinity 2 NAN NOTES 1 Sets the OPERR bit in the FPSR exception byte 2 If the source operand is a NAN refer to 4 5 4 NANs for more information Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Instruction Format 15 14 13 1 1 0 R M 0 Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Not affected BSUN SNAN OPERR OVFL UNFL DZ INEX2 ...

Page 79: ...Xn 111 011 bd PC Xn 111 011 bd PC Xn od 111 011 bd PC Xn od 111 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point data register FPm If R M 1 specifies the source data format 000 L Long Word Integer 001 S Sin...

Page 80: ...in rounding modes RN R2 and RP returns 0 0 in RM 2 Sets the OPERR bit in the FPSR exception byte 3 If either operand is a NAN refer to 4 5 4 NANs for more information Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Not affected BSUN SNAN OPERR OVFL UNFL DZ INEX2 INEX1 Cleared Refer to 4 5 4 ...

Page 81: ...0 reg number An bd An Xn 110 reg number An bd An XnJ od 110 reg number An bd An Xn od 110 reg number An Only if fret is Byte Word Long or Single Addressing Mode Mode Register xxx W 111 000 x x L 111 001 data 111 100 d16 PC 111 010 ds PC Xn 111 011 bd PC Xn 111 011 bd PC Xnl od 111 011 bd PC Xn od 111 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 ...

Page 82: ... result is in the range of r 2 w 2 Operation Table Source Destination Result In Range Arc Sine I Zero 0 0 0 0 Infinity NAN 7 NOTES 1 Sets the OPERR bit in the FPSRexception byte 2 If the source operand is a NAN refer to 4 5 4 NANs for more information Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITIO...

Page 83: ...dressing Mode Mode Register xxx W 111 000 xxx L 111 001 data 111 100 d16 PC 111 010 ds PC Xn 111 011 bd PC Xn 111 011 bd PC Xn od 111 011 libd PC Xn od 111 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M O specifies the source floating point d...

Page 84: ...o 4 5 4 NANs for more information Status Register Condition Codes Quotient Byte Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Not affected Exception Byte Accrued Exception Byte BSUN SNAN OPERR OVFL UNFL DZ INEX2 INEX1 Cleared Refer to 4 5 4 NANs Cleared Cleared Refer to 6 1 5 Underflow Cleared Refer to 6 1 7 Inexact Result If fmt is Packed refer to 6 1 8 Inexact Result on...

Page 85: ...Xn 111 011 bd PC Xn 111 011 lbd PC Xn od 111 011 lbd PC Xn od 111 Ol 1 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point data register FPm If R M 1 specifies the source data format 000 L Long Word Integer 001 S ...

Page 86: ...and the OPERR bit is set in the FPSR OperationTable Source Destination In Range Result Hyperbolic Arc Tangent Zero 4 0 0 0 0 Infinity NAN 1 NOTE 1 Sets the OPERR bit in the FPSR exception byte 2 If the source operand is a NAN refer to 4 5 4 NANs for more information StatusRegister Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Affected as described in 4 5 5 1 SETTING FLOATING ...

Page 87: ...ingle Addressing Mode Mode Register xxx W 111 000 xxx L 111 001 data 111 100 d16 PC 111 010 ds PC Xn 111 011 Ibd PC Xn 111 011 bd PC XnJ od 111 011 bd PC Xn od 111 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating...

Page 88: ...diately following the instruction operation word The conditional specifier cc selects any one of the 32 floating point conditional tests as described in 4 4 CONDITIONAL TEST DEFINITIONS Status Register Condition Codes Not affected Quotient Byte Not affected Exception Byte BSUN Accrued Exception Byte Set if the NAN condition code is set and the condition selected is an IEEE nonaware test SNAN Not A...

Page 89: ...Conditional Predicate Field Specifies one of 32 conditional tests as defined in 4 4 CONDITIONAL TEST DEFINITIONS NOTE When a BSUN exception occurs the main processor takes a pre instruction ex ception If the exception handler returns without modifying the image of the PC on the stack frame to point to the instruction following the FBcc then it must clear the cause of the exception by clearing the ...

Page 90: ... set or cleared as appropriate If the name of a condition code bit is not given then that bit is always cleared by the operation The infinity bit is always cleared by the FCMP instruction since it is not used by any of the conditional predicate equations Note that the NAN bit is not shown since NANs are always handled in the same manner as described in 4 5 4 NANs Source Destination In Range Zero I...

Page 91: ... 110 reg number An bd An Xn 110 reg number An bd An Xn od 110 reg number An bd An Xn od 110 reg number An Only if fmt is Byte Word Long or Single Addressing Mode xxx W xxx L data d16 PC ds PC Xn bd PC Xn Ibd PC Xnl od bd PC Xn od Mode Register 111 00O 111 00 111 100 111 010 111 011 111 011 111 011 111 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1...

Page 92: ...ts greater than approximately 1020 lose all accuracy The result is in the range of 1 1 Operation Table ce In Range Result Cosine Zero 1 0 Infinity p NAN I NOTE 1 Sets the OPERR bit in the FPSR exception byte 2 if the source operand is a NAN refer to 4 5 4 NANs for more information Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Affected as described in 4 5 5 1 S...

Page 93: ... data 111 d16 PC 111 do PC Xn 111 bd PC Xn 111 Ibd PC Xn od 111 bd PC Xn od 111 Register OOO 001 100 010 011 011 011 011 Only if fret is Byte Word Long or Single R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point...

Page 94: ... 4 5 4 BANs for more information Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Instruction Format 15 14 13 1 1 0 R M 0 Affected as described in 4 5 5 1 SE r rlNG FLOATING POINT CONDITION CODES Not affected BSUN SNAN OPERR OVFL UNFL DZ INEX2 INEX1 Cleared Refer to 4 5 4 NANs Cleared Refer to 6 1 4 Overflow Cleared Cleared Refer to 6 1 7 Inexact Result If fret i...

Page 95: ...ode 111 111 111 111 111 111 111 111 Register 000 001 100 010 011 011 011 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point data register FPm If R M 1 specifies the source data format 000 L Long Word Integer ...

Page 96: ... exhausted and execution continues with the next instruction If the result is not equal to 1 execution continues at the location specified by the current value of the PC plus the sign extended 16 bit displacement The value of the PC used in the branch address calculation is the address of the displacement word The conditional specifier cc selects any one of the 32 floating point conditional tests ...

Page 97: ...less than 2 There are two basic ways of entering a loop at the beginning or by branching to the trailing FDBcc instruction If a loop structure terminated with FDBcc is entered at the beginning the control counter must be one less than the number of loop executions desired This count is useful for indexed addressing modes and dynamically specified bit operations However when entering a loop by bran...

Page 98: ... Sets the DZ bit in the FPSR exception byte 2 Sets the OPERR bit in the FPSR exception byte 3 If either operand is a NAN refer to 4 5 4 NANs for more information Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Not affected BSUN SNAN OPERR OVFL UNFL DZ tNEX2 INEX1 Cleared Refer to 4 5 4 NANs ...

Page 99: ... reg number An 110 reg number An 110 reg number An 110 reg number An 110 reg number An Only if fmt is Byte Word Long or Single Addressing Mode Mode xxx W 111 xxx L 111 data 111 d16 PC 111 ds PC Xn 111 bd PC Xn 111 bd PC Xnl od 111 bd PC Xn od 111 Register 0O0 001 100 01O 011 Oll 011 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is e...

Page 100: ... information Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Instruction Format 15 14 13 I 1 I 0 R M Affected as described in 4 5 5 1 SE I ING FLOATING POINT CONDITION CODES Not affected BSUN SNAN OPERR OVFL UNFL DZ INEX2 INEX1 Cleared Refer to 4 5 4 NANs Cleared Refer to 6 1 4 Overflow Refer to 6 1 5 Underflow Cleared Refer to 6 1 7 Inexact Result If fmt is Pac...

Page 101: ...Xn 111 011 bd PC Xn 111 011 bd PC Xn od 111 011 bd PC Xn od 111 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point data register FPm If R M 1 specifies the source data format 000 L Long Word Integer 001 S Sin...

Page 102: ...nformation Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Instruction Format 15 14 13 J I 1 I O R M 0 Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Not affected BSUN SNAN OPERR OVFL UNFL DZ INEX2 INEX1 Cleared Refer to 4 5 4 NANs Cleared Refer to 6 1 4 Overflow Refer to 6 1 5 Underflow Cleared Refer to 6 1 7 Inexact Result If fret is P...

Page 103: ... 0d 111 011 bd PCJ Xn od 111 011 Only if fmt is Byte Word Long or Single R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point data register FPm If R M 1 specifies the source data format 000 L Long Word Integer 001 ...

Page 104: ... Result Exponent Zero _ I Infinity 0 0 0 0 NAN 1 NOTES 1 Sets the OPERR bit in the FPSR exception byte 2 If the source operand is a NAN refer to 4 5 4 NANs for more information Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Affected as described in 4 5 5 1 SETI ING FLOATING POINT CONDITION CODES Not affected BSUN SNAN OPERR Cleared Refer to 4 5 4 NANs Set if th...

Page 105: ...ng Mode Mode Register xxx W 111 00O xxx L 111 001 data 111 100 d16 PC 111 010 ds PC Xn 111 011 bd PC Xn 111 011 bd PC Xn od 111 011 I bd PC Xn od 111 011 RIM Field Specifies the source operand address mode 0 The operation is register to register 1 m The operation is ea to register Source Specifier Field Specifies the source register or data format If R M O specifies the source floating point data ...

Page 106: ...Source InRange Zero Destination Result I Mantissa 0 0 O Q NOTE S I Sets the OPERR bit in the FPSR exception byte 2 If the source operand is a NAN refer to 4 5 4 NANs for more information J Infinity l NAN1 1 Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Affected as described in 4 5 5 1 SE R ING FLOATING POINT CONDITION CODES Not affected BSUN SNAN OPERR OVFL UN...

Page 107: ...r An bd PC Xn od reg number An Ibd PC Xn od Only if fret is Byte Word Long or Single Mode 111 111 111 111 111 111 111 I 111 Register 000 001 100 010 011 011 011 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating po...

Page 108: ...ple the integer part of 137 57 is 137 0 for the round to zero and round to minus infinity modes and 138 0 for the round to nearest and round to plus infinity modes Note that the result of this operation is a floating point number Operation Table Source In Range Zero I Infinity Destination Result Integer 0 0 0 0 inf J NOTE If the source operand is a NAN refer to 4 5 4 NANs for more information inf ...

Page 109: ...ngle Addressing Mode Mode Register xxx W 111 000 xxx L 111 001 data 111 100 d16 PC 111 010 d8 PC Xn 111 011 bd PC Xn 111 011 bd PC Xn od 111 011 bd PC Xn od 111 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field m Specifies the source register or data format If R M 0 specifies the source floating ...

Page 110: ... number that is to the left of the radix point when the exponent is zero For example the integer part of 137 57 is 137 0 the integer part of 0 1245x 102 is 12 0 Note that the result of this operation is a floating point number Operation Table Source In Range Destination Result Integer Forced Round To Zero Zero 0 0 0 0 inf inf NOTE If the source operand is a NAN refer to 4 5 4 NANs for more informa...

Page 111: ...ng or Single Addressing Mode Mode Register xxx W 111 000 xxx L 111 001 data 111 100 d16 PC 111 010 d8 PC Xn 111 011 bd PC Xn 111 011 bd PC XnLod 111 011 bd PC Xn od 111 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source flo...

Page 112: ...ception byte 3 If the source operand is a NAN refer to 4 5 4 NANs for more information Status Register Condition Codes Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Quotient Byte Not affected Exception Byte BSUN SNAN OPERR Accrued Exception Byte Instruction Format 15 14 13 1 I Cleared Refer to 4 5 4 NANs Set if the source operand is 0 cleared otherwise OVFL Cleared UNFL C...

Page 113: ...ister 111 000 111 001 111 100 111 010 111 011 111 011 111 011 111 0tl R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point data register FPm If R M 1 specifies the source data format 000 L Long Word Integer 001 S S...

Page 114: ...byte 3 If the source operand is a NAN refer to 4 5 4 NANs for more information Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Not affected BSUN SNAN OPERR OVFL UNFL DZ Cleared Refer to 4 5 4 NANs Set if the source is 0 cleared otherwise Cleared Cleared Set if the source is or 0 cleared othe...

Page 115: ...111 011 bd PC Xn 111 011 bd PC Xn od 111 011 bd PC Xn od 111 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point data register FPm If R M 1 specifies the source data format 000 L Long Word Integer 001 S Single...

Page 116: ...efer to 4 5 4 NANs for more information Status Register Condition Codes Infinity F inf NAN1 Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Quotient Byte Not affected Exception Byte BSUN SNAN OPERR Cleared Refer to 4 5 4 NANs Set if the source operand is 0 cleared otherwise OVFL Cleared UNFL Cleared DZ Set if the source is or 0 cleared other wise NEX2 Refer to 6 1 7 Inexact...

Page 117: ...Xn 111 011 bd PC Xn 111 011 bd PC Xn od 111 011 bd PC Xn od 111 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point data register FPm If R M 1 specifies the source data format 000 L Long Word Integer 001 S Sin...

Page 118: ...xception byte and returns a NAN If the source is 1 sets the OPERR bit in the FPSR exception byte and returns a NAN 2 Sets the OPERR bit in the FPSR exception byte 3 If the source operand is a NAN refer to 4 5 4 NANs for more information Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Affected as described in 4 5 5 1 SE I FING FLOATING POINT CONDITION CODES Not a...

Page 119: ...essing Mode Mode Register xxx W 111 000 xxx L 111 001 data 111 100 Id16 PC 111 010 d8 PC Xn 111 011 bd PC Xn 111 011 bd PC Xn od 111 011 bd PC Xn od 111 011 R M Field m Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point da...

Page 120: ... remainder that is required by the IEEESpecification for Binary Floating Point Arithmetic Operation Table Source Destination In Range In Range Zero Infinity Modulo Remainder NAN 1 FPn2 Zero 0 0 NAN1 0 0 0 0 0 0 Infinity NAN 1 NAN 1 NAN1 NOTES 1 Sets the OPERR bit in the FPSR exception byte 2 Returns the vatue of FPn before the operation However the result is processedbythe normal instruction termi...

Page 121: ...e Mode Register Addressing Mode Mode Register Dn 000 reg number Dn xxx W 111 O00 An xxx L 111 001 iAn 010 reg number An data 111 100 An 011 reg number An An 100 reg number An d16 An 101 reg number An d16 PC 111 010 ds An Xn 110 reg number An d8 PC Xn 111 011 bd An Xn l t0 reg number An bd PC Xn 111 011 bd An Xn od 110 reg number An bd PC Xn od 111 011 bd AnJ Xn od 110 reg number An bd PC Xn od 111...

Page 122: ...n The FMOVE instruction only supports memory to register register to register and register to memory operations in this context memory may refer to an MPU data register if the data format is byte word long or single The memory to register and register to register operations use a command word encoding distinctly different from that used by the register to memory operation and these two operation c...

Page 123: ...ale assemblers default to ID I for the FPCP Effective Address Field Determines the addressing mode for external operands If RIM 0 this field is unused and should be all zeros If RIM 1 this field is encoded with an M68000 addressing mode as shown 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Addressing Mode Dn An 0 0 An An An 0 1 1 1 1 Mode 000 di6 h d An Xn bd An Xnl Register Addressing Mode 1 xxx1 ...

Page 124: ...ified destination format and stores it at the destination effective address If the format of the destination is packed decimal a third operand is required to specify the format of the resultant string This operand called the k factor is a 7 bit signed integer twos complement and may be specified as an immediate value or in a main processor data register If a data register contains the k factor Onl...

Page 125: ...ared otherwise OVFL Cleared UNFL Cleared DZ Cleared INEX2 Refer to 6 1 7 Inexact Result INEX1 Cleared Accrued Exception Byte Affected as described in 6 1 10 IEEEException and Trap Com patibility Instruction Format 15 14 13 12 fl 10 9 8 7 6 5 4 3 2 1 _ COPROCESSOR EFFECTIVEADDRESS 1 IO 0 0 0 MOOE I REGISTER DESTINATION SOURCE K FACTOR 1 FORMAT REGISTER IF REQUIRED Instruction Fields Coprocessor ID ...

Page 126: ...al Packed Decimal Real with static k factor Word Integer Double Precision Real Byte Integer Packed Decimal Real with dynamic k factor Source Register Field Specifies the source floating point data register FPm k factor Field Only used if the destination format is Packed Decimal to specify the format of the decimal string For any other destination format this field should be set to all zeros For a ...

Page 127: ... The format of the string that is generated is independent of the source of the k factor static or dynamic k Factor SourceOperandValue Destination String 5 12345 678765 1 234567877 E 4 3 12345 678765 1 2345679 E 4 1 12345 678765 1 23457 E 4 0 12345 678765 1 2346 E 4 1 12345 678765 1 E 4 3 12345 678765 1 23 E 4 5 12345 678765 1 2346 E 4 MC68881 MC68882 USER S MANUAL FREESCALE 4 69 ...

Page 128: ...itten Status Register Changed only if the destination is the FPSR in which case all bits are modified to reflect the value of the source operand Instruction Format 15 14 13 I I 1 I 0 dr 12 11 10 9 8 7 6 5 4 3 2 1 g COPROCESSOR I EFFECTIVFq ADDRESS l z ID 0 0 0 MODE REGISTER REGISTER SELECT 0 0 0 0 0 I 0 0 0 Instruction Fields Coprocessor ID Field Specifies which coprocessor in the system is to exe...

Page 129: ...is the FPIAR Addressing Mode xx W xxx L data d16 PC ds PC Xn bd PC Xn bd PC Xn odl bd PCI Xn od Mode 111 111 Register 000 001 dr Field Specifies the direction of the data transfer 0 Move an external operand to the specified system control register 1 Move the specified system control register to an external location Register Select Field Specifies the system control register to be moved 100 FPCR Fl...

Page 130: ...he ROM are shown in the offset table at the end of this description Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Not affected BSUN Cleared SNAN Cleared OPERR Cleared OVFL Cleared UNFL Cleared DZ Cleared INEX2 Refer to 6 1 7 Inexact Result INEX1 Cleared Affected as described in 6 1 10 IEEE...

Page 131: ...he desired constant is located The offsets for the available constants are Offset Constant 00 0B Log10 2 0C e S0D Log2 e 0E Logl0 e 0F 0 0 30 ln 2 31 ln 10 32 10o 33 101 34 102 35 104 36 108 37 10TM 38 1032 39 1064 3A 10126 3B 10256 3C 10512 3D 10TM 3E 102048 3F 104096 The on chip ROM contains other constants useful only to the on chip microcode rou tines The values contained at offsets other than...

Page 132: ...a register the remaining bits of the register are ignored FMOVEM allows three types of addressing modes the control modes the predecre ment mode or the postincrement mode If the effective address is one of the control addressing modes the registers are transferred between the FPCPand memory start ing at the specified address and up through higher addresses The order of the transfer is from FP7 FP0...

Page 133: ...de and exception status bits Instruction Format 15 14 13 1 1 1 1 dr 12 11 10 9 8 7 6 5 4 3 2 1 0 I COPROCESSOR EFFECTIVEADDRESS 1 ID 0 0 0 MODE I REGISTER MODE I 0 I 0 0 REG STERLIST Instruction Fields Coprocessor ID Field Specifies which coprocessor in the system is to execute this instruction Freescale assemblers default to ID 1 for the FPCP Effective Address Field Determines the addressing mode...

Page 134: ... FP2 FP1 FP0 Static An or Control FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 Dynamic 0 r r r 0 0 0 0 The format of the dynamic list mask is the same as for the static list and is contained in the least significant eight bits of the specified main processor data register Programming Note This instruction provides a very useful feature dynamic register list specification that can significantly enhance system p...

Page 135: ...y The appropriate registers are then stored along with the two masks Called procedure MOVE W D7 D6 AND W WILL USE D7 FMOVEM D7 A7 MOVE W D7 AT EOR W D7 D6 MOVE W D6 P A7 Copy the list of active registers Generate the list of doubly used registers Save those registers Save the register list Generate the list of not saved active registers Save it for later use If the second procedure calls a third p...

Page 136: ...nted by the total size of the register images to be moved i e four times the number of registers and then the registers are transferred starting at the resultant address For the postincrement ad dressing mode the selected registers are transferred to or from the specified address and then the address register is incremented by the total size of the register images transferred If a single system co...

Page 137: ...n An d16 An I dB An Xn Ibd An Xn bd An Xn od bd AnJ Xn od Mode Register 00O reg number Dn 001 reg number An 010 reg number An 011 reg number An 100 reg number An 101 reg number An it0 reg number An I 110 reg number An 110 reg number An 110 reg number An Only if a single FPcr is selected Only if the FPIAR is the single register selected Addressing Mode Mode Register xxx W 111 000 xxx L 111 001 data...

Page 138: ...R exception byte 2 If the source operand is a NAN refer to 4 5 4 NANs for more information Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Not affected BSUN SNAN OPERR OVFL UNFL DZ INEX2 INEX1 Cleared Refer to 4 5 4 NANs Set for 0 x infinity cleared otherwise Refer to 6 1 4 Overflow Refer to...

Page 139: ...n reg number An reg number An reg number An or Single Addressing Mode Mode xxx W 111 xxx L 111 data 111 d16 PC 111 d8 PC Xn 111 bd PC Xn 111 bd PC XnJ od 111 bd PC Xn od 111 Register 000 001 100 010 011 011 011 011 R M Field m Specifies the source operand address mode 0 The operation is register to register 1 m The operation is ea to register Source Specifier Field Specifies the source register or...

Page 140: ... the source operand is a NAN refer to 4 5 4 NANs for more information inf Status Register Condition Codes Quotient Byte Exception Byte Affected as described in 4 5 5 1 SETrlNG FLOATING POINT CONDITION CODES Not affected BSUN SNAN OPERR OVFL UNFL DZ INEX2 INEX1 Cleared Refer to 4 5 4 NANs Cleared Cleared If source is an extended precision denormal ized number refer to 6 1 5 Underflow cleared otherw...

Page 141: ...ressing Mode Mode Register xxx W 111 000 xxx L 111 001 data 111 100 d16 PC 111 010 dG PC Xn 111 011 bd PC Xn 111 011 bd PC Xn od 111 011 bd PC Xn od 111 011 R M Field Specifies the source operand address mode 0 m The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point da...

Page 142: ...o nized with the MC68881 The MC68882 may not wait to begin execution of another floating point instruction until it has completed execution of the current instruction However the FNOP instruc tion synchronizes the coprocessor and MPU by causing the MPU to wait until the current instruction or both instructions have completed The FNOP instruction also forces the processing of exceptions pending fro...

Page 143: ...0 0 Instruction Fields Coprocessor ID Field u Specifies which coprocessor in the system is to execute this instruction Freescale assemblers default to ID 1 for the FPCP NOTE FNOP uses the same opcode as the FBcc W label instruction with cc F non trapping false and label 2 which results in a displacement of 0 MC68881 MC68882 USER S MANUAL FREESCALE 4 85 ...

Page 144: ...t is different from the remainder required by the IEEESpecification for Binary Floating Point Arith metic Operation Table Source Destination In Range In Range Zero F Infinity F IEEE Remainder NAN 1 FPn2 0 O 0 0 Zero NAN 1 0 0 0 0 Infinity NAN 1 NAN 1 NAN 1 NOTES 1 Sets the OPERR bit in the FPSR exception byte 2 Returns the value of FPn before the operation However the result is processed by the no...

Page 145: ...egister Addressing Mode Mode Register Dn 000 reg number Dn xxx W 111 000 An xxx L 111 001 An 010 reg number An data 111 100 An 011 reg number An An 100 reg number An dlG An 101 reg number An d16 PC 111 010 d8 An Xn 110 reg number An d8 PC Xn 111 011 bd An Xn 110 reg number An bd PC Xn 111 011 bd An Xnl od 110 reg number An bd PC XnJ od 111 011 bd An Xn od 110 reg number An bd PC Xn od 111 011 Only...

Page 146: ...tion and proceeding through higher addresses The FRESTOREinstruction does not normally affect the programmer s model registers of the FPCP except for the NULL state size as described below but is used only to restore the user invisible portion of the machine The FRESTOREinstruction is used with the FMOVEM instruction to perform a full context restoration of the FPCP in cluding the floating point d...

Page 147: ...is type of state frame although the completion of the suspended instruction after the restore is executed may modify the programmer s model Status Register Cleared if the state size is NULL otherwise not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 S COPROCESSOR 1 1 1 1 IO 1 0 l 4 3 2 1 0 EFFECTIVEADDRESS MODE REGISTER Instruction Fields Coprocessor ID Field Specifies which coprocessor fn...

Page 148: ...e XX is the FPCP version number The Not Ready format word indicates that the FPCPis not prepared to perform a state save and that the MPU should process interrupts if necessary and then re read the save CIR The FPCP uses this format word to cause the main processor to wait while an internal operation is completed if possible in order to allow an IDLE frame to be saved rather than a BUSY frame The ...

Page 149: ...struction where it was necessary to save the entire internal state of the processor This frame size is only used when absolutely necessary because of the large size of the frame and the amount of time required to transfer it The action of the FPCPwhen this state frame is saved is the same as for the IDLE state frame The FSAVE does not save the programmer s model registers of the FPCP but is used t...

Page 150: ...or the state frame Only predecrement or control alterable addressing modes are allowed as shown Addressing Mode Mode Register Dn An An 010 reg number An An An 100 reg number An d16 An 101 reg number An d8 An Xn 110 reg number An bd An Xn 110 reg number An bd An Xn od 110 reg number An bd An Xn od 110 reg number An Addressing Mode Mode Register 000 xxx W xxx L data d16 PC ds PC Xn bd PC Xn bd PC Xn...

Page 151: ...e operand is 214 an overflow or underflow always results Operation Table e In Range Zero Infinity In Range Scale Exponent FPnI NAN2 Zero 0 0 0 0 NAN2 0 0 0 0 Infinity inf inf NAN2 inf inf NOTES 1 Returns the value FPn before the operation However the result is processed by the normal instruction termination procedure to round it as required Thus an underflow and or inexact result may occur if the ...

Page 152: ...emblers default to ID 1 for the FPCP Effective Address Field Determines the addressing mode for external operands If R M 0 this field is unused and should be all zeros If R M 1 this field is encoded with an M68000 addressing mode as shown Addressing Mode On An An An An d16 An ds An Xn bd An Xn bd An Xn od bd AnJ Xn od Mode Register 000 reg number Dn 010 reg number An 011 reg number An 100 reg numb...

Page 153: ...format If R M 0 specifies the source floating point data register FPm If R M 1 specifies the source data format 000 L Long Word Integer 001 S Single Precision Real 010 X Extended Precision Real 011 P Packed Decimal Real 100 W Word Integer 101 D Double Precision Real 110 B Byte Integer Destination Register Field w Specifies the destination floating point data register FPn MC68881 MC68882 USER S MAN...

Page 154: ...AL TEST DEFINITIONS Status Register Condition Codes Not affected Quotient Byte Not affected Exception Byte BSUN Accrued Exception Byte Instruction Format 15 14 1 3 12 I I 7 1 0 O 0 O Set if the NAN condition code is set and the condition selected is an IEEE nonaware test SNAN Not Affected OPERR Not Affected OVFL Not Affected UNFL Not Affected DZ Not Affected INEX2 Not Affected INEXl Not Affected T...

Page 155: ... od 110 reg number An Addressing Mode Mode Register xxx W 111 000 xxx L 111 001 data d16 PCl _ d8 PC Xn _ bd PC Xn bd PC XnJ od bd PC Xn od Conditional Predicate Field Specifies one of 32 conditional tests as defined in 4 4 CONDITIONAL TEST DEFINITIONS NOTE When a BSUN exception occurs a pre instruction exception is taken by the main processor If the exception handier returns without modifying the...

Page 156: ...gardless of the round ing precision selected in the FPCR mode control byte Refer to 4 5 5 2 UNDERFLOW ROUND OVERFLOW for more information Operation Table Source Destination In Range Zero Infinity InRange Divide Single Precision Zero inf1 infl inf iof 1 I Infinity 0 0 0 0 0 0 0 0 0 0 0 0 NAN2 0 0 0 0 0 0 0 0 0 0 0 0 inf inf inf inf NAN2 inf inf inf inf NOTES 1 Sets the DZ bit in the FPSR exception ...

Page 157: ... number An An t00 reg number An Id16 An 101 reg number An ds An Xn 110 reg number An bd An Xn 110 reg number An bd An Xnl od 110 reg number An bd An Xn od 110 reg number An Only if fret is Byte Word Long or Single Addressing Mode Mode xxx W 11i xxx L 111 data 111 d16 PC 111 d8 PC Xn 111 bd PC Xn 111 bd PC Xnl od 111 bd PCJ Xn od 111 Register 000 001 100 010 011 011 011 011 R M Field Specifies the ...

Page 158: ...ult exponent may exceed the range of single precision regardless of the round ing precision selected in the FPCR mode control byte Refer to 4 5 5 2 UNDERFLOW ROUND OVERFLOW for more information OperationTable Source Destination _ In Range In Range Multiply Single Precision Zero 0 0 0 0 0 0 0 0 Infinity inf inf inf inf Zero O 0 0 0 0 O 0 O NAN1 0 O 0 0 0 0 0 0 Infinity inf inf inf inf inf inf NAN1 ...

Page 159: ...eg number An An 100 reg number An d16 An 101 reg number An ds An Xn 110 reg number An bd An Xn 110 reg number An Ibd An Xn od 110 reg number An bd AnJ Xn od 110 reg number An Only if fret is Byte Word Long or Single Addressing Mode Mode xxx W 111 xxx L 111 data 111 d16 PC 111 d8 PC Xn 111 bd PC Xn 111 bd PC XnJ od 111 bd PC Xn od 111 Register O00 001 100 010 011 011 011 011 R M Field Specifies the...

Page 160: ...oximately 102 lose all accuracy The result is in the range of 1 11 Operation Table _ Source i In Range Zero Destination Result Sine 0 0 0 0 NOTES 1 Sets the OPERR bit in the FPSR exception byte 2 If the source operand is a NAN refer to 4 5 4 NANs for more information Infinity NAN 1 Status Register Condition Codes Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Quotient Byte...

Page 161: ...Mode Mode Register xxx W 111 000 xxx L 111 001 data 1i t 100 d16 PC 111 010 d8 PC Xn 111 011 bd PC Xn 111 011 bd PC Xn od 111 011 bd PC Xn od 111 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point data regist...

Page 162: ...s not defined for source operands of infinity If the source operand is not in the range of 2 r 2 r the argument is reduced to within that range before the sine and cosine are calculated However large argu ments may lose accuracy during reduction and very large arguments greater than approximately 102 lose all accuracy The results are in the range of 1 1 OperationTable Source In Range Destination F...

Page 163: ... shown Addressing Mode Mode Register Dn 000 reg number Dn An An 010 reg number An An 011 reg number An IAn 100 reg number An d16 An 101 reg number An ds An Xn 110 reg number An bd An Xn 110 reg number An bd An Xn od 110 reg number An bd AnJ Xn od 110 reg number An Only if fmt is Byte Word Long or Single Addressing Mode Mode Register xxx W 111 O0O xxx L 111 001 data 111 100 d16 PC 111 010 d8 PC Xn ...

Page 164: ...ster FPs The sine result is stored in this register If FPc and FPs specify the same floating point data register the sine result is stored in the register and the cosine result is discarded If R M O and the source register field is equal to either of the destination register fields the input operand is taken from the specified floating point data register and the appropriate result is written into...

Page 165: ...NANs for more information inf Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Not affected BSUN SNAN OPERR OVFL UNFL DZ INEX2 INEX1 Cleared Refer to 4 5 4 NANs Cleared Refer to 6 1 4 Overflow Refer to 6 1 5 Underflow Cleared Refer to 6 1 7 Inexact Result If fmt is Packed refer to 6 1 8 Inexa...

Page 166: ...10 d8 PC Xn 111 011 bd PC Xn 111 011 Ibd PC Xn od 111 011 bd PC Xn od 111 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point data register FPm If R M 1 specifies the source data format 000 L Long Word Integer...

Page 167: ...OTES 1 Sets the OPERR bit in the FPSR exception byte 2 If the source operand is a NAN refer to 4 5 4 NANs for more information Infinity inf NAN 1 Status Register Condition Codes Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Quotient Byte Not affected Exception Byte BSUN SNAN OPERR Cleared Refer to 4 5 4 NANs Set if the source operand is not zero and is negative cleared ot...

Page 168: ...essing Mode xxx W xxx L data d16 PC Mode 111 111 111 111 111 Register i I O D O O01 100 t 010 t 011 d8 PC Xn bd PC Xn 111 011 bd PC Xn od 111 i 011 bd PC Xn od 111 i 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floati...

Page 169: ... 0 0 in rounding modes RN RZ and RP returns 0 0 in RM 2 Sets the OPERR bit in the FPSR exception byte 3 If the source operand is a NAN refer to 4 5 4 NANs for more information Status Register Condition Codes Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Quotient Byte Not affected Exception Byte BSUN SNAN OPERR Cleared Refer to 4 5 4 NANs Set if both the source and destina...

Page 170: ...n Xn 110 reg number An bd An Xn 110 reg number An bd An Xn od 110 reg number An bd AnJ Xn od 110 reg number An Only if fmt is Byte Word Long or Single Addressing Mode xxx W Mode I Register d8 PC Xn 111 xxx L i 111 031 data 111 I 103 I I d16 PC 111 I 010 011 Ibd PC Xn bd PC Xn ocl bd PC Xn od 111 J 00 3 011 I 111 I 011 111 t 011 R M Field Specifies the source operand address mode 0 The operation is...

Page 171: ...guments greater than approximately 102 lose all accuracy Operation Table ce Result In Range Tangent Zero 0 0 0 0 Infinity NAN 1 NOTES 1 Sets the OPERR bit in the FPSR except on byte 2 If the source operand is a NAN refer to 4 5 4 NANs for more information Status Register Condition Codes Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Quotient Byte Not affected Exception Byt...

Page 172: ...mber An bd PC Xn 111 011 bd An Xn od 110 reg number An bd PC Xnl od 111 011 Ibd An Xn od 110 reg number An bd PC Xn od 111 011 Only if fret is Byte Word Long or Single R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating...

Page 173: ...ult Hyperbolic Tangent Zero 0 0 O 0 Infinity 1 0 1 0 NOTE Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte if the source operand is a NAN refer to 4 5 4 NANs for more information Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Not affected BSUN SNAN OPERR OVFL UNFL DZ INEX2 INEX1 Cleared Refer to 4 5 4 NANs Cleared Cleared Refer to 6 1 5 U...

Page 174: ...r Single Addressing Mode xxx W xxx L data d16 PC d8 PC Xn bd PC Xn Mode I Register 111 000 111 001 111 100 111 010 111 t 011 111 I 011 bd PC Xn od 111 i 011 bd PC Xn od 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source flo...

Page 175: ...information Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Instruction Format 15 14 13 1 1 I 0 R M 0 Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Not affected BSUN SNAN OPERR OVFL UNFL DZ INEX2 INEX1 Cleared Refer to 4 5 4 NANs Cleared Refer to 6 1 4 Overflow Refer to 6 1 5 Underflow Cleared Refer to 6 1 7 Inexact Result If fret is Pa...

Page 176: ... 111 111 111 111 111 l 111 111 1 Register 000 001 100 010 011 011 011 011 R M Field m Specifies the source operand address mode 0 m The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point data register FPm If R M 1 specifies the source data format 000 L Long Word Integer...

Page 177: ...ithin the trap handler The conditional specifier cc selects one of the 32 conditional tests defined in 4 4 CONDITIONAL TEST DEFINITIONS Status Register Condition Codes Not affected Quotient Byte Not affected Exception Byte BSUN Set if the NAN condition code is set and the condition selected is an IEEE nonaware test SNAN Not Affected OPERR Not Affected OVFL Not Affected UNFL Not Affected DZ Not Aff...

Page 178: ...s one of 32 conditional tests as described in 4 4 CONDITIONAL TEST DEFINITIONS Operand Field Contains an optional word or long word operand that is user defined NOTE When a BSUN exception occurs a pre instruction exception is taken by the main processor If the exception handler returns without modifying the image of the PC on the stack frame to point to the instruction following the FTRAPcc it mus...

Page 179: ...sult none N Zero Infinity I I Z NZ I NI NOTES 1 if the source operand is a NAN set the NAN condition code bit 2 If the source operand is a SNAN set the SNAN bit in the FPSR exception byte Status Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Instruction Format 15 14 13 1 1 1 0 R M 0 Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Not affected B...

Page 180: ... 011 bd PC Xn od 111 011 bd PC Xn od 111 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point data register FPm If R M 1 specifies the source data format 000 L Long Word Integer 001 S Single Precision Real 010 ...

Page 181: ...s Register Condition Codes Quotient Byte Exception Byte Accrued Exception Byte Instruction Format 15 14 13 1 1 1 0 R M 0 Affected as described in 4 5 5 1 SETTING FLOATING POINT CONDITION CODES Not affected BSUN SNAN OPERR OVFL UNFL DZ INEX2 INEX1 Cleared Refer to 4 5 4 NANs Cleared Refer to 6 1 4 Overflow Refer to 6 1 5 Underflow Cleared Refer to 6 1 7 Inexact Result If fret is Packed refer to 6 1...

Page 182: ...C Xn 111 011 Ibd PC Xn 111 011 bd PC Xn od 111 011 bd PC Xn od 111 011 R M Field Specifies the source operand address mode 0 The operation is register to register 1 The operation is ea to register Source Specifier Field Specifies the source register or data format If R M 0 specifies the source floating point data register FPm If R M 1 specifies the source data format 000 L Long Word Integer 001 S ...

Page 183: ...o execute this in struction Freescale assemblers default to ID 1 for the FPCP Type Specifies the type of coprocessor instruction 000 General Instructions Arithmetics FMOVE FMOVEM 001 FDBcc FScc FTRAPcc 010 FBcc W 011 FBcc L 100 FSAVE 101 FRESTORE 110 Undefined Reserved 111 m Undefined Reserved Type Dependent m Normally specifies the effective address or conditional predicate but usage depends on t...

Page 184: ... main processor data register that Icontains the list The FPCPgeneral type instructions are classified into groups based upon instruction func tion and argument location external or internal to the FPCP as follows 1 Floating Point Register to Register 2 External Operand to Floating Point Data Register 3 Move Constant to Floating Point Data Register 4 Move Floating Point Data Register to External D...

Page 185: ...he extension field indicates the operation to be performed Table 4 13 lists the extension field encodings and functions Also shown are the services requested of the MPU by the FPCP 4 7 1 2 EXTERNAL OPERAND TO REGISTER INSTRUCTIONS This class of instructions includes external operand to floating point data register move and arithmetic instructions External operands are located either in memory or a...

Page 186: ...exceptions other then BSUN are enabled The second primitive is null CA 0 to terminate the instruction dialog 2 The FPCPissues the take pre instruction exception primitive with a vector number of 11 to instruct the MPU to take an F line emulator trap 3 Some extension field encodings are unspecified are redundant with valid instructions implemented by the FPCP end do not cause an F line exception if...

Page 187: ... field values for the FMOVECR instruction The only service required by the FPCP from the MPU is the passing of the MPU PC to FPIAR if exceptions other than BSUN are enabled This service is requested with the null CA 1 PC 1 primitive 4 7 1 4 MOVE TO EXTERNAL DESTINATION INSTRUCTIONS External destinations are either memory or an MPU data register Data format conversion from the extended data format ...

Page 188: ...ng of 111 indicates a packed decimal string destination with the formatting parameter k in an MPU data register The extension field contains the number of the MPU data register that contains the k factor The MPU data register number is encoded in bits 6 4 of the extension field bits 3 0 should be zero The seven least significant bits of the MPU data register contain a twos complement k factor The ...

Page 189: ...er the MPU data register containing the k factor b Null CA 1 IA 1 is used to force the MPU to wait while the conversion takes place c Evaluate effective address and transfer data CA 1 is issued to request the transfer of the converted operand d Null CA 0 is used to terminate the dialog if no exceptions occurred If an exception occurred the take mid instruction exception primitive is used to termin...

Page 190: ...e address a d transfer data CA 1 indicating the appropriate transfer size and allowed effective addressing mode The second primitive is null CA 0 to terminate the instruction dialog 2 For the current implementation of the FPCP this encoding is redundant with the 001 encoding of the regi er se e field i e it selects the FPIAR as the only register to be moved however this encoding is reserved for fu...

Page 191: ... in the command word for the various mode field encodings is shown in the following table If a bit in the register list is set then the corresponding register is moved otherwise the list is scanned for the next bit that is set For the dynamic register list format rrr specifies the MPU data register that contains the register list X means either zero or one The format of a dynamic register list is ...

Page 192: ... three primitives the first is the transfer single main processor register CA l primitive to request the transfer of the MPU data register that contains the dynamic register list The second is the transfer multipTe coprocessor registers CA 1 primitive to request that the MPU evaluate the effective address read the register seTe CIR and transfer the number of registers indicated by the mask with an...

Page 193: ...o 1 the MPU proceeds to the next instruction otherwise the 16 bit disp acement is sign extended and added to the PC The MPU takes an F line emulation trap The MPU writes the conditional predicate to the FPCPfor evaluation The null CA 0 primitive is used to return the true false evaluation If the condition is true then the cpTRAPcc exception is taken Oth erwise the MPU proceeds to the next instruct...

Page 194: ...ess Than or Equal Note 2 010110 GL Greater Than or Less Than Note 2 010111 GLE Greater Than or Less Than or Equal Note 2 011000 NGLE Not Greater Than or Less Than or Equal Note 2 011001 NGL Not Greater Than or Less Than Note 2 011010 NLE Not Less Than or Equal Note 2 011011 NLT Not Less Than Note 2 011100 NGE Not Greater Than or Equal Note 2 011101 NGT Not Greater Than Note 2 I 011110 SNE j Signah...

Page 195: ...s determined by the MPU and is transparent to the FPCP Also the FNOP instruction syntax that is recognized by Freescale assem blers generates an FBcc W instruction with cc F false and a displacement value of zero 4 7 4 Save Instruction Format The FSAVE instruction indicates that the FPCP must immediately suspend any current operation and save the internal state in memory Effective addressing modes...

Page 196: ...pecifies the M68000Family addressing modethat is to be used to locate operands external to the FPCP if required by the instruction For some operations restrictions are placed on which of the available addressing modes are allowed These restrictions are enforced by hardware in the MPU and FPCP and Freescale assemblers do not generate operation words with disallowed effective addressing mode field e...

Page 197: ... with Displacement 111 010 X X X d16 PC Program Counter Indirect with Index 111 011 X X X d8 PC Xn 8 Bit Displacement Progr m Counter Indirect with Index 111 011 X X X bd PC Xn Base Displacement PC Memory Indirect Postindexed 111 011 X X X Ebd PCl Xn od PC Memory Indirect Preindexed 111 011 X X X bd PC Xn od Immediate 111 100 X X data 4 8 5 Destination Register Field This field is common to all of...

Page 198: ... or Less Than 001101 Unordered or Less Than or Equal 001110 Not Equa 001111 True 010000 Signaling False 010001 Signaling Equal 010010 Greater Than 010011 Greater Than or Equal 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 OR UN UEQ UGT UGE ULT ULE NE T SF SEQ GT GE LT LE GL GLE NGLE NGL NLE NLr NGE NGT SNE ST Less Than Less Than or Equal Greater Than or Less T...

Page 199: ... O SOURCE DESTINATION 0 R M 0 SPECIFIER REGISTER 6 5 4 3 2 I 0 EFFECTIVEADDRESS 0 MODE REGISTER 0 0 0 I 0 0 I 0 FINTRZ 15 14 13 12 11 10 9 8 7 I COPROCESSOR I 1 1 1 1 ID O O SOURCE DESTINATION 0 R M 0 SPECIFIER REGISTER 6 5 4 3 2 1 0 EFFECTIV A D D R E S S 0 MODE REGISTER o ololo ol FSQRT 15 14 13 12 11 10 9 8 7 COPROCESSOR 1 1 1 l ID 0 0 SOURCE DESTINATION 0 R M 0 SPECIFIER REGISTER 6 5 4 3 2 1 0...

Page 200: ... EFFECTIVEADDRESS 1 ID 0 0 0 MODE REGISTER SOURCE DESTINATION I 1 1 i i SPECIF ER REGISTER O 0 O_ 1 0 I 1 O FASIN 15 14 13 1 1 1 0 R M I 0 12 11 l0 9 8 7 6 5 4 3 2 1 Q 1 ID 0 0 0 MODE i REGISTER sou c l i i i SPECIFIER REGISTER 0 0 0 1 i D C FATAN H 15 14 13 0 RIM 0 12 II I0 9 8 7 6 5 4 3 2 I 0 I COPROCESSOR I 1 ID I 0 SOURCE DESTINATION SPECIFIER REGISTER i EEEECTIV ADDRESS o MODE REO STE I 1 o o...

Page 201: ...ATION SPECIFIER REGISTER 6 5 4 3 2 EFFECTIVEADDRESS 0 MODE REGISTER o l l oo FTENTOX 15 14 1 O R M 13 12 1 1 10 9 8 7 COPROCESSOR 1 1 IO 0 0 SOURCE DESTINATION 0 SPECIFIER REGISTER G 5 4 3 2 EFFECTIVEADDRESS 0 MODE REGISTER o o 1o o1 1o FLOGN 15 14 13 12 t 1 1 I 0 R M 0 11 10 9 8 7 COPROCESSOR IO 0 0 SOURCE DESTINATION SPECIFIER REGISTER 6 5 4 3 2 EFFECTIVEAODRESS 0 MODE REGISTER 0 011 0 1 0 I 0 F...

Page 202: ...1 ID 0 0 0 SOURCE DESTINATION 0 SPECIFIER REGISTER 0 S 4 3 2 1 C EFFECTIVEADDRESS MODE REGISTER O 1 I 0 1 0 1 FNEG 15 14 13 1 1 1 0 RIM O 12 11 IO 8 7 SOURCE DESTINATION SPECIFIER REGISTER 0 5 4 3 2 I C EFFECTIVEADDRESS MODE t REGISTER oll oi 1o FACOS t5 14 13 1 1 1 O RIM O 12 11 10 9 8 7 6 COPROCESSOR I ID 0 0 0 SOURCE DESTINATION SPECIFIER REGISTER 0 5 4 3 2 I C EFFECTIVEADDRESS MODE I REGrSTER ...

Page 203: ...ION SPECIFIER REGISTER 5 4 3 2 1 0 EFFECTIVEADDRESS MODE REGISTER I 0 0 0 0 0 FMOD 15 14 13 I 1 1 0 WM 0 12 11 10 9 8 7 1 I COPROCESSOR l I D 0 0 SOURCE DESTINATION SPECIFIER REGISTER 5 4 3 2 1 O EFFECTIV ADDRESS MODE REGISTER 110 0 0 0 1 FADD 15 14 1 1 0 R M 13 12 11 10 9 8 7 I COPROCESSOR 1 1 IO 0 0 SOURCE DESTINATION 0 SPECIFIER REGISTER 5 4 3 2 1 0 EFFECTIVtADDRESS MODE REGISTER Fold Oll o FMU...

Page 204: ...GISTER 0 5 4 3 2 I 0 EFFECTIVEADDRESS I MODE REGISTER o o o L FSGLMUL 15 14 13 1 1 1 0 RIM 0 12 11 l0 9 8 7 6 COPROCESSOR I I ID 0 0 O SOURCE DESTINATION SPECIFIER RESISTER 0 5 4 3 2 I 0 EFFECTIV ADDRESS MODE REGISTER l o l o 1 I I FSUB 15 14 13 1 1 I 0 R M 0 I2 El 10 9 8 7 6 J COPROCESSOR I I ID 0 0 0 SOURCE I DESTINATION SPECIFIER REGISTER 0 5 4 3 2 I 0 EFFECTIVEADDRESS MODE J REGISTER 1 0 1 O O...

Page 205: ...stination Format Field Specifies the data format of the destination operand as fol lOWS 000 Long Word Integer 001 Single Precision Real 010 Extended Precision Real 011 Packed Decimal Real static k factor 100 Word Integer 101 Double Precision Real 110 Byte Integer 111 Packed Decimal Real dynamic k factor k factor Field Specifies the format of the packed decimal string to be generated if the destina...

Page 206: ...ed 000 Undefined reserved 100 FPCR 001 w FPIAR 101 FPCR then FPIAR 010 FPSR 110 FPCR then FPSR 011 FPSR then FPIAR 111 FPCR then FPSR then FPIAR FMOVEM FPn 15 14 1 1 1 1 13 12 11 10 9 8 7 6 5 4 3 2 I 0 COPROCESSOR EFFECT V ADDRESS 1 113 0 0 0 MODE REGISTER dr MODE I 0 l_ 0 0 REGISTERLIST dr Field Specifies the direction of the transfer 0 Move the listed registers from memory to the FPCP 1 Move the...

Page 207: ...PREDICATE FDBcc 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 l 0 I 0 0 O 0 CONDITIONALPREDICATE 16 BIT DISPLACEMENT Count Register Field Specifies the main processor data register to be decremented FTRAPcc 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 I i i i 0 0 0 0 0 O I 0 O 0 0 CONDITIONALPREDICATE 16 GIT0PERANO ORMOST SIGNIFICA T WORDOF3Z B TOPERAND IFNEEDED LEASTSIGNIFICANTWORDOF32 81TOPERAND IF NEEDE...

Page 208: ...ED Size Field Specifies the size of the twos complement displacement Size 0 Displacement is 16 bits and is sign extended before it is used Size 1 Displacement is 32 bits 5 4 3 2 1 0 EFFECTIVE tADDRESS MODE REGISTER FSAVE 15 14 13 12 11 10 9 8 7 6 FRESTORE 15 14 13 12 11 10 9 8 7 6 1 I 1 1 COPROCESSORID 1 I I 1 0 1 5 4 3 2 1 EFFEDTIV ADDRESS MODE REGISTER FREESCALE 4 150 MC68881 MC68882 USER S MANU...

Page 209: ...n the MC68881 can be used on the MC68882 without alteration but optimization of code for the MC68882 provides significant reduction in execution time The following paragraphs describe the concurrency available with the MC68881 the greater concurrency provided by the MC68882 and optimization techniques for MC68882 programs 5 1 1 Concurrency The M68000 coprocessor interface the MC68020 and MC68030 m...

Page 210: ...d operands to the coprocessor the main processor is free to perform other instructions Meanwhile the coprocessor converts the operand to internal format calculates the result and rounds the result as required The concurrency shown in Figure 5 1 for an MC68881 applies also to an MC68882 M 020 8030 c0 U E CY J M C 6 8 8 8 1 F M U L CALCULATE Figure 5 1 MC68881 Concurrency FMUL Instruction 5 1 1 2 CO...

Page 211: ...does the following a Prefetches the source operand from memory by using the evaluate ea and transfer data primitive with CA 0 This releases the main processor immediately after the source operand is written to the operand CIR b Converts the memory source operand to internal extended format If the selected rounding precision is single or double waits until the APU is idle and hands off the instruct...

Page 212: ...ngle or double precision converts the source operand to the extended precision internal format c Creates a tag that represents the data type of the converted source operand nor malized unnormalized denormalized zero infinity or NAN d Waits until the APU is idle and hands off the instruction to the APU Table 5 1 lists the minimum concurrency instructions The monadic operations designated mop in Tab...

Page 213: ...Instructions Instruction Function FABS Absolute Value FACOS Arc Cosine FASIN Arc Sine FATAN Arc Tangent FATANH Hyperbolic Arc Tangent FCOS Cosine FCOSH Hyperbolic Cosine FETOX ex FETOXM1 ex 1 FGETEXP Extract Exponent FGETMAN Extract Mantissa FINT Extract Integer Part FINTRZ Extract Integer Part Rounded to Zero FLOGN In x FLOGNPI In x 1 FLOGIO Logl0 X FLOG2 Log2 x FNEG Negate FSIN Sine FSINH Hyperb...

Page 214: ... 5 Fully Concurrent Instructions Instruction Operand Operand Syntax Format FMOVE FPm FPn X FMOVE ea FPn S D FMOVE ea FPn X FMOVE FPm ea FMOVE FPm ea S D a X a a Register Conflict of FPm with preceding instruction s des tination floating point data register b NAN Unnormalized or Denormalized Data Types c Rounding Precision in FPCRset to Single or Double d INEX2 bit in FPCR EXC byte is enabled e An ...

Page 215: ...OVEinstructiOn as shown in Figure 5 2 The following assumptions apply 1 Both FMUL instructions have external operands opclass 010 2 The FMOVE instruction has a memory destination opclass 011 and 3 No exceptions are enabled The main processor initiates the second FMUL instruction and the MC68881 returns the null CA l primitive as long as the APU is involved in the calculate phase of the first FMUL ...

Page 216: ...gins executing the FMOVE instruction Since the CU contains the converted operand for the second FMUL instruction at this time it is not available to convert the source operand of the FMOVE instruction However when the APU completes the rounding phase for the first FMUL instruction it accepts the operand from the CU and begins calculations for the second FMUL instruction The CU now converts the sou...

Page 217: ... point data registers A register conflict occurs when the destination register of an instruction is the source register of the following instruction and that instruction is afully concurrent instruction listed in Table 5 5 For example FADD D ea FP0 FMOVE D FP0 ea FP0 conflicts A register conflict occurs when the destination register of an instruction is the desti nation register of the following i...

Page 218: ...nstructions Notice that FP1 contains the result of the computations using index il and that FP2 contains the result of the computations using index i 1 Also notice that the two FMOVE instructions that move registers to registers are executed following FADD instructions and that the FMOVE instructions that move registers to effective ad dresses are executed following FMUL instructions Figure 5 5 sh...

Page 219: ...8882 than for the MC68881 The MC68882 uses the additional bytes to store the state of the conversion unit 5 2 2 Exception Handler Code The code for floating point exception handlers for the MC68882 must include the following instructions 1 An FSAVE instruction at the beginning of the handler ahead of the first coprocessor instruction 2 A BSET or similar instruction following the FSAVE instruction ...

Page 220: ...mpleted Figure 5 6 shows the required instructions in a minimum exception handler for an MC68882 HANDLER FSAVE SP SAVEINTERNALSTATE MOVE B SP O0 FIRSTB q EOFSTATEFRAME BEQ NULl BRANCHIF NULLFRAME CLR L DO CLEARDATAREGISTER MOVE B I SP DO LOADSTATEFRAMESIZE BSET 3 SP DO SETBIT 27 OFBIU NULL FRESTORE SP RESTORESTATE RTE RETURN Figure 5 6 Minimum Exception Handler An exception handler can access the ...

Page 221: ...VE instruction 5 2 3 2 BUS ARBITRATION During execution of a floating point instruction the MPU can relinquish control of the bus through bus arbitration If the FPCP has released the MPU and is completing execution of the instruction relinquishing the bus has no effect on the coprocessor If the MPU is involved in a dialog with the coprocessor relinquishing the bus delays the execution of the instr...

Page 222: ...or instruction has no effect on the coprocessor Either the main processor or the coprocessor can detect an exception during execution of a floating point instruction The handlers for these exceptions are bracketed with FSAVE and FRESTORE instructions as previously described to ensure that coprocessor state in formation about concurrently executing instructions is properly restored after execution ...

Page 223: ...s that the floating point exception has not been serviced The FADD instruction is not allowed to continue 7 The floating point exception handler is executed This handler includes a BSET in struction that sets bit 27 of the BIU flags word When the FRESTORE instruction restores the state frame the FADD instruction continues In this example if the interrupt handler allowed the FADD instruction to con...

Page 224: ...ception handler executes at this point See text Figure 5 9 Coprocessor Identification Code The FNOP instruction takes an F line emulation exception when no floating point copro cessor is available The F line emulation exception handler must set the no coprocessor flag and increment the stacked PC value by four The BNE instruction branches around this code when no coprocessor is present The instruc...

Page 225: ...ndler 7 Return to the previous context The first two steps involve slightly different operations for exceptions detected by the main processor and those detected by the FPCP but the manner in which these operations are performed is consistent with noncoprocessor related exceptions The major difference in the processing of exceptions detected by the FPCP and the main processor is the point at which...

Page 226: ...to the command or condition coprocessor inted ace register CIR Then instead of returning the first primitive of the dialog for the new in struction the FPCP returns the take pre instruction exception primitive to start exception processing for the offending instruction For the MC68881 the offending instruction is always the previous floating point instruction since no multiple floating point concu...

Page 227: ...ion request 3 The MPU acknowledges the request by writing an exception acknowledge to the control CIR The appropriate stack frame is then stored in memory and control is transferred to the exception handler routine 4 The response to the exception acknowledge differs for the type of exception and for the FPCP as follows a Protocol violation MC68881 Aborts all internal operations that may be active ...

Page 228: ... or disabled FPCP instruction exceptions arise from the detection of abnormal conditions during coprocessor instruction execution All coprocessor detected instruction exceptions are enabled or dis abled via the FPCRENABLE byte Any of eight exception conditions can be detected during the execution of a floating point instruction The location of the exception bits in the EXC and ENABLE bytes contain...

Page 229: ...st associated with the FBcc FDBcc and FTRAPcc instructions when an unordered condition is present An unordered condition occurs when an input to an arithmetic operation is a NAN The BSUN exception can only occur during FPCP conditional instructions with the following IEEE nonaware branch condition predicates GT Greater Than NGT Not Greater Than GE Greater Than or Equal NGE Not Greater Than or Equa...

Page 230: ...ves incrementing the stored program counter in the stack to bypass the conditional instruction This technique applies to situations where a fall through is desired Be aware that accurate calculation of the program counter increment requires detailed knowledge of the size of the conditional instruction being bypassed The second method is to clear the NAN bit of the FPSRcondition code byte However t...

Page 231: ...rrors not frequent or important enough to merit a specific exception con dition Basically an operand error occurs when an operation has no mathematical inter pretation for the given operands The possible operand errors are listed in Table 6 2 When an operand error occurs the OPERR bit is set in the FPSR exception status byte Trap Disabled Results For a memory or MPU data register destination sever...

Page 232: ... Source infinity FSUB Source and floating point data registerare infinity or source and FPn are infinity FTAN Source is infinity Trap Enabled Results For memory or MPU data register destinations the destination operand is written as if the trap were disabled and then a take exception primitive is returned to the MPU This can only occur for the FMOVE FPm ea instruction and the exception is reported...

Page 233: ...ons when the intermediate result exponent is greater than or equal to the maximum exponent value of the destination data format Overflow can only occur when the destination is in the S D or X format Overflows when converting to the B W or L integer and packed decimal formats are included as operand errors Refer to 3 6 DATA FORMAT DETAILS for the maximum exponent value for each format At the end of...

Page 234: ...d is the intermediate result mantissa rounded to the destination precision with a 15 bit exponent biased as a normal extended precision number In the case of a memory destination the evaluated effective address of the operand is available in the MPU mid instruction stack frame at offset 10 This allows the trap handler to overwrite the default result if necessary without recalculating the effective...

Page 235: ... Underflow can only occur when the destination format is S D or X When the destination format is packed decimal underflows are included as operand errors When the destination format is B W or L the conversion underflows to zero without causing either an underflow or an operand error See 3 6 DATA FORMAT DETAILS for the minimum exponent value for each format At the end of any operation that could po...

Page 236: ... MPU reads the response CIR of the FPCP Since the MC68881 does not allow multiple floating point concurrency the ex ception is always reported as a pre instruction exception when the next floating point instruction is attempted The MC68882 however may report an exception as a mid instruction exception on a subsequent floating point instruction The address of the instruction that caused the underfl...

Page 237: ...s NOTE The IEEE standard defines two causes of an underflow 1 When a result is very small the absolute value of the number is less than the minimum number that can be represented by a normalized number in a specific format When loss of accuracy occurs while attempting to calculate a very small number a loss of accuracy also causes an inexact exception The IEEE standard specifies that if the underf...

Page 238: ...ister is not modified and a take exception primitive is returned when the MPU reads the response CIR of the FPCP Since the MC68881 does not allow multiple floating point concurrency the exception is always reported as a pre instruction exception when the next floating point instruction is attempted The MC68882 however may report an exception as a mid instruction exception on a subsequent floating ...

Page 239: ... byte and the infinitely precise result is rounded as described in the next paragraph The FPCPsupports the four rounding modes specified by the IEEE standard These modes are round to nearest RN round toward zero RZ round toward plus infinity RP and round toward minus infinity RM The rounding definitions are Rounding Mode Result RN The representable value nearest to the infinitely precise intermedi...

Page 240: ...lways in the extended precision format However if the single or double precision rounding mode is in effect the final result generated by the FPCP is within the range of the format except for the FSGLDIV and FSGLMUL instructions as described in 4 5 5 2 UNDERFLOW ROUND OVERFLOW Range control is accomplished by not only rounding the intermediate result man tissa to the specified precision but also c...

Page 241: ...is returned immediately after the operand is stored If the destination is a floating point data register a take exception primitive is returned when the MPU reads the response CIR of the FPCP Since the MC68881 does not allow multiple floating point concurrency the exception is always reported as a pre instruction exception when the next floating point instruction is attempted The MC68882 however m...

Page 242: ...rounded result is stored in the floating point data register If the instruction is not an FMOVE the rounded result is used in the calculation Trap Enabled Results The result is generated in the same manner as if traps were disabled except that a take exception primitive is returned when the MPU reads the response CIR of the FPCP Since the MC68881 does not allow multiple floating point concurrency ...

Page 243: ...mine when to trap there are seven possible instruction traps defined INEX1 and INEX2 share one exception vectorl instead of the five defined by the standard If it is necessary to write an application program that only supports the five IEEE specified traps the BSUN SNAN and OPERRexception vectors should be set to point to the same handler routine This allows the FPCPto support the invalid operatio...

Page 244: ...resumes execution of the main program at the beginning of the illegal coprocessor command by writing to the command CIR again The illegal instruction exception is then reported by the FPCP 6 1 12 Coprocessor Detected Protocol Violation All interprocessor communications in the coprocessor interface occur as standard M68000 bus cycles A failure in this communication results in the FPCP reporting a m...

Page 245: ... MC68881 always terminates the access by immediately asserting DSACKx Note that in certain cases resulting from serious system programming errors an unre coverable protocol violation may occur when using the MC68882 This particular case of the protocol violation occurs during the coprocessor interface dialog for the FMOVE and FMOVEM instructions if a read of the operand CIR occurs before the evalu...

Page 246: ...ration being executed previously is aborted and the FPCPassumes the idle state when theexception acknowledge is received Therefore the primitive read from the response CIR is null CA 0 If the protocol violation is detected by the MPU due to an illegal primitive the FPCP response CIR contains that primitive when the exception handler reads it Since the FPCPcannot internally generate an illegal prim...

Page 247: ...he next instruction Note that after a take mid instruction exception primitive is re turned the main processor is not required by the MC68881 to perform a read from the response CIR before initiating the next floating point instruction but the MPU always performs this action when processing a mid instruction stack frame An MC68881 arithmetic exception handler i e a handler for any exception other ...

Page 248: ...n response to this exception contains two uointer values 1 A pointer to the FTRAPcc instruction that caused the exception 2 A pointer to the instruction that follows the FTRAPcc the pointer to which the pro cessor returns if an RTE instruction is executed 6 2 2 Illegal Instructions The FPCPinstructions consist of an operation word a coprocessor command word if any and extension words if any The MP...

Page 249: ... This allows a debugging program in the trace exception handler to monitor the execution of a program under test Refer to the main processor user s manual for a complete description of the trace mode Many FPCP instructions can operate concurrently with MPU instructions and defer the reporting of coprocessor detected instruction exceptions until the next FPCPinstruction is dispatched by the MPU Thi...

Page 250: ...he user visible context followed by an FRESTORE instruction to reinstate the exact context of the FPCP prior to the trace exception processing Note that since the MPU is forced to wait until the completion of an FPCP instruction before processing a pending trace exception the exe cution of the FSAVE instruction by the trace handler always results in an idle state frame being saved The user visible...

Page 251: ...UPT LATENCY TIMES for more information 6 2 6 Address and Bus Errors Bus cycle faults may occur while processing FPCPinstructions during the MPU accesses of the coprocessor interface registers or during memory cycles run by the MPU to access instructions or data If the MPU receives a fault while running the bus cycle which initiates an FPCP instruction i e the initial write to the command or condit...

Page 252: ...re met the resulting MC68882 handlers can be used with no adverse effects for systems that use the MC68881 Since the MC68882 is pin compatible and user software compatible with the MC68881 the exception handlers can be written to meet the system software requirements of both the MC68881 and the MC68882 When this is done systems that only use the MC68881 at present can replace the MC68881 with the ...

Page 253: ...e of the FPCPwhen an FSAVE instruction is executed the format of the internal state information written to memory may be in one of three forms idle null or busy Also the FPCP may force the MPU to wait for a short time while the internal state is prepared for the save operation During execution of an FRESTORE instruction the FPCP interprets the state information read from memory and written to the ...

Page 254: ...contain 32 additional bytes which store the CU internal state Second the saved CU internal state is saved at the top of the frame immediately following the format word This results in offsets to the APU information that are greater than those for cor responding data in the MC68881 state frames by 20 The null state frame consists only of the format word in both coprocessors When an FSAVE instructio...

Page 255: ...ormat word is written to the FPCPto initiate the restore operation When this occurs the FPCP checks the version number and frame size values for validity and signals a format exception if they are not valid for this particular device The version number is an 8 bit value that identifies the microcode version of the FPCP and the format of this number is defined internally by the FPCP Future devices ...

Page 256: ... IDLESTATE FRAME As shown in Figure 6 4 24 bytes of internal state are saved in the idle state frame for the MC68881 For the MC6882 the idle state frame consists of 56 bytes see Figure 6 5 The format word indicates the coprocessor version number and state size 24 or 56 bytes in addition to the format word An idle state frame is produced if an FSAVE occurs when a floating point instruction is not b...

Page 257: ... These bits can be used to qualify the image of the operand register and should not be modified Bits 24 25 These bits contain internal state information about the CU and should not be modified Bit 26 This bit indicates that the FPCP has completed any necessary operand conversions and is ready to write an operand to memory If this bit is a zero an operand transfer to memory is pending This bit shou...

Page 258: ...30 combine to define the pending operation as listed in Table 6 4 Bit 29 Bit 30 This bit defines the type of pending operand access that is expected or the type of pending operation that is saved in the command condition register image This bit should not be modified Bits 28 30 combine to define the pending operation as listed in Table 6 4 This bit indicates that the FPCP has received a new comman...

Page 259: ...er the completion of the transfer of a floating point operand to memory If EXC PEND is true when an attempt is made to initiate an FPCP instruction other than an FMOVEM FMOVE control register FSAVE or FRESTORE the response CIR is encoded to the take pre instruction exception primitive or the take mid instruction primitive when the instruc tion in the CU is reporting an exception caused by the inst...

Page 260: ...he copro cessor is ready to transfer the state frame and also what size frame is to be saved If the FPCP is not ready to begin the transfer of the state frame it returns the come again format word forcing the MPU to wait When the MPU receives the come again format word it checks for pending interrupts and processes them if necessary Otherwise it repeatedly reads the save CIR until a format word ot...

Page 261: ...s considered to be a catastrophic system error since the FPCP context is lost and cannot be recovered When the MPU receives an idle or busy format word the bytes in the frame four bytes at a time are transferred from the operand CIR to memory First the format word is written to memory at the evaluated effective address For the predecrement addressing mode the value of the specified address registe...

Page 262: ...come again format word to the MPU The MPU repeatedly reads the save CIR until it receives a valid format word The FPCP continues internal processing up to the next checkpoint at which time processing stops and the next read of the save CIR acquires the appropriate format word to start the save operation At this point the save command proceeds to completion and the FPCP supplies a busy state frame ...

Page 263: ...ad the response CIR If an exception related to the FPCP caused the suspension of the task earlier an RTE instruction is eventually executed to return to the original context Depending on the exception type the RTE may re establish the MCU coprocessor protocol of the suspended operation or begin the exe cution of a new FPCPinstruction 6 4 5 Context Switching Summary To perform a complete context sa...

Page 264: ...SAVECONTROLREGISTERS PLACENOT NULLFLAGONSTACK INSTRUCTIONSEQUENCETO LOADTHENEXTCONTE Q TST B An BEQ NULL_RST ADDQ L 4 An FMOVEM An FPCR FPSR FFIAR FMOVEM An FPO FP7 FRESTORE An CHECKFORNULLFRAMEORNOT NULLF G SKIPPROGRAMMER SMODEL RESTOREIFNULL ELSE THROWAWAYTHENOT NULLFLAG RESTORETHE CONTROLREGISTERS RESTORETHEDATAREGISTERS RESTORETHEFPCPSTATEFRAME Figure 6 7 Full Context Save Restore Instruction ...

Page 265: ...he MPU A main processor other than an MPU explicitly accesses the FPCPCIRs using a software routine that simulates the behavior of the MPU with respect to the coprocessor interface For more information on the electrical interconnecti0n between the main processor and the FPCP refer to SECTION 11 INTERFACING METHODS 7 1 CHIP SELECT DECODE The MPU does not require any special bus signals beyond the n...

Page 266: ...RUL rlON ADDP SS OPERAND ADDRESS Figure 7 2 FPCP Coprocessor Interface Register Map The FPCPchip select decode therefore uses the MPU function codes FC2 FC0 the CPU space type field A19 A16 and the Cp ID field A15 A13 The FPCPdecodes the address bits A4 A0 to determine the function as defined by the selected CIR of any coprocessor access 7 2 COPROCESSOR INTERFACE REGISTERS Table 7 2 identifies the...

Page 267: ... 1C These CIRs are optionally implemented by a coprocessor only if they are needed since they are not used by the MC68881 they are not implemented Writes to these locations are ignored and reads always return all ones 7 2 1 Response CIR 00 This 16 bit read only register is used to communicate service requests from the FPCP to the main processor A read of the response CIR is always legal regardless...

Page 268: ...n a new instruction protocol following the write cycle Unlike the MC68881 the MC68882 distinguishes a write to the AB bit from a write to the XA bit A write to the AB bit is interpreted as an abort of the last instruction receh ed However an abort is only recognized during a certain window which begins when the main processor writes an instruction to the command CIR and extends to the last CIR rea...

Page 269: ...e executing and prepare to load a new internal state context from a memory resident state frame After the main processor writes a format word to the restore CIR it must read the restore CIR to receive the result of the format word verification If the written format wora is valid that format word is read back from the restore CIR to indicate the successful verification If the format word is invalid...

Page 270: ...ed condition and returns the null CA 0 TF x primitive where the TF bit indicates whether the conditional evaluation is true 1 or false 0 A write to this CIR location is legal at any time except when the FPCP is in the initial phase of a general instruction or before the read of the conditional evaluation for a previous conditional instruction If a write to the condition CIR occurs when it is not e...

Page 271: ...e least significant eight bits are always read as zeros The most significant eight bits contain the register mask for the multiple register transfer with each bit set if the corresponding floating point register is to be transferred The main processor should not interpret the order of the bits in the register mask but rather count the number of ones in the mask to determine the number of registers...

Page 272: ...address register for the APU This implementation is necessary to ensure that an exception handler can point to the correct instruction the one that causes the exception However this implementation requires that the instruction address CIR be writ ten whenever the MC68882 requests it The MC68882 issues a protocol violation whenever the main processor fails to supply the requested program counter va...

Page 273: ... coprocessor operation is selected general branch conditional save or restore The type and type dependent fields and the coprocessor command word for all FPCP instructions are described in 4 7 INSTRUCTION ENCODING DETAILS 7 4 1 Instruction Protocol All FPCP instructions have a typical protocol which the MPU and FPCP use This com munication protocol is as follows 1 When the MPU detects an F line op...

Page 274: ...s summarize all FPCPresponse primitives and how they are used The M68000 coprocessor response primitives are encoded in a 16 bit word that is trans ferred to the main processor through the response CIR Figure 7 7 illustrates the general format of a response primitive 15 14 13 12 11 I0 9 8 7 6 5 4 3 2 0 ICAI PCIDR I FUNCTION I PARAMETER I Figure 7 7 M68000 Coprocessor Response Primitive General For...

Page 275: ...tives issued by the MC68881 with the exception of the null primitive have the CA bit equal to one causing the MPU to check the response CIR after any service is performed This allows the MC68881 to assure correct internal operation and to report exceptions immediately after a service is performed However the MC68882 may occasionally issue an evaluate ea and transfer data primitive with CA equal to...

Page 276: ...instruction can be executed This re sponse is also used when a new FPCP instruction is initiated while a previous one is still being executed The expected response is for the main processor to re read the response CIR after servicing pending interrupts The same as the preceding response except that the main processor is requested to pass the current program counter before processing any pending in...

Page 277: ...ddress that is to be evaluated is specified in the F line operation word and any required extension words are fetched by the main processor as needed If the prede crement or postincrement addressing mode is used the address register is decremented or incremented before or after the transfer by the size of the operand as indicated in the length field The valid EA field specifies various classes of ...

Page 278: ... as the first primitive of an instruction dialog to request the transfer 1 0 0 111 4 of one or more control registers from memory or a main processor reg 1 0 0 101 4 ister to the FPCP The length field indicates the total size of all control 1 0 0 110 8 registers to be moved 4 bytes per register 1 0 0 110 12 FMOVE FPcr ea and FMOVEM FPcr_list ea OPCLASS 101 Issued as the first primitive of an instr...

Page 279: ...te that the FPCP returns this primitive only once during an instruction dialog When this primitive is read from the response CIR it is discarded by the FPCP and the response encoding is changed to the null primitive until the request has been serviced By doing this the FPCP avoids spurious service requests in systems where the MPU is not the main processor The meanings of the CA and PC bits are as...

Page 280: ...ck using the An addressing mode The designated stack pointer is decremented by 12 bytes before the transfer of each register Then the bytes within each register are written to memory with ascending addresses Thus the address register is decremented by the total number of bytes transferred by the end of the primitive execution 7 4 2 5 TAKE PRE INSTRUCTION EXCEPTION PRIMITIVE Take exception primitiv...

Page 281: ...sly executed concurrent instruction This primitive is also returned if an illegal command word is written to the command CIR or if a protocol violation occurs Finally this primitive is issued when a conditional instruction is executed that utilizes one of the IEEE nonaware conditional predicates and the NAN bit in the FPSR condition code byte is set The format of this primitive is shown in Figure ...

Page 282: ...3 2 1 0 I01 10 0 I VECT0 Ms I Figure 7 15 Take Mid Instruction Exception Primitive Format The CA bit is always zero for this primitive because there is an implied protocol pre emption in this service request The PC bit is always zero since a null primitive earlier in the dialog for the move out instruction is used to request the program counter transfer The vector number identifies the type of the...

Page 283: ...agraphs describe in detail the coprocessor communications dialogs that are executed by the FPCPand MPU during each floating point instruction In this discussion a dialog refers to the sequence of command and data transfers to the FPCP and the service request primitives that are returned to control that sequence Although the following dis cussion assumes that the main processor is an MC68020 or MC6...

Page 284: ...d 4900 Null CA 0 PC 1 IA 1 PF 0 TF 0 5504 Evaluate ea and Transfer Data Single 5608 CA 0 PC 1 DR 0 External to MC68882 Double 560C Extended 5C30 Take Pre lnstruction Exception Branch or Set On Unordered PC 0 810C Transfer Multiple Coprocessor Registers CA l PC 0 DR 0 Memory to FPCP 8900 Null CA 1 PC 0 IA I PF 0 TF 0 8C00 8C01 8C02 8C03 8C04 8C05 8C06 8C07 9501 9502 9504 9608 960C 9704 Transfer Sin...

Page 285: ...s Similarly if the FPCPis not idle before the initiation of a new instruc tion multiple reads of the null CA 1 IA 1 8900 primitive may occur after the command or condition CIR write and before the read of the first primitive shown in a diagram 7 5 1 General Instructions This group of instructions includes all of the arithmetic instructions the move system control register instructions the move ins...

Page 286: ...o be as much as 1 5 times the MC68882 clock frequency For main processors other than the MC68020 or MC68030 the system designer must ensure that the main processor does not read the response CIR during the initiation of an instruction less than three MC68882 clocks after the last operand transfer of the previous instruction 7 5 1 1 REGISTER TO REGISTER OPCLASS 000 This dialog is utilized for all o...

Page 287: ...MC68030 as the main processor When an encoding is indicated for the Response CIR it is not changed until a new encoding is given Figure 7 17 MC68881 Register to Register Instruction Dialog thus avoiding spurious request primitives in non MPU based systems The MC68881 dialog for this instruction type which also applies to the MC68882 with operand data formats other than single double or extended is...

Page 288: ...hile it is an opclass 010 instruction uses the register to register protocol described in 7 5 1 1 REGISTER TO REGISTER OPCLASS 000 7 5 1 3 REGISTER TO EXTERNAL OPCLASS 011 This dialog is utilized onlyforthe move from floating point data register instruction The MC68881 dialog for this instruction type which also applies to the MC68882 except when the data format is single double or extended is sho...

Page 289: ...e encodings shown in Figure 7 20 with the notation PC x For the packed decimal with a dynamic k factor case the dark shaded operations are always performed with the PC bit set if necessary The MPU services the transfer single main processor primitive with the PC bit set by first transferring the program counter and then transferring the requested register For all other destination data formats the...

Page 290: ...l registers instructions The dialog for this instruction type is shown in Figure 7 22 The first primitive of the dialog requests that the main processor evaluate the effective address and transfer the appropriate number of bytes to or from the operand CIR The read of the first primitive causes the response CIR encoding to be changed to the null primitive thus avoiding spurious request primitives i...

Page 291: ... and then the transfer multiple coprocessor registers primitive is issued In response to the transfer multiple coprocessor registers primitive the main processor reads the register list from the register select CIR and transfers one register for each bit that is set in the list Note that the register list can be equal to zero in which case no register transfer occurs The read of the transfer singl...

Page 292: ...e of an MC68882 are not idle a null primitive CA 1 IA I PC 0 TF 0 is returned and the main processor reads the response CIR again later This process of rereading the response CIR continues until the coprocessor is idle Note that it is possible for a pre instruction exception to be reported at any time during this process If no exception is reported and when the coprocessor is finally idle the copr...

Page 293: ...urns a format word that indicates the current state of the machine For most cases of this dialog with the MC68881 the first read of the save CIR returns the idle format word and the main processor then proceeds to transfer six long words from the operand CIR to memory In this dialog with the MC68882 the idle format word is followed by 14 long words Optionally the first primitive may be a null form...

Page 294: ...ng the effective address fetching a format word from that address and writing the format word to the restore CIR The main processor then reads the restore ClR to verify that the format word is valid During this read cycle the FPCP returns a format word that indicates if the format word that was written is valid for the current revision of the device If the format word is valid the same value that ...

Page 295: ...otocol violations is a hardware failure since the FPCPcannot return an illegal response primitive For FPCP detected protocol violations the cause is most likely a software failure that causes a new instruction to be initiated before the previous instruction dialog is completed In this case the new instruction dialog is aborted immediately but the previous instruction dialog may not terminate for s...

Page 296: ...would take the original exception again nesting the repetitions of the exception han dler Figure 7 30 shows the dialog that applies when an exception handler does not set the exception pending bit even though it begins with an FSAVE instruction and closes with an FRESTORE A protocol violation cannot occur in this case but because the exception pending bit is not set the instruction again takes the...

Page 297: ...33X NOt13fltilSNl 3 Jd IV1 _ ZO t l dd 0 1 O Od VO 77 N 3903 MON I3V N011d33X331EIM 3 N0aS3EIOV3td 0NVV 03 I IBM 3O03 MONN3 N011d 3X I311 M 0NV t O3 311YM NOt1313 SNi3003 0 O 3d NOIId 3X3 0 3d NOUd33X3 N0113fi815NI 3tJcl tVl O Od NOIIdDOX NOlJ 31 815NI 7 d IVl O Od NOIId OX3 NOllO SISN 3 d NVI 0 3ct NORd33X3 N0113nEIISNF3 J3WVl C0 05 Hd O V 0 Od 0 VO 77nN O 4 OO OO OO 5 s O t m _ X _ o __ u t 6u L...

Page 298: ...Vl O Od O VO 7InN o 3 NOI2EgOX 2 NOII flEISNI 91 M EXV1 0 0 NOUdgOX 3 NOIIOfl JSNI 9 d3 VI 0 3d N011d 3X N0 3nHiSNI Sd 3 V1 Z d O l O Od O O 7 FIN 0 O0 O0 o _ 2 e X I tJ e o r i o SNOd U O NOI 3nI LSNI JO Z I lIS I g 90 IN0 N 3V NOEd 3X 3_I O V 03 lld NOE3 S I 300330 tO O2J Z rl XZ f O lO 1Z C I G 1 fL _ C C 7 q t I O CO r t I O i O oi X UJ tJ j I p FREESCALE 7 34 MC68881 MC68882 USER S MANUAL ...

Page 299: ...andler changes the primitive to a null primitive Figure 7 33 shows the same case but with a specific instruction FMOVE FPm ea in the CU When the exception handler does not contain an FSAVEinstruction the take mid instruction exception primitive is not replaced by a null primitive and the next floating point instruction takes the exception again Figure 7 34 shows the dialog for a mid instruction ex...

Page 300: ...0 I 0 I M o I r o I t KULL CA O PC O IA O FF L TRANSFERS NfiIE MA N PROCESSOR REGISTER CA I PC DR O NULL CA t PC O IA I PF OJ O0 TAKE IO INST UCI ON I XCEPI IPC D TAKE I I STRUCflO V I XCEPTI PC O NULL CA O PC O IA O PF L NULL CA l PC O IA L PF O EVALUATE ea A D TRANSFER DATA CA I PC O DA I NULL CA O PC D A O PF t fFECCV 3 PASSPC TP NSFER E E STE I SU FJT 27 CF THEE UFt 3 z 3 FZ SFC SE EVALLL T c ...

Page 301: ... UJ UJ NO On suFaln w v p _ 1 3 001Vf0NOII3 81SNI 0 NOdS 81SUBJ l NDII3fl ISNI31 1 gQ IMON 3V NOE d 3X LI M 0dSJff 0 3ff NOILV 3dO031 3ff0 0Q SN0dS380V 8 gNVM 03 llgM N0113RH18NI 003 0 0 0 NO Ia33X3 NOIIC l JISNI II 7 VV oO O0 0 o o od NOIId3OX3 NOII gFI SNI OI Y ZVVj O 9d NO ldBOX9 NO lOl lSNl OlYl g vb l 0 3dl N011d 3X N01Z3fiUISNI 01V VJ I V3 O01Vl0NOll3n lSNI l dd Z VI O gd 0 VO 77 7N o 0 C 9 ...

Page 302: ...y valid method for checking the status of the FPCP is to execute the FSAVE instruction and examine the state frame that is generated followed by an FRESTORE instruction to reinstate the previous context of the FPCP 7 5 4 4 TAKE BSUN EXCEPTION This dialog is utilized by the FPCP when a conditional instruction is initiated by writing one of the IEEE nonaware conditional predicates to the condition C...

Page 303: ...n MC68030 based systems 7 5 4 5 F LINEEMULATOR EXCEPTION This dialog is utilized by the FPCPwhen a general instruction is initiated and the value written to the command CIR is not a legal FPCP command word encoding In this case the dialog consists of two write cycles and one read cycle as shown in Figure 7 38 First the main processor attempts to initiate a new instruction by writing to the command...

Page 304: ...an FSAVE or FRESTORE instruction prior to an attempt to execute a new FSAVE instruction If there is a possibility that a nested FSAVE might occur the MPU MOVES instruction might be used to read the save CIR before the FSAVE is executed If the value returned from the save CIR is the illegal format word then the new FSAVE should be postponed Reading the save CIR in this manner is not destructive 7 5...

Page 305: ... 2 o o_ J Figure 7 40 FRESTOREFormat Exception Dialog MC68881 MC68882 USER S MANUAL FREESCALE 7 41 ...

Page 306: ...7 FREESCALE 7 42 MC68881 MC68882 USER S MANUAL ...

Page 307: ...g instructions This section includes timing in formation that shows the amount of instruction overlap this concurrency provides 8 1 FACTORS AFFECTING EXECUTION TIMES When investigating instruction execution timing for the FPCP it is assumed that the fol lowing information is required in order to make informed engineering trade offs Best case instruction execution timings for determining whether or...

Page 308: ...tion time in communication with the main processor With this set of assumptions as a starting point several factors must be defined that contribute to the overall execution time for a given instruction Some of these factors are common to all instructions while others are only applicable to certain instructions or data types Particularly the execution times for the conditional and system control in...

Page 309: ... register indireCt An then no instruction prefetch words and one long word indirect address fetch may be required to calculate the final address of the operand Then once the operand is located up to three long word fetches may be required to transfer the operand to the FPCP The execution times for these operations are quite predictable i e there are no data dependencies involved although they are ...

Page 310: ...rocessor executes MPU instructions while the coprocessor completes execution of a floating point instruction The MC68882 can execute two floating point instructions concurrently providing additional concurrency not available in the MC68881 Overlap time between instructions determines the degree of concurrency that is possible Overlap time is derived from the combination of the tail of an instructi...

Page 311: ...ynchronously and they are handled on the next instruction boundary While the average interrupt latency for the MPU is quite short the maximum latency is often of critical importance since real time interrupts cannot require servicing in less than the maximum interrupt latency The max imum interrupt latency for the MPU is approximately 250 clock cycles for the MOVEM L d32 An Xn d32 D0 D7 A0 A7 inst...

Page 312: ...een these two values For nonconcurrent instructions the amount of time during which interrupts are allowed is shown in the tables as the number of allowed overlap clock cycles and the interrupt latency is approximately equal to the total execution time minus the allowed overlap time However as shown in Figure 8 1 there may be two separate time periods during which the MPU is not allowed to process...

Page 313: ... the response CIR to null CA 1 IA 1 causing the MPU to wait 4 The MPU continues to read the response CIR repeatedly until a new primitive is encoded or an interrupt becomes pending if an interrupt occurs the MPU resumes polling of the response CIR after the interrupt handler executes an RTE instruction 5 The MC68881 APU becomes idle by completing the previous instruction and waits for the next rea...

Page 314: ...umed thus a coprocessor interface overhead value of 11 clock cycles is included in the timing numbers If an attempt is made to optimize an instruction sequence for overlapped execution the coprocessor interface overhead may be reduced by as much as nine clock cycles However incorrect optimization may result in an 11 clock cycle overhead which is no worse than the no overlap case previously describ...

Page 315: ...X z I r D D r _l r Drid I c _1 t e I 13 O fJ O u O 3 U MC68881 MC68882 USER S MANUAL FREESCALE 8 9 ...

Page 316: ...numbers that depend on the context of the instruction i e the alignment of the instruction stream whether the MPU instruction cache is enabled and whether the cache contains the instruction 1 The best case value where prefetches hit in the MPU on chip cache and the instruction benefits from the maximum overlap in the MPU pipeline with other instructions Due to the highly volatile nature of the ins...

Page 317: ...xecution time for the selected instruction and a second table one of five listing the instruction groups is used to determine the additional time required for the calculation of the effective address by the MPU for those instructions that require an effective address calculation The second group of tables is used to calculate a more precise execution timing value for a specific instruction address...

Page 318: ...rform an address calculation implied by the transfer multiple coprocessor reg isters primitive For the FScc FRESTORE and FSAVE instructions the request to evaluate an effective address is implied by the F line instruction word therefore no response primitive is issued by the FPCPto request the evaluation The following table is used for these three instructions to adjust the basic instruction execu...

Page 319: ... 21 0 2 1 0 0 0 d32 B l d32 18 0 0 1 0 0 0 21 0 0 1 0 0 0 24 0 3 1 0 0 0 B Base address 0 An PC Xn An Xn PC Xn Form does not affect timing I lndex 0 or Xn NOTE Xn cannot be in B and I at the same time Scaling and size of Xn does not affect timing 8 5 1 3 MC68882 CONCURRENT OPERATIONS The MC68882 overall instruction timing table Table 8 3 contains the H and T numbers which are helpful in estimating...

Page 320: ...D 70 99 91 97 95 I 907 FMOVE to FPn 33 60 52 58 56 870 FMOVE to memory 100 80 86 72 2002 FMOVECR 29 I 9gS FNEG 35 62 54 FREM 100 129 121 FSCALE 41 70 62 69 FSGLDIV 90 J 96 80 I 125 94 i FSGLMUL 127 68 59 96 86 672 937 98 878 936 88 FSIN 391 418 410 FSINCOS 461 478 470 FSINH 714 706 FSQRT 126 134 667 107 FTST 33 896 416 414 1228 476 474 1288 712 710 1524 132 130 944 FSUB 51 80 72 78 76 i 883 FTAN 4...

Page 321: ... 6 40 40 6 45 13 809 891 0 0 110 44 44 50 50 0 02006 0 0 44 38 38 I FMOVE to memory 0 0 110 0 0 50 0 0 38 FMOVE to memory FTENTOX 0 0 2006 FMOVECR 10 0 32 FMUL 17 55 76 21 74 114 30 58 89 36 58 95 42 58 101 13 947 929 FNEG 17 17 38 21 28 68 30 20 51 36 20 57 42 20 63 13 811 893 FREM 17 84 105 21 103 143 30 87 118 36 87 124 42 87 130 13 876 958 FSCALE 17 25 46 21 44 84 30 28 59 36 28 65 42 28 71 13...

Page 322: ...ile waiting for the transfer to start For an MC62 881 if no interrupts occur the number of additional response CIR read cycles is 5 for integer 3 for singTeor double 1 for extended and 194 for packed For an MC68882 the number of additional response read cycles is 5 for integer and 194 for packed Instruction ea Time FMUL D ea FP1 6 Table 8 5 Timing Calculation Example MC68882 MC68881 Times Times Ad...

Page 323: ... less the actual overlap time The conclusion is that for the instruction sequence shown here the MC68881 required 1 80 times longer to execute compared to the MC68882 8 5 1 4 MOVE CONTROL REGISTER AND FMOVEM OPERATIONS Table 8 6 shows the execution times for the FMOVE FPcr and FMOVEM instructions The timing for the appro priate effective addressing mode must be added to the numbers in this table t...

Page 324: ... clock for condition false Add the appropriate effective address calculation time Since the conditional instructions are intrinsic to the M68000 Family coprocessor interface i e they are not defined by the FPCP through the use of response primitives the MPU performs most of the processing associated with these instructions The only part of the instruction that the FPCP performs is the evaluation o...

Page 325: ...pts 8 5 2 MC68881 Detail Timing Tables This set of tables provides the information needed to calculate a more precise execution time for an instruction executing in the MC68881 based on the input operand format and type than can be obtained with the typical timing tables shown previously Also these tables contain the information necessary to determine instruction execution timing for a system that...

Page 326: ... TRANSFER I ISTART UpI oa PREPARE I FRAME MC680201MC68030 I I 2 t I0 I M00 I 0 l I During this period the MC68881 may force the MC6802O MC68030 to wait while an internal operation is completed or reaches a point where a save operation can be performed Context RestoreOperation I I EVALUATE I TRANSFER I I MC 0 0 MC 0301S ARTUP I e FRAME C0NT NUE L l Eiiiiiii MC68881 10 When the context restore opera...

Page 327: ...ng numbers derived for them can be utilized by non MPU based system designers As a further aid to understanding the interaction of the MPU with the MC68881 during the execution of an instruction four diagrams are presented in Figures 8 4 and 8 5 The bus cycle activity and overlapped execution that is allowed during the communications dialog is shown in the diagrams in addition to illustrations of ...

Page 328: ...E 13CLOCKS It CLO S I OVERALLEXECDT 0N TZME 30 CLOCKS I CACHECASE ISEENOTE1 SEENOTE21 v C L O C K I I I I I I I I I I I I I I I I I I I I I I I I I l l l l i i i i i I I I i i I I I l l l l l l l l l i l l l l MC68020 J cpGEN FMOVE XFPm FPn WAITI MC68030 I j NULL CA 0 I SUBSE0 I I eYe E q o EA0 6 CLOCKS 12CLOCKS t2 CLOCKS OVERALLEXECUTION TIME 30 CLOCKS NOTES 1 These six clocks do not add to the o...

Page 329: ...n m m m R 5 o o c o a a _o a 0 o o o E Q o r U r ud 3 UL I D E X W O c o r 2 co O J m MC68881 MC68882 USER S MANUAL FREESCALE 8 23 ...

Page 330: ...igure 8 5 illustrates the execution of the FMOVE S An FPn instruction where the instruction is even word aligned the MPU cache is disabled and at least one of the arithmetic exceptions is enabled Under these conditions the cpGEN start up op eration is identical to the first diagram in Figure 8 4 except that the primitive returned by the MC68881 is evaluate effective address and transfer data with ...

Page 331: ...01011 1 14 6 010101111 17 9 1101011fl FBcc 12 6 0 0 0 1 1 14 6 0 0 0 1 1 14 6 0 0 0 1 I FDBcc FScc and FTRAPcc 12 6 0 0 0 1 1 14 6 0 0 0 1 1 17 9 1 01011 1 FSAVE 13 1 010111110 15 1 0 0 1 1 0 15 1 0 0 1 1 0 FRESTORE 16 4 0 1 0 1 1 18 4 0Ilf0 1 1 18 4 0 1 0 1 1 These execution time numbers represent the overall execution time for this operation with respect to the MPU and therefore are used to calc...

Page 332: ...erlaps with the input operand transfer and conversion operations by the FPCP and therefore is not added to the overall execution time for the instruction although these operations are included in the calculation of the effective execution time for the MPU Table 8 11 Operand Transfer Time External Operand Transfer Type Operand Format Byte word Long Single Double t Ex t Packed From MC68020 Dn 14 0 0...

Page 333: ...te cycle to the operand CIR For dyadic operations one portion of Table 8 13 for conversions from each combination of source data format and type versus destination data type is included For monadic operations one portion includes the conversion timing for any data format and type Only one number is listed in each entry since the total number of clock cycles required is equal to the number of overl...

Page 334: ... 36 38 Zero 24 42 28 30 32 Infinity 22 40 26 28 30 24 NAN 42 28 30 32 Dyadic Input Conversions Source O Jerand is Double Precision Zero Infinity NAN Source Not Destination Normalized Normalized Normalized 16 34 20 22 24 Unnormalized 28 48 32 34 36 Zero 22 40 26 I 28 30 J J Iofinity 20 38 24 I 28 i 28 NAN 22 40 26 I 28 i 3o Dyadic Input Conversions w Source O mrand is Extended Precision Destination...

Page 335: ...conversion time The minimum maximum conversion time is 954 clock cycles Monadic or Dyadic Input Conversions Source Operand is FPm e Normalized Not Normalized Zero Infinity NAN Normalized 14 30 16 16 18 Unnormalized 26 42 28 28 30 Zero 36 22 22 24 Infinity NAN 20 18 34 20 20 22 20 36 22 22 24 Monadic Input Conversions Source Operand is in Memory I Normalized Byte Word Long 22 24 Single 16 Double 14...

Page 336: ...rce and destination exponents are not equal FCMP Calculation Time Source Destination Normalized Zero Infinity Normalized CMP 6 6 CMP 8 6 6 8 Zero Infinity 8 6 6 8 8 6 6 8 NAN NAN4 NAN4 6 6 6 NAN4 NAN NAN1 NAN2 NAN2 NAN3 MP 8 if thesource exponent is greater than the desination exponent 10 if the source exponent is less than or equal to the destination exponent FDIV Calculation Time Source Destinat...

Page 337: ...culation Time e Normalized Zero Infinity NAN Normalized MUL Zero Infinity NAN NAN2 6 8 6 8 20 NAN2 6 8 20 6 8 NAN2 NAN 1 NAN2 NAN2 NAN3 MUL 46 if the intermediate result is normalized 48 if the intermediate result is not normalized FREM Calculation Time Source Destination Normalized Zero Infinity NAN Normalized Zero REM infinity NAN 6 NAN2 6 NAN2 20 NAN2 NAN2 NAN3 20 6 20 lOP 20 NAN1 NAN2 REM 18 i...

Page 338: ...ized Normalized NAN _ SGLDIV NAN2 Zero 6 8 NAN2 Infinity 6 8 RAN2 NAN NAN1 NAN3 Zero Infinity 6 8 2O 8 6 20 6 8 6 8 20 NAN2 NAN2 44 if no extendedpreclsion underflow or overflow occurs 62 if an extended precision overflow occurs 90 if an extended precision underflow occurs SGLDIV FSGLMUL Calculation Time Source Destination Normalized Normalized Zero I Infinity 6 6 8 8 6 8 20 20 6 8 NAN2 NAN2 NAN S...

Page 339: ...e nonzero input values is listed in a second table Table 8 17 The amount of time required to perform this conversion depends on the value and type of the input operand and the format of the desired output The values given in the following tables in FPCPclock cycles include the time from the fourth clock cycle of the first response CIR read which returns a null CA l IA l primitive to completion of ...

Page 340: ...2 6 20 NAN2 FLOG2 550 lOP 22 6 20 NAN2 FMOVE to FPn 2 6 6 NAN2 FMOVECR 181 262 FNEG 4 4 8 NAN2 t FSIN 360 3 6 20 NAN2 420 3 20 FSINCOS FSINH 26 656 NAN6 NAN2 FSQRT 76 lOP 6 6 20 NAN2 FTAN 442 3 6 20 NAN2 FTANH 630 6 8 NAN2 FTENTOX 536 536 FTST FTWOTOX NAN2 NAN5 NAN2 NOTES 1 If the extended precision rounding mode is used 2 If the single or double precision rounding mode is used This assumes that t...

Page 341: ...58 Overflow RM or RP Mode No Round Overflow 46 56 Overflow RM or RP Mode Round Overflow 50 60 Underflow No Round Overflow 66 76 Underflow Round Overflow 70 80 Table 8 18 Rounding Operation Time Values Rounding Result Clock Cycles Precision Extended Single or Double No Underflow Overflow or Round Overflow No Underflow or Overflow Round Overflow Underflow Overflow RN or RZ Mode No Round Overflow Ove...

Page 342: ...9 Exception Handling Time Values Exception Identifier lOP NAN 1 NAN2 NAN3 NAN4 NAN5 NAN6 NAN7 Conditions Source Operand is Not Denormalized Source Operand is Denormalized Destination is a QNAN Source is not Denormalized Destination is a QNAN Source is Denormalized Destination is an SNAN Source is not Denormalized Destination is an SNAN Source is Denormalized The NAN is a QNAN The NAN is an SNAN Bo...

Page 343: ...y the FPCP This value is shown in Table 8 20 in FPCP clock cycles and indicates the best case time from the start of the condition CIR write to the end of the response CIR read which are the only two coprocessor accesses required 8 5 2 8 MULTIPLE REGISTER TRANSFER Table 8 21 lists the number of clock cycles and bus cycles required for the MPU to perform a multiple register transfer to or from the ...

Page 344: ...store Idle Busy 35 0 0 6 0 06 270 0 0 45 0 0 45 Before the transfer of a state frame to the FPCPduring an FRESTORE instruction the MPU must read the format word from memory write it to the restore CIR and verify that it is valid by reading the restore CIR Likewise during an FSAVE instruction the MPU must read the format word from the save CIR and store it in memory The instruction start up timing ...

Page 345: ...uction exception the instruction start up time for the arithmetic or conditional instruction that is pre empted by the ex ception is added to the exception processing time from Table 8 24 The exception pro cessing time for a take mid instruction exception primitive is added to the overall execution time for the FMOVE to memory instruction that caused the exception For conditional instructions that...

Page 346: ...peration In addition to the occurrence of an exception whether exceptions are enabled or not can also affect instruction execution time This is because the FPCP requests the transfer of the program counter at the start of any arithmetic instruction if any exception other than the BSUN exception is enabled If the source operand resides in a floating point data register the transfer of the PC does n...

Page 347: ... used to indicate that a signal is inactive or false VCC GND CLK RESET 7 13 MC68881 MC68882 FLOATING POINT COPROCESSOR AO A4 DOoD31 R W OSACKO Figure 9 1 MC68881 MC68882 Input Output Signals 9 1 ADDRESS BUS A4 A0 These active high address line inputs are used by the main processor to select the copro cessor interface register locations located in the CPU address space These lines control the regis...

Page 348: ...path between the MC68020 MC68030 MPU and the FPCP Regardless of whether the FPCP is operating as a coprocessor or a peripheral processor all interprocessor transfers of instruction in formation operand data status information and requests for service occur as standard M68000 bus cycles The FPCP can operate with an 8 16 or 32 bit system data bus To operate with the required system data bus size bot...

Page 349: ...nals when the MPU asserts CS If the bus cycle is a r ain processor read the FPCP asserts DSACK1 and DSACK0 signals to indicate that the information on the data bus is valid Both DSACK signals can be asserted in advance of the valid data being placed on the bus If the bus cycle is a main processor write to the FPCP DSACK1 and DSACK0 are used to acknowledge acceptance of the data by the FPCP The FPC...

Page 350: ...SACK lines are then three stated placed in the high impedance state to avoid interference with the next bus cycle 9 9 RESET R E S This active low input signal causes the FPCPto initialize the floating point data registers to nonsignaling not a numbers NANs and clears the floating point control status and instruction address registers When performing a powerup reset external circuitry should keep t...

Page 351: ...cs of the power supplied to the part quite important The power supply must be as free from noise as possible and it mbst be able to supply large amounts of instantaneous current when the FPCP performs certain operations In order to meet these requirements more detailed attention should be given to the power supply connection to the FPCPthan is required for older NMOS devices that operate at slower...

Page 352: ...taneous current requirements of both the MPU and the FPCP In addition to the capacitive decoupling of the power supply care should be taken to ensure a low resistance connection between the FPCPVCC and GND pins and the system power supply traces In particular the connections to pins B7 and J8 the GND pins for the data bus pins must have very low resistance This is necessary because a read of the F...

Page 353: ... Size SIZE Input Low Address Strobe AS Input Low Chip Select CS Input Low Read Write R W Input High Low Data Strobe DS Input Low Data Transfer and Size Acknowledge DSACK1 DSACK0 Output Low Yes Reset RESET input Low Clock CLK Input Sense Device SENSE Input Output Low No Power input VCC Input Ground GND Input MC68881 MC68882 USER S MANUAL FREESCALE 9 7 ...

Page 354: ...9 FREESCALE 9 8 MC68881 MC68882 USER S MANUAL ...

Page 355: ...fer the entire operand Also if an FPCP port size of 8 or 16 bits is selected multiple bus cycles can be required to transfer items that can be transferred with a single cycle over a 32 bit port The communications mechanism utilized by the FPCPand the main processor uses a set of mail box registers called the coprocessor interface registers CIRs to move data in structions and control information be...

Page 356: ...r for each port size 10 1 1 32 Bit Port Size When SIZE and A0 are both high the FPCP port size is defined to be 32 bits In most cases this configuration is statically selected by connecting the SIZE and A0 pins directly to VCC although dynamic port size selection is possible ifthe proper timing constraints are followed for the SIZE and A0 pins Although this configuration selects a 32 bit port size...

Page 357: ...operand is transferred in a single bus cycle and is left aligned with the operand CIR All other operands are transferred through the operand CIR in 32 bit units until the entire item is transferred When multiple bus cycles are required to transfer an item the first operand CIR access transfers the most significant long word of the item each successive access transfers the next least significant lo...

Page 358: ... are transferred across D31 D24 All other operands are transferred through the operand CIR in 16 bit units until the entire item is transferred When multiple bus cycles are required to transfer an item the first operand CIR access transfers the most significant word of the item each successive access transfers the next least significant word For example when an extended precision number is moved t...

Page 359: ... significant word For example when an extended precision number is moved the first operand CIR access is used to transfer bits 95 88 of the operand the second access transfers bits 87 80 and the third through twelfth accesses transfer bits 79 72 71 64 63 56 55 48 47 40 39 32 31 24 23 16 15 8 and 7 0 respectively to complete the operand transfer Note that the manner in which the operand is read fro...

Page 360: ...l frame 5V S N 7 C A L S O 5 I P 0 W E R 0 N S Y S T E M i msrr MC68881 MC68882 Figure 10 3 FPCP Reset Logic Example 10 3 CHIP SELECT TIMING Most of the bus cycle timing requirements of the FPCPare straightforward with all signal timing following the normal M68000 Family conventions The only signal timing that is specific to the FPCPbus interface is the relationship of the assertion of chip select...

Page 361: ... FPCP tAVCS 10 ns maximum The 74AS02 and 74AS30 implementation shown in Figure 10 4 or a PAL implementation witha maximum decode delay time of 10 ns may be used For a 25 MHz and 33 MHz MPU FPCPsystem refer to EB116 entitled Chip Select Generation for a 33 33 MHz MC68030 Microprocessor and a 33 33 MHz MC68882 Floating Point Co processor A late chip select design can use slower and therefore less ex...

Page 362: ...17 O A B C Z J A15 C J 74AS02 74AS30 Cp IO001 74x521 A0 At FC0 A2 B2 FC A3 B3 A16 A4 E4 A17 A5 65 A18 A6 86 A19 A7 B7 I 0 2I 81 Up to seven coprocessors in the system Only one coprocessor in the system Decode Delay Times Programmable Array Logic PAL 10 25 ns max_ 74x00 74x138 combined propagation delay 9 5 12 8 ns max 74x521 compare delay 5 5 11 ns max 74AS02 74AS30cernbinedpropagationdelay 9 ns m...

Page 363: ...teristics of each bus cycle type for an AC parametric description of the FPCPbus interface refer to SECTION 12 ELECTRICAL SPECIFICATIONS In the following discussions the main processor is assumed to be an MC68020 or MC68030 with the FPCP and the MPU both driven by the same clock signal Thus the terminology and conventions used are identical to the bus description for the MPU This clock frequency r...

Page 364: ...select lines on each rising edge of the CLK signal When all three of these signals are sampled as asserted the FPCP latches certain internal state flags and uses those flags to determine the appropriate response primitive or format word to be placed on the data bus One and one half clock cycles later the FPCP begins to drive the data value onto the bus and asser the appropriate data transfer and s...

Page 365: ...DSACKx by the FPCP The assertion of DSACKx by the FPCPis triggered by the falling edge of the clock and the propagation delay for this assertion can be quite long slightly longer than one 16 67 MHz clock cycle under worst case system conditions Since the MPU samples DSACKx on the falling edge of the clock the assertion of DSACKx triggered by a given falling clock edge may not be completed ahead of...

Page 366: ...xcept the response and save CIRs as dual ported structures Thus the main processor can access these CIRs at the maximum speed regardless of the clock frequency of the FPCP while the FPCP internally accesses these CIRs in a synchronous manner The functional timing for the asynchronous read cycle is shown in Figure 10 7 The FPCP detects the start of an asynchronous read cycle when chip select addres...

Page 367: ...le The definition of asynchronous in the first paragraph of the preceding subsection applies also to asynchronous write cycles The functional timing for the asynchronous write cycle is shown in Figure 10 8 The FPCP detects the start of an asynchronous write cycle when chip select and address strobe are asserted and read write is low When this condition is met and an asserted pulse occurs on D S th...

Page 368: ...ternal oper ations are completed Synchronous accesses i e accesses to the response or save CIR execute in the normal manner regardless of preceding accesses The following is a list of the bus cycles that initiate internal operations on the negated edge of DS where a sub sequent asynchronous bus cycle might overrun the FPCPand necessitate a delay in the assertion of DSACKx 1 A write cycle to the le...

Page 369: ...hus the access to the command CIR is deemed illegal and a protocol violation occurs In this case if the main processor follows the protocol and services the come again request by reading the response CIR immediately after the last operand CIR access a null CA 1 IA 1 primitive may be returned by the MC68881 Since the response CIR read cycle timing is synchronous with the MC68881 clock signal this r...

Page 370: ...10 FREESCALE 10 16 MC68881 MC68882 USER S MANUAL ...

Page 371: ... Coprocessor Connection Figure 11 1 illustrates the coprocessor interface connection of an FPCP to an MPU using a 32 bit data bus The FPCP is configured to operate over a 32 bit data bus when both the A0 and SIZE pins are connected to VCC CHIP SELECT 1 coD I FCO FC2 A20 A31 t AI6 AI9 AI3 A15 1 A5 A12 A1 A4 A0 OS R W 024 D31 O16 023 41 D8 D15 91 00 07 DSACKO ql OSACK1 VCC VCC II IP Ib E1 SIZE A1 A4...

Page 372: ...B A12 A1 A4 AO D24 D31 D16 D23 OB 015 DO D7 OSACKO DSACK j I CHIP L____ VCC G N D z ZE A1 A4 AO R W D24 D31 016 D23 08 D15 D0 07 D S A C K O DSACKI f t MAINPROCESSDR COPROCESSOR CLOCK CLOCK Figure 11 2 16 Bit Data Bus Coprocessor Connection 11 1 3 8 Bit Data Bus Coprocessor Connection Figure 11 3 illustrates the connection of an FPCP to an MPU as a coprocessor over an 8 bit data bus The FPCP is co...

Page 373: ...when the SIZE pin is connected to VCC and the A0 pin is connected to GND The 16 least significant data pins D15 D0 must be connected to the 16 most significant data pins D31 D16 when the FPCP is configured to operate over a 16 bit data bus i e connect DO to D16 D1 to D17 and D15 to D31 The DSACK1 pin of the FPCP is connected to the DTACK pin of the main processor and the DSACK0 pin is not used Whe...

Page 374: ...system dependent and the CS must be decoded in the supervisor or user data spaces 11 3 PERIPHERAL PROCESSOR OPERATION The FPCP can be used as a peripheral processor on systems where the main processor does not have a coprocessor interface by using instruction sequences that emulate the protocol of the coprocessor interface When an FPCP instruction is encountered by an MC68000 MC68008 or MC68010 th...

Page 375: ... AI A4 A0 O0 O7 OTACK GND t MC68881 MC68882 Al A4 A0 1 R N ii O24 D31 16 023 08 015 DO B7 os t t MAIN PROCESSOR COPROCESSOR CLOCK CLOCK Figure 11 5 8 Bit Data Bus Peripheral Processor Connection MC68881 MC68882 USER S MANUAL FREESCALE 11 5 ...

Page 376: ...11 FREESCALE 11 6 MC68881 MC68882 USER S MANUAL ...

Page 377: ...SIDERATIONS The average chip junction temperature Tj in C can be obtained from Tj TA PD 0JA where TA 0JA PD PINT PI O 1 Ambient Temperature C Package Thermal Resistance Junction to Ambient C W PINT PI O ICCx VCC Watts Chip Internal Power Power Dissipation on Input and Output Pins User Determined For most applications PI O PINT and can be neglected The following is an approximate relationship betwe...

Page 378: ...sign purposes only Thermal measurements are complex and dependent on procedure and setup User derived values for thermal resistance may differ 12 4 DC ELECTRICAL CHARACTERISTICS Vcc 5 0 Vdc 5 GND 0 Vdc TA 0 C to 70 C symbol l Ms I Characteristic Input High Voltage VIH I 2 0 i Input Low Voltage VIE IGND 0 5 I Input LeakageCurrent 5 25 V CLK RESE_ T RNV __A0 AA_ 4 lin I CS DS AS SIZE J Hi Z Off Stat...

Page 379: ... Min Max 8 16 67 12 5 20 12 5 25 16 7 33 33 60 125 50 80 40 80 30 60 24 95 20 54 15 59 14 66 Unit MHz ns ns 5 5 4 3 ns CLOCK NOTE 1 Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltageof 2 0 volts unless otherwise noted The voltageswing through this range should start outside and pass through the range such that the rise or fall will be linear between 0 8 vo...

Page 380: ...0 I0 10 Negated to R W Low Read or D S 10 Negated to R High Write DS Width Asserted Write 40 DS Width Negated 40 DS Negated to AS Asserted 30 CS DS Asserted to Data Out Valid Read DS Negated to Data Out Invalid Read 0 DS Negated to Data Out High Impedance Read Data In Valid to DS Asserted Write 15 DS Negated to Data In Invalid Write 15 START True to DSACKO and DSACK1 Asserted DSACK0 Asserted to DS...

Page 381: ...ccur only when the save or response CIR locations are read 4 This specification only applies to systems in which back to back accesses read write or write write of the operand CIR can occur When the MC68882 is used as a coprocessor to the MC68020 MC68030 this can occur when the addressi mode is Immediate 5 If the SIZE pin is not strapped to either VCC or GND it must have the same setup times as do...

Page 382: ...12 FREESCALE 12 6 MC68881 MC68882 USER S MANUAL ...

Page 383: ...z Temperature Pin Grid Array 12 5 RC Suffix Order Number 16 67 20 0 C to 70 C MC68881RC12 40 C to 85 C MC68881LRC12 55 C to 125 C MC68881ERC12 0 C to 70 C MC68881RC16 40 C to 85 C MC68881LRC16 55 C to 125 C MC68881ERC16 25 0 C to 70 C MC68881RC20 40 C to 85 C MC68881LRC20 55 C to 125 C MC68881ERC20 Pin Grid Array 33 33 RC Suffix 16 67 20 25 0 C to 70 C MC68881RC25 O Ctp 70 C MC68882RC33 O Cto 70 C...

Page 384: ...D D12 D15 0 0 0 0 0 0 GND CLK GND D9 D13 D14 0 0 0 o 0 0 o o 0 0 VCC GND GND SE D2 D5 GND VCC D10 Dll 0 0 0 0 0 0 0 0 0 0 JCC 6ND DO D1 D3 D4 DB D7 D8 GND 1 2 3 4 5 6 7 8 9 10 Pin Group VCC GND D31 D16 H8 JB D15 DO0 B8 B7 Internal Logic E2 E9 DSACK1 DSACK0 Separate C1 E ra A1 B1 J2 A10 D2 F2 H9 A2 B2 B3 134 C3 E10 K3 New assignment for the A93N mask Reserved for future Freescaleuse SENSE pin may b...

Page 385: ...MSANDT S DATUMSURFACE 2 POSITIONALTOLERANCEFORLEADS pLACES 3 MENSIONING AN TOLERANCING B ANSI YI4 M I 4 CONTROLLING DtMEN ON iNCH MIM IIIETIERS INCHES M i WN MAX N mX A 2S S7 27 17 1 050 1 070 B 26 67 27 17 1 050 1 070 C 1 91 2 r 0 075 o os o o 43 oso o 017 0 02 G 2 BSC o 100BSC K 4 32 I 4 82 0 170 I 0190 MC68881 MC68882 USER S MANUAL FREESCALE 13 3 ...

Page 386: ...13 FREESCALE 13 4 MC68881 MC68882 USER S MANUAL ...

Page 387: ...uble and extended precision The numerical value of the bit string is the signed product of the significand and two raised to the power of the exponent DENORMALIZED NUMBER A floating point number having all zeros in the exponent and a non zero value in the fraction mantissa DOUBLE PRECISION A 64 bit binary floating point operand format composed of three fields a one bit sign field an 11 bit biased ...

Page 388: ...nt numbers FRACTION F FIELD The field of the significand that lies to the right of its implied binary point INTEGER Any of the natural numbers the negatives of these numbers or zero MANTISSA Mantissa and significand are interchangeable throughout this manual See significand MODULO A mathematical operation that yields the remainder of division Thus 39 modulo 6 3 MONADIC OPERATION An operation on on...

Page 389: ...ight of the implied binary point Significand and mantissa are interchangeable throughout this manual See fraction F field SINGLE PRECISION A 32 bit binary floating point operand format composed of three fields a one bit sign field an 8 bit biased exponent field and a 23 bit fraction significand field TRANSCENDENTAL Being involving or representing a function sine x log x that cannot be expressed by...

Page 390: ...A FREESCALE A 4 MC68881 MC68882 USER S MANUAL ...

Page 391: ...ordered cc Condition code CLK Clock CMP Compare cp Coprocessor CPU Central processor unit CPRED Conditional predicate CS Chip select CU Conversion unit d Displacement D Data D Double precision binary real floating point DIV Divide DMA Direct memory access DS Data strobe DSACK Data and size acknowledge DZ Divide by zero e Exponent ea Effective address EQ Equal EXC Exception EXP Exponent ENAB Enable...

Page 392: ...8881 MC68882 coprocessor Floating point set Floating point Floating point Floating point Floating point Floating point Floating point Floating point Floating point Floating point Floating point Floating point Floating point branch branch equal branch greater than branch less than or equal branch not equal set equal set on greater than set on less than or equal set not equal set on not greater than...

Page 393: ...greater or less or equal NGT Not greater than NLE Not less than or equal NLT Not less than OGE Ordered greater than or equal OGL Ordered greater or less than OGT Ordered greater than OLE Ordered less than or equal OLT Ordered less than OPERR Operand error OR Ordered OVFL Overflow P PC Packed binary coded decimal real string Program counter QUOT Quotient R W Read write REM Remainder RM Round toward...

Page 394: ...ing true Subtract T T TTL Trap True Transistor transistor logic UEQ UGE UGT ULE ULT UN UNFL Unordered or equal Unordered or greater or equal Unordered or greater Unordered or less or equal Unordered or less than Unordered Underflow W Word integer x X Don t care irrelevant Extended precision binary real floating point Z Zero Hexadecimal inf Positive infinity inf Negative infinity FREESCALE B 4 MC68...

Page 395: ...11 2 11 3 A13 A15 Signals 10 7 A16 A19 Signals 10 7 roB Benchmark Linpack 5 10 5 11 Binary RealFormats 3 2 Bit CA 7 10 DR 7 10 EXC PEND 5 11 6 35 INDEX Bit Continued IA 7 11 PC 7 11 PF 7 11 TF 7 11 BIU 1 6 Flags 5 11 6 32 6 33 Block Diagram MC68881 1 7 MC68882 1 8 Branch Set on Unordered Exception 6 5 BSUN Exception 6 5 Dialog 7 33 7 36 Bus Address 7 2 9 1 10 1 10o4 10 6 11 2 11 3 Arbitration Proc...

Page 396: ...E Exception 6 19 Trap 6 19 Computational Accuracy 4 5 Concept Coprocessor 1 2 ConcurrencY Instruction 5 1 MC68881 FMUL and FMOVE Instruction 5 7 MC68881 FMUL Instruction 5 2 MC68882 FMUL and FMOVE Instruction 6 8 Concurrent Floating Point Computations 5 1 5 2 Instruction Execution 8 4 Integer Computations 5 1 Operations MC68882 8 13 Condition CIR 6 20 6 25 6 35 7 5 7 7 7 19 7 35 8 7 8 18 8 25 8 36...

Page 397: ...tion 7 22 7 23 MC68882 7 24 OPCLASS011 Instruction 7 24 7 25 MC68882 7 26 OPCLASS100 Instruction 7 26 7 27 OPCLASS101 Instruction 7 26 7 27 OPCLASS110 Instruction 7 27 7 28 OPCLASS111 Instruction 7 27 7 28 Register to External Instruction 7 22 7 23 MC68882 7 26 Register to RegisterInstruction 7 22 RESTOREInstruction 7 30 Take BSUN Exception 7 38 Take Mid Instruction Exception 7 32 MC68881 7 34 MC6...

Page 398: ... 5 Handler Code 5 11 Handlers MC68882 6 28 Handling Times 8 36 Processing 5 14 6 1 Dialogs 7 30 Times 8 39 Recovery 6 22 Status Byte 1 4 2 6 6 4 Vector Assignments 6 4 Numbers 7 17 Exceptions Coprocessor Detected 6 2 MPU Detected 6 24 Multiple 6 19 Execution Times Conditional Instructions 8 18 FMOVEFPcr and FMOVEMInstructions 8 17 FSAVEand FRESTOREInstructions 8 19 MC68882FMOVEInstructions 5 10 Ex...

Page 399: ...at Exception Dialog FRESTORE Instruction 7 41 FSAVE instruction 7 40 Format Summary 1 12 1 13 Format Word Definitions 6 37 Formats Binary Real 3 2 Data 1 11 3 1 Floating Point 1 11 3 2 Integer 1 11 3 1 State Frame 6 29 FPCC 2 4 FPCR 2 2 2 3 6 4 6 19 10 6 FPIAR Register 2 8 6 23 7 8 7 27 7 28 7 39 FPSR 2 4 2 6 6 4 6 18 10 6 FRESTOREInstruction Dialog 7 30 Format 4 137 Exception Dialog 7 40 Overview...

Page 400: ...ip Select Logic Example 10 9 Timing 10 9 Latency Interrupt 8 5 Linpack Benchmark 5 10 5 11 Loops MC68882Instruction 5 9 M Mantissa Sizes 1 11 Maximum Ratings 12 1 MC68881 Arithmetic Operation Timing 8 14 Block Diagram 1 7 Busy State FrameFormat 6 30 Detail Timing Tabtes 8 19 FMUL and FMOVEInstruction Concurrency 5 7 FMUL Instruction Concurrency 5 2 Idle State FrameFormat 6 30 Instruction Overlap E...

Page 401: ...ASS 100 Instruction Dialog 7 26 7 27 OPCLASS 101 Instruction Dialog 7 26 7 27 OPCLASS 110 Instruction Dialog 7 27 7 28 OPCLASS 111 Instruction Dialog 7 27 7 28 Operand Address CIR 7 8 Operand Alignment Data Bus 10 2 Operand CIR 5 4 6 20 6 34 6 36 7 3 7 4 7 7 7 13 7 29 7 40 10 3 10 5 10 14 10 15 Operand Errors 6 7 Exception 6 7 Operand Transfer Times 8 26 Operation Peripheral Processor 11 4 Reset 1...

Page 402: ... 3 10 6 10 12 Recovery Exception 6 22 Register Conflicts MC68882 5 9 Coprocessor Interface 1 8 7 2 7 3 9 2 10 1 Floating Point Control 2 2 2 3 6 4 6 18 10 5 Data 2 1 Field Encoding 4 127 Instruction Address 2 8 6 22 7 7 7 27 7 28 7 35 Status 2 4 2 7 6 4 6 19 10 5 FPIAR 2 8 6 23 7 8 7 27 7 29 7 39 Register Select CIR 6 21 7 7 7 15 7 27 10 3 10 14 Register to External Instructions 4 129 Dialog 7 24 ...

Page 403: ... Pre lnstruction Exception 7 18 Start Up PhaseTiming 8 3 Times Instruction 8 25 State Frame Busy 6 35 Formats 6 29 Idle 6 32 Null 6 32 Sizes 5 10 Transfer Times 8 38 Summary Context Switching 6 39 DataTypes 3 7 Format 1 12 1 13 Instruction Format 4 141 4 150 ResponsePrimitive 7 19 Signal 9 7 Switching Context 6 28 Synchronous ReadCycles 10 9 Timing 10 10 System Control Instructions 4 5 T Tables Ex...

Page 404: ...ngle Main Processor Register Primitive 7 14 Format 7 14 Transfers Interprocessor 7 8 Types CPU Space 7 2 Data 3 3 3 13 Typical Coprocessor Configuration 1 6 Execution Timing Assumptions 8 11 U Undefined Command Word 4 133 Underfiow Exception 6 11 Processing 4 15 UNFL Exception 6 11 Unit Bus Interface 1 6 Vw Valid Effective Address Codes 7 14 VCC Decoupling 9 6 Pin Asskjnments 9 6 Vector Numbers Ex...

Page 405: ...MC68881 MC68882 USER S MANUAL FREESCALE Foldout 1 MC68881 MC68882 USER S MANUAL FREESCALE Foldout 2 MC68881 MC68882 USER S MANUAL FREESCALE Foldout 3 ...

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Page 409: ... Programming Model Operand Data Formats Instruction Set Coprocessor Programming Exception Processing Coprocessor Interface Instruction Executive Timing Functional Signal Descriptions Bus Operation Interfacing Methods Electrical Specifications Ordering Information and Mechanical Data Glossary Abbreviations and Acronyms Index ...

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