MC13192/MC13193 Technical Data, Rev. 2.7
6
Freescale Semiconductor
Data Transfer Modes
4.3 Transmit Path Description
For the transmit path, the TX data that was previously stored in RAM is retrieved (packet mode) or the TX
data is clocked in via the SPI (stream mode), formed into packets per the 802.15.4 PHY, spread, and then
up-converted to the transmit frequency.
If the MC13192/MC13193 is in packet mode, data is processed as an entire packet. The data is first loaded
into the TX buffer. The MCU then requests that the MC13192/MC13193 transmit the data. The MCU is
notified via an interrupt when the whole packet has successfully been transmitted.
In streaming mode, the data is fed to the MC13192/MC13193 on a word-by-word basis with an interrupt
serving as a notification that the MC13192/MC13193 is ready for more data. This continues until the
whole packet is transmitted.
Figure 3. MC13192 Simplified Block Diagram
P has e S hift M odulator
R ST
G PIO 1
G PIO 2
G PIO 3
G PIO 4
XT A L2
XT A L1
R F IN -
R F IN +
P AO +
PAO -
M O SI
M ISO
SP IC LK
R XT XEN
C E
AT T N
G PIO 5
G PIO 6
G PIO 7
R ec eiv e
Pac k et R A M
T rans m it
P ac k et R AM 1
T rans m it R AM
Arbiter
R ec eiv e R AM
Arbiter
P A
V CO
C ry s t a l
O s c illa to r
S y m bol
G eneration
F C S
G eneration
Header
G eneration
MU
X
Sequenc e
M anager
(C ontrol Logic )
V D D L O 2
÷
4
256 M Hz
2.45 G Hz
LN A
1s t IF M ix er
IF = 65 M Hz
2nd IF M ix er
IF = 1 M Hz
PM A
Dec im ation
F ilter
M atc hed
F ilter
Bas eband
M ix er
DC D
C
or
relat
or
Sy
m
bol
Sy
nc
h &
D
et
C C A
Pac k et
P roc es s or
IR Q
A rbiter
24 Bit Ev ent T im er
IR Q
16 M Hz
AG C
Analog
R egulator
VBA T T
Digital
R egulator L
Digital
R egulator H
Pow er-U p
C ontrol
Logic
C ry s tal
R egulator
VC O
R egulator
VDDIN T
Program m able
Pres c aler
C LKO
4 Program m able
T im er C om parators
Sy nthesizer
VDDD
VDDVC O
SE
R
IA
L
PE
R
IPH
ER
AL
IN
TE
R
FA
C
E
(SP
I)
V DDA
VDDLO 1
T rans m it
P ac k et R AM 2