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Freescale Semiconductor MC13192, Technical Data Manual, Page: 16 / 22

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Freescale Semiconductor MC13192 Technical Data Manual Download Page 16

MC13192/MC13193 Technical Data, Rev. 2.7

16

Freescale Semiconductor

Pin Connections

Figure 9. Pin Connections (Top View)

1

2

3

GPIO3

GPIO2

GPIO1

RST

RXT

XEN

A

TTN

CL

KO

SPICLK

4

5

6

7

8

NC

RFIN+

NC

PAO+

PAO-

NC

GPIO4

RFIN-

VDDINT

GPIO5

VDDD

IRQ

CE

MISO

MOSI

GPIO6

12

13

14

15

16

11

10

9

24

23

22

21

20

19

18

17

VDDA

VBA

T

T

VDDVCO

VDDL

O1

VDDL

O2

XT

AL2

XT

AL1

GPIO7

EP

29

28

27

26

25

30

31

32

MC13192/
MC13193

Summary of Contents for MC13192

Page 1: ...udes the 802 15 4 PHY MAC for use with the HCS08 Family of MCUs The MC13193 also includes the 802 15 4 PHY MAC plus the ZigBee Protocol Stack for use with the HCS08 Family of MCUs With the exception o...

Page 2: ...gulation and full spread spectrum encoding and decoding The device supports 250 kbps Offset Quadrature Phase Shift Keying O QPSK data in 2 0 MHz channels with 5 0 MHz channel spacing per the IEEE 802...

Page 3: ...rk and application software as required reside on the host processor The host can vary from a simple 8 bit device up to a sophisticated 32 bit processor depending on application requirements 4 Data Tr...

Page 4: ...the transmitted data which generates a Cyclical Redundancy Check CRC result Link Quality is measured over a 64 s period after the packet preamble and stored in RAM If the MC13192 MC13193 is in packet...

Page 5: ...2 7 Freescale Semiconductor 5 Figure 2 Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator 85 75 65 55 45 35 25 85 75 65 55 45 35 25 15 Input Power Level dBm Reported P...

Page 6: ...a This continues until the whole packet is transmitted Figure 3 MC13192 Simplified Block Diagram Phase Shift M odulator R ST GPIO1 GPIO2 GPIO3 GPIO4 XT AL2 XT AL1 R F IN R F IN PAO PAO M OSI M ISO SPI...

Page 7: ...Analog Receiver MC13192 MC13193 Frequency Generation Analog Transmitter Voltage Regulators Power Up Management Control Logic Buffer RAM Digital Transceiver SPI and GPIO Microcontroller SPI ROM Flash R...

Page 8: ...Electrical Characteristics or Recommended Operating Conditions tables Note Meets Human Body Model HBM 2 kV and Machine Model MM 200 V except RFIN 100 V MM PAO 50 V MM 1 kV HBM and VBATT 100 V MM RF ou...

Page 9: ...VIL 0 30 VDDINT V Input High Voltage all digital inputs VIH 70 VDDINT VDDINT V Output High Voltage IOH 1 mA All digital outputs VOH 80 VDDINT VDDINT V Output Low Voltage IOL 1 mA All digital outputs...

Page 10: ...aracteristic Symbol Min Typ Max Unit Power Spectral Density 40 to 85 C Absolute limit 47 30 dBm Power Spectral Density 40 to 85 C Relative limit 20 40 Nominal Output Power 2405 2480 MHz with Register...

Page 11: ...er number of bursts 2 SPI Clock SPICLK The host drives the SPICLK input to the MC13192 MC13193 Data is clocked into the master or slave on the leading rising edge of the return to zero SPICLK and data...

Page 12: ...gisters to internal registers and memory 6 2 1 SPI Burst Operation The SPI port of an MCU transfers data in bursts of 8 bits with most significant bit MSB first The master MCU can send a byte to the s...

Page 13: ...ough the SPI bus is capable of sending data simultaneously between master and slave the MC13192 MC13193 never uses this mode The number of data bytes payload will be a minimum of 2 bytes and can exten...

Page 14: ...ut Output General Purpose Input Output 1 When gpio_alt_en Register 9 Bit 7 1 GPIO1 functions as an Out of Idle indicator 12 RST Digital Input Active Low Reset While held low the IC is in Off Mode and...

Page 15: ...stal Reference oscillator input Connect to 16 MHz crystal and load capacitor 27 XTAL2 Input Output Crystal Reference oscillator output Note Do not load this pin by using it as a 16 MHz source Measure...

Page 16: ...onnections Top View 1 2 3 GPIO3 GPIO2 GPIO1 RST RXTXEN ATTN CLKO SPICLK 4 5 6 7 8 NC RFIN NC PAO PAO NC GPIO4 RFIN VDDINT GPIO5 VDDD IRQ CE MISO MOSI GPIO6 12 13 14 15 16 11 10 9 24 23 22 21 20 19 18...

Page 17: ...contain a reference divider so 16 MHz is the only frequency that can be used A crystal requiring higher load capacitance is prohibited because a higher load on the amplifier circuit may compromise its...

Page 18: ...The 16 MHz crystal should be mounted close to the MC13192 MC13193 because the crystal trim default assumes that the listed KDS Daishinku crystal see Table 10 and the 6 8 pF load capacitors shown are u...

Page 19: ...hm1 C10 10pF L3 8 2nH MISO C5 6 8pF SS IC1 MC13192 14 19 15 11 10 9 8 25 23 24 20 18 17 6 5 1 2 12 13 7 16 4 3 26 27 31 32 21 22 29 28 30 EP ATTNB CEB CLKO GPIO1 GPIO2 GPIO3 GPIO4 GPIO7 GPIO5 GPIO6 IR...

Page 20: ...IC2 PG2012TK E2 NEC 9 1 J1 SMA Receptacle Female 10 1 L1 6 8 nH 11 2 L2 L3 8 2 nH 12 1 R1 470 k 13 2 R2 R3 0 14 1 X1 16 000 MHz Type DSX321G ZD00882 KDS Daishinku Corp 15 2 Z1 Z2 LDB212G4020C 001 Mur...

Page 21: ...ION DETAIL N 0 60 0 24 0 60 0 24 4 DETAIL N CORNER CONFIGURATION OPTION DETAIL T DETAIL M BACKSIDE PIN 1 INDEX OPTION DETAIL T BACKSIDE PIN 1 INDEX OPTION 90 5 2X 2X 0 39 0 31 0 1 0 0 DETAIL M BACKSID...

Page 22: ...or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by cu...

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