Instruction Model
e200z3 Power Architecture Core Reference Manual, Rev. 2
3-4
Freescale Semiconductor
rfci, rfdi, rfi—no longer mask bit 62 of CSRR0, DSRR0, or SRR0 respectively. The destination address
is [D,C]SRR0[32:62] || 0b0.
bclr, bclrl, bcctr, bcctrl—no longer mask bit 62 of the LR or CTR respectively. The destination address
is [LR,CTR][32:62] || 0b0.
3.6 Memory Access Alignment Support
The e200z3 core provides hardware support for unaligned memory accesses. However, there is a
performance degradation for accesses that cross a 64-bit (8 byte) boundary. For these cases, the
throughput of the load/store unit is degraded to one misaligned load every 2 cycles. Stores misaligned
across a 64-bit (8 byte) boundary can be translated at a rate of 2 cycles per store. Frequent use of
unaligned memory accesses is discouraged because of the impact on performance.
Note:
Accesses that cross a translation boundary may be restarted. A misaligned
access that crosses a page boundary is restarted in its entirety in the event
of a TLB miss of the second portion of the access. This may result in the
first portion being accessed twice.
Accesses that cross a translation boundary where endianness changes cause
a byte-ordering data storage interrupt.
3.7
Memory Synchronization and Reservation Instructions
lists the e200z3 implementation details for the memory synchronization and load and store with
reservation instructions.
Table 3-4. Memory Synchronization and Reservation Instructions—e200z3-Specific Details
Instruction
e200z3 Implementation
msync
Provides synchronization and memory barrier functions.
msync
completes only after all preceding instructions and
data memory accesses complete. Subsequent instructions in the stream are not dispatched until after the
msync
ensures these functions have been performed.